Abstract: Multi-processor computer systems with multiple levels of cache memories are slowed down in trying to process software locks for common functions. This invention obviates the problem for the vast majority of transactions by providing an alternate procedure for handling so-called communal locks differently from ordinary software locks. The alternative procedure is not used for ordinary (non communal software lock) data and instruction transfers. The function of the CSWL (Communal SoftWare Lock) is actually accomplished at a specific cache to which an individual CSWL is mapped to, rather than sending the lock to the requesting process, which also enhances efficiency.

Abstract: A backup and archiving system by means of tape cassettes is proposed which avoids bottlenecks at a higher performance level [that may be] caused by a central working storage especially during backup and archiving procedures. Such a backup and archiving system provides a distributed hardware architecture in which several Component Computers (6) work without reciprocal obstruction.

Abstract: A method and apparatus are described for protecting cache lines allocated to a cache by a run-ahead prefetcher from premature eviction, preventing thrashing. The invention also prevents premature eviction of cache lines still in use, such as lines allocated by the run-ahead prefetcher but not yet referenced by normal execution. A protection bit indicates whether its associated cache line has protected status in the cache or whether it may be evicted.

Abstract: A process and system for analyzing executable portion of computer code for processors with unprotected pipelines is provided. The process assumes a worst set of current processor states; analyzes plural control paths for possible hazards by computing an induced set of processor states after executing a computer instruction; and adjusts the worst set of current processor states based on program annotations to the computer instruction.

Abstract: A cache way replacement technique to identify and replace a least-recently used cache way. A cache way replacement technique in which a least-recently used cache way is identified and replaced, such that the replacement of cache ways over time is substantially evenly distributed among a set of cache ways in a cache memory. A least-recently used cache way is identified in a cache memory having a non-binary number of cache ways.

Abstract: A method and apparatus for the optimization of memory read operations via read launch optimizations in memory interconnect are disclosed. In one embodiment, a write request may be preempted by a read request.

Abstract: A method and system for upgrading a programmable battery unit in a mobile information handling system. The method and system make use of unique address words, checks, and comparisons stored in memory in order to allow upgrades in the battery unit. Non-reprogrammable section provides security in calculating checksums of addresses in the non-reprogrammable section and programmable section of memory.

Abstract: A system and method to reduce the time for system initializations is disclosed. In accordance with the invention, data accessed during a system initialization is loaded into a non-volatile cache and is pinned to prevent eviction. By pinning data into the cache, the data required for system initialization is pre-loaded into the cache on a system reboot, thereby eliminating the need to access a disk.

Abstract: A software tool automatically places files and folders of a software program within segments of a DVD. The segments are defined by security placeholders, and the disposition of the placeholders is initially randomly determined, consistent with predefined rules. The placeholders are included on the disc to hinder unauthorized copying. A developer generally defines the order in which the files and folders are to be laid out, and the software tool automatically places the files and folders, filling successive segments and shifting the placeholders to accommodate files that will not fit in a current segment. However, any movement of the placeholders must be done by the tool and is only permitted if the new disposition of the placeholder is in accord with the predefined rules. A user can manually modify the automated layout, and in response, the files and folders are automatically shifted to accommodate the changes introduced by the user.

Abstract: A system having RAID levels includes a storage medium, a memory and a CPU. The storage medium has at least two disks. The memory stores a striping zone information table of total disks in which a physical address of data recorded in a disk of the storage medium is converted into a logic address. The CPU modifies a striping zone information table stored in the memory in case a new disk is added to the storage medium, stores the modified striping zone information table in the memory, converts a logic address of data to be written/read out from the stored table into a physical address in response to the disk writing/reading instructions, searches positions of a corresponding disk D and a physical block B and controls writing or reading out data.

Abstract: A system and methods implemented within a multi-level RAID (redundant array of independent disks) storage array operate to initially write data to a lower performing RAID level within the array. In addition, data is migrated between lower and higher performing RAID levels via data migration processes that function as background processes. Benefits of the disclosed system and methods include a non-disruptive environment for servicing host I/O (input/output) requests. Array response times are significantly reduced by not allowing initial data writes to interfere with higher performing RAID levels and by migrating data between lower and higher performing RAID levels in the background when the array is less busy servicing host I/O requests.

Abstract: One embodiment of the present invention provides a system that implements a last-in first-out buffer. The system includes a plurality of cells arranged in a linear array to form the last-in first-out buffer, wherein a given cell in the interior of the linear array is configured to receive get and put calls from a preceding cell in the linear array, and to make get and put calls to a subsequent cell in the linear array. If the given cell contains no data items, the given cell is configured to make a get call to retrieve a data item from the subsequent cell. In this way the data item becomes available in the given cell to immediately satisfy a subsequent get call to the given cell without having to wait for the data item to propagate to the given cell from subsequent cells in the linear array. If the given cell contains no space for additional data items, the given cell is configured to make a put call to transfer a data item to the subsequent cell.

Abstract: In accordance with one embodiment, a method re-orders requests for shared resources. The method includes receiving requests for accessing the shared resources from one or more requestors, wherein a plurality of requests may be received from each requestor; arbitrating between the plurality of requests in such a way so that the plurality of requests from each requestor may be re-ordered in non-FIFO order; and selecting a next request to access the shared resources based on the re-ordering of requests. In accordance with another embodiment, a system re-orders requests for shared resources. The system includes one or more requestors for sending requests for accessing the shared resources, wherein a plurality of requests may be received from each requestor; and an arbiter for arbitrating between the plurality of requests in such a way so that the plurality of requests from each requestor may be re-ordered in non-FIFO order.

Abstract: Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.

Abstract: A program executing apparatus such as a programmable controller has a re-structureable address conversion section restructuring an address to generate a new address for specifying bit data that corresponds to each bit position in a physical memory or an I/O memory. Further, a program development supporting apparatus, such as a control program development supporting apparatus, has a conversion tool that generates configuration data describing a detailed restructure indication to enable the program executing apparatus to restructure the address, and a program making access to the restructured address.

Abstract: A content addressable memory having a function for extending a data width to a plurality of words includes an entry configuration set unit which sets the number of words to form one entry, and a logical-segment-to-physical-segment converting circuit for converting the logical segments in one entry to the physical segments according to the setting of the entry configuration. The content addressable memory further includes a word circuit chain having the maximum number of one-word circuits belonging to each physical block which are combined to form one entry. The one-word circuits have CAM words associated therewith, and are connected in series over the physical block. A group of the words at the same number in entries where one entry is composed of a plurality of words forms a logical segment.

Abstract: Virtual storage systems and virtual storage system operational methods are described. According to one aspect, a virtual storage system includes a virtual storage space including a plurality of virtual storage locations, a physical storage space including a plurality of physical storage locations configured to store data, a memory configured to store a plurality of activated pointers which associate a plurality of virtual storage locations with a plurality of the physical storage locations, and a controller configured to deactivate at least some of the activated pointers including extracting the deactivated pointers from the memory, to access a request pertaining to selected data associated with at least one of the deactivated pointers, to activate the deactivated pointers including providing the deactivated pointers in the memory providing reactivated pointers, and to modify at least one of the reactivated pointers responsive to the request.

Abstract: A computer system with mechanisms for exclusive caching that avoids the accumulation of duplicate copies of information in host and storage system caches. A computer system according to these exclusive caching techniques includes a host system having a host cache and a storage system having a storage system cache and functionality for performing demote operations to coordinate the placement of information in the host cache to the storage system caches.

Abstract: A method, system and computer program product for sharing an Integrated Device Electronics (IDE) drive among server blades in a dense server environment. By logically partitioning the IDE drive, where each logical partition is associated with a particular server blade, the IDE disk may be shared among multiple server blades in the dense server environment.

Abstract: A memory card having a one-time programmable memory which stores a plurality of storage allocation tables and which is compatible with a host device.