Abstract: A symmetric multiprocessor data processing system having an apparatus for imprecisely tracking cache line inclusivity of a higher level cache is disclosed. The symmetric multiprocessor data processing system includes multiple processing units. Each of the processing units is associated with a level one cache memory. All the level one cache memories are associated with an imprecisely inclusive level two cache memory. The imprecisely inclusive level two cache memory includes a tracking means for imprecisely tracking cache line inclusivity of the level one cache memories. The tracking means includes a last_processor_to_store field and a more_than_two_loads field per cache line. When the more_than_two_loads field is asserted, except for a specific cache line in the level one cache memory associated with the processor indicated in the last_processor_to_store field, all cache lines within the level one cache memories that shared identical information with that specific cache line are invalidated.

Abstract: A symmetric multiprocessor data processing system having a highly scalable shared cache memory hierarchy is disclosed. The symmetric multiprocessor data processing system includes multiple processing units. Each of the processing units includes a level one cache memory. All the level one cache memories are associated with a level two cache memory. The level two cache memory is non-inclusive of all the level one cache memories. An invalidation bus is connected to all of the level one cache memories. In response to a write access to a specific cache line within one of the level one cache memories, the invalidation bus invalidates other cache lines that shared identical information with the specific cache line within the rest of the level one cache memories.

Abstract: A memory management unit (MMU) is disclosed for managing a memory storing data arranged within a plurality of memory pages. The MMU includes a security check unit (SCU) receiving a physical address generated during execution of a current instruction. The physical address resides within a selected memory page. The SCU uses the physical address to access one or more security attribute data structures located in the memory to obtain a security attribute of the selected memory page, compares a numerical value conveyed by a security attribute of the current instruction to a numerical value conveyed by the security attribute of the selected memory page, and produces an output signal dependent upon a result of the comparison. The MMU accesses the selected memory page dependent upon the output signal. The security attribute of the selected memory page may include a security context identification (SCID) value indicating a security context level of the selected memory page.

Abstract: A method, system and apparatus for cascading backup mirrors are provided. A mirroring map is created. The mirroring map includes at least three mirrors. A first mirror of the three mirrors is set to synchronize to a second mirror and a third mirror is set to synchronize to the first mirror. The first and the third mirror are backup mirrors and the second mirror is a working mirror. One of the backup mirrors is located remotely and the other locally.

Abstract: A set of local invalidation buses for a highly scalable shared cache memory hierarchy is disclosed. A symmetric multiprocessor data processing system includes multiple processing units. Each of the processing units is associated with a level one cache memory. All the level one cache memories are associated with an imprecisely inclusive level two cache memory. In addition, a group of local invalidation buses is connected between all the level one cache memories and the level two cache memory. The imprecisely inclusive level two cache memory includes a tracking means for imprecisely tracking cache line inclusivity of the level one cache memories. Thus, the level two cache memory does not have dedicated inclusivity bits for tracking the cache line inclusivity of each of the associated level one cache memories. The tracking means includes a last_processor_to_store field and a more_than_two_loads field per cache line.

Abstract: A cache memory is provided which is capable of reducing areas occupied by data memory macro units and preventing delays in data transmission caused by wirings, thus improving performance of the cache memory. The cache memory is provided with four data memory macro units the number of which is equal to that of ways. Each of the data memory macro units can be accessed simultaneously. A different way number is made associated, for every word address having the same index address, with a data storing position in each of the data memory macro units and data having the same index address and same word address in each of the ways is stored for every data memory.

Abstract: Method and apparatus are disclosed for identifying logical volumes stored among a plurality of storage elements in a computer storage system. A unique logical volume identifier may be assigned to the logical volumes and used to access identifying information about the logical volumes.

Abstract: An apparatus for and a method of converting an address in a semiconductor memory device sequentially performing a data write operation on addresses from an upper address, by performing a write or read operation after converting inputted logical addresses into physical addresses in a memory device by using an address converting table. As a result, an operation speed of the system is improved and power consumption is reduced.

Abstract: A system and method for facilitating unmanaged code participation in a memory management system employing a garbage collection system or service is provided. The invention provides for an unmanaged component to invoke a machine state capturing component that captures machine state (e.g., machine registers and stack pointer) into a machine state data structure and publishes the fact that the unmanaged component desires to participate in garbage collection pointer enumeration. The invention further provides for an unwind component to be invoked during garbage collection that determines register value(s) to facilitate participation in garbage collection pointer enumeration by the unmanaged component. As part of its participation in garbage collection, the unwind component can alter contents of the machine state data structure stored by the machine state capturing component. The invention further provides for an unmanaged component to invoke a machine state restoring component that restores the machine state (e.

Abstract: A memory access control circuit including a memory and a slot for receiving therein a memory card having a controller. Address, CS (chip select) and We (output enable) signals different in active period from one another are supplied to the controller. Due to this, ID data signals are read from the memory. The CPU determines for properness on the read-out ID data signals. Specifically, when the common data contained in the ID data signal exhibits a predetermined value, the ID data signal is determined proper. However, when the common data does not exhibit the predetermined value, the ID data signal is determined to be improper. The CPU determines as an optimal active period a shortest active period among the active periods that proper ID data signals have been read out.

Abstract: A method for rebuilding meta-data stored in a data storage system (104) having storage devices (106) in which segments of data are located; for example, a storage system in the form of a log structured array. Data is written in segments to the storage devices (106) from a plurality of flows (122) of data and each segment of data contains meta-data relating to that segment. The meta-data stored in the storage system (104) can be rebuilt in the event of a failure by scanning the meta-data in each segment. A first scan of the meta-data in each segment in the storage devices (106) identifies the last segment written from each flow (122) and these segments are excluded from the rebuilding process as they may contain incomplete or inconsistent information. A second scan of the meta-data in each segment in the storage devices (106) identifies any segments which do not contain any live data tracks and these segments are also excluded from the, rebuilding process.

Abstract: A network storage controller for transferring data between a host computer and a storage device, such as a redundant array of inexpensive disks (RAID), is disclosed. The network storage controller includes at least one channel interface module which is adapted to be connected to the host computer and storage device. The channel interface module is connected to a passive backplane, and selectively transfers data between the host computer and storage device and the passive backplane. The network storage controller also includes at least one controller management module, attached to the passive backplane. The controller management module communicates with the channel interface module via the passive backplane, and processes and temporarily stores data received from the host computer or storage device. In applications where redundancy is required, at least two controller management modules and at least two channel interface modules may be used.

Abstract: A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may access address spaces in common. The mechanism further supports private TLB entries among logical processors, which may each access a different physical address through identical virtual addresses. The sharing mechanism provides for installation and updating of TLB entries as private entries or as shared entries transparently, without requiring special operating system support or modifications. Sharability of virtual address translations by logical processors may be determined by comparing page table physical base addresses of the logic processors. Using the disclosed sharing mechanism, fast and efficient virtual address translation is provided without requiring more expensive functional redundancy.

Abstract: An operation method of a storage wherein when a storage detects that a remaining amount of its own storage area has become less than a predetermined value, a remote storage area provided by a remote storage connecting with said storage via a predetermined communication means may be used as said storage area.

Abstract: A system and method for performing disk drive diagnostics and restoration using a host-inaccessible partition are disclosed. The system includes a disk drive including: a host-accessible user partition; a host-inaccessible hidden partition independent of the host-accessible user partition; and a disk controller. The user partition includes: a user partition address range; a host-selected operating system; and a host-selected master boot record.

Abstract: The present invention, in various embodiments, provides techniques for managing data in a queue. In one embodiment, two write pointers control writing into a memory queue and one read pointer control reading from the queue. Individual entries written into the queue may complete out-of-order and depend on various conditions such as whether the pointer associated with the entries is active or passive, whether the other pointer is tracking a transaction, whether the active pointer is lower, equal to, or higher than the inactive pointer, whether the data is the last piece of data in a transaction, etc. Data read from the queue is in the order of the transaction headers written into the queue. The data may bypass the queue, i.e., the data is not written into the queue, but is loaded directly to an output register.

Abstract: Methods and apparatus are disclosed for moving logical entities from one storage element to another storage element. Movement of the logical entity may be accomplished by using a logical volume identifier, which is unique to the logical volume with respect to other logical volumes stored on the storage elements. The movement may be accomplished by changing an entry for the physical storage location corresponding to the unique logical volume identifier.

Abstract: A technique for implementing a distributed lock for a shared resource accessible by a plurality of requesters in a processor-based device. The lock is implemented as an array of memory locations, in which the size of each memory location corresponds to a cache line size. Each requester attempting to acquire the lock is assigned a particular memory location at which to wait until lock ownership is available. Acquisition and release of the lock is facilitated by a token-passing scheme.

Abstract: A magnetic disc device includes a disc enclosure for enclosing a magnetic disc medium on which data has been recorded, and a circuit for processing a signal that has been read from the magnetic disc device, wherein a signal that is read from the magnetic disc is output from only an interface. The device may further include an authentication device which determines whether authentication codes match and/or a device that limits the number of times that a retry procedure may be performed when a data read error occurs.

Abstract: A RDRAM memory controller is provided to couple to a channel that is further coupled to a first RDRAM device and a second RDRAM device. The memory controller may include a command queue to store a plurality of commands and scheduling logic to schedule the plurality of commands to shift from the command queue based on a clock signal. Delaying logic may be provided to delay at least one command after the command shifts from the command queue. The delaying logic may include a plurality of multiplexors and a delay register coupled to outputs of the command queue.