Abstract: In a system for conducting virtual address translation in a virtual memory system and implementing a table such as a Translation Lookaside Buffer, a system and method enabling quicker access to tables entries in which the entries are addressed after adding a plurality of address parts wherein the plurality is two (2) or (3). Particularly, a smaller and/or faster adder is used having, for example, only n=2 ports in the time critical path. In order to make the exact address calculation, during array accesses, a multiplexor is implemented to decide, after the TLB arrays are accessed for preselection, which of a plurality of possible entries has to be taken.

Abstract: A way-determination scheme for an n-way associative cache is provided that is based on the entirety of the line address of a requested data item, thereby eliminating the possibility of a mis-identification of the way that contains the requested data item. A limited number of line addresses, and their assigned ways, are stored in a Way Determination Table. If a requested data address corresponds to one of these line addresses, the assigned way is provided; if not, a ‘null’ response is provided, indicating that the way is not known for this data address. If an assigned way is provided, the way corresponding to this assigned way is accessed, with the assurance that the accessed way contains the requested data item. If a ‘null’ response is provided, the n-ways are accessed to determine whether the requested data line is in the cache, as in a conventional n-way associative cache.

Abstract: A system and method store information to a sequential storage media such that storage space occupied-by data deemed obsolete may be reclaimed. Information may be written to the storage media as sequential data sets with each data set including a catalog describing the information in the data set. A reclamation catalog identifies the obsolete data stored on the media and is written to the media. A generation number on the storage media may indicate whether the storage media has been reclaimed. A reclamation process transfers data from the source media (e.g., the tape media that includes obsolete data) to a destination media (e.g., a blank tape) while excluding the obsolete data identified in the reclamation catalog. The reclamation process may read a catalog stored on the source media that describes the data stored on the source media. The reclamation process then modifies that catalog by the information stored in the reclamation catalog to create a unified catalog.

Abstract: A one-time programmable memory is described with a storage allocation table which is compatible with a host computer.

Abstract: A hash CAM is provided with a first and a second memory array, and comparison circuitry. The first memory array is used to store an m-bit input in a partitioned manner suitable for being subsequently output in a successive manner in portions of size m/p, where m and p are positive integers, with m being greater than or equal to p. The second memory array is used to store a plurality of threaded lists of entries, with each entry having a comparand also m-bit in size and stored in the same partitioned manner suitable for being selectively output in the same successive manner in portions of size m/p. The successive output is made responsive to an n-bit index generated in accordance with the m-bit input, with n being also a positive integer, but smaller than m.

Abstract: An address counter and address counting method is provided for enhancing an operational speed by forming a path for outputting a corresponding output address as soon as an external address or a previous internal address is inputted and further generating both a path for the case when a parity signal having a high state is inputted and a path for the case when a parity signal having a low state is inputted. While the paths are being produced, the parity signal is generated and the next internal address is immediately outputted in response to the generation of the parity signal. Moreover, an operation of latching the next address is terminated as soon as the parity signal is generated.

Abstract: A high-function address generating apparatus is realized which generates a memory address that can access a multidimensional area without running over a memory area specified by a user. Continuous addressing domain which is determined by a top address and a final address is set by an addressing domain setting means 101, an address is generated by a two-dimensional address generating means 106, the address in a two-dimensional area is compared with the final address and the top address by a first and a second comparing means 108 and 109, respectively, whether it runs over the addressing domain or not is judged by an address correction means 112, and an address running over is corrected so as to not run over.

Abstract: Architecture for a cache fabricated on a die with a processor including a plurality of cache banks, each containing a plurality of memory cell sub arrays. The sub arrays including a plurality of arrays of memory cells, the arrays including regular arrays and at least one redundant sub array. Logic circuitry is associated with each cache bank. A change in a single bit of the logic circuitry from a first to a second logic state causes one of the regular arrays to become disconnected from the global data bus, and the redundant array to become connected to the global data bus.

Abstract: A method of maintaining coherency in a cache hierarchy of a processing unit of a computer system, wherein the upper level (L1) cache includes a split instruction/data cache. In one implementation, the L1 data cache is store-through, and each processing unit has a lower level (L2) cache. When the lower level cache receives a cache operation requiring invalidation of a program instruction in the L1 instruction cache (i.e., a store operation or a snooped kill), the L2 cache sends an invalidation transaction (e.g., icbi) to the instruction cache. The L2 cache is fully inclusive of both instructions and data. In another implementation, the L1 data cache is write-back, and a store address queue in the processor core is used to continually propagate pipelined address sequences to the lower levels of the memory hierarchy, i.e., to an L2 cache or, if there is no L2 cache, then to the system bus. If there is no L2 cache, then the cache operations may be snooped directly against the L1 instruction cache.

Abstract: A disaster-tolerant data backup and remote copy system which is implemented as a controller-based replication of one or more LUNs (logical units) between two remotely separated pairs of array controllers connected by redundant links. The system provides a method for allowing a large number of commands to be ‘outstanding’ in transit between local and remote sites while ensuring the proper ordering of commands on remote media during asynchronous or synchronous data replication. In addition, the system provides a mechanism for automatic ‘tuning’ of links based on the distance between the array controllers.

Abstract: A reproduction apparatus is provided for use with a recording medium on which sub-data is recorded in association with main data. The apparatus includes a reading device for reading the sub-data from the recording medium, a memory for storing the sub-data, a data discriminator for determining whether a piece of sub-data read from the recording medium, which is at least one portion of the sub-data, is included in stored data already stored in the memory, and a controller. The controller stops the reading device from reading the sub-data when the data discriminator determines that the piece of sub-data is included in the stored data.

Abstract: In a computer, software may make an access to a controller in order to rewrite the contents of a nonvolatile storage device. If so, an interruption signal is automatically supplied to a CPU. In response to the interruption signal the CPU stops executing the software and starts performing an interruption process. During the interruption process it is determined whether the access made by the software is a right one. If the access is a wrong one, the rewriting of the contents of the nonvolatile storage device is prohibited at once.

Abstract: A cache memory organized into banks of subarrays includes repeaters for connecting to the data provided by the subarrays to a global data bus. The repeaters comprise a logic gate providing either a NAND or NOR function coupled in series with an inverter. The logic gate has a first input connected to receive a first logic value of a bus line, and a second input coupled to receive data output from a subarray. The inverter drives the first logic value onto the bus line when the cache bank subarray is inactive, and drives the data value from the subarray onto the bus line when the cache bank subarray is activate.

Abstract: Data integrity checking methods utilize a cumulative hash function. A sequence of data blocks and a corresponding sequence of hashes are stored on a medium. Each hash in the sequence of hashes corresponds to a data block in the sequence of data blocks. A particular hash corresponding to a particular data block is determined as a function of the particular data block and at least one previous hash corresponding to a previous data block in the sequence of data blocks.

Abstract: Providing data from a volume of a remote storage device coupled to a local storage device that is coupled to a host, includes providing a command to the remote storage device to request the data, if the data is stored in a cache portion of the remote storage device, the remote storage device providing the data, and if the data is not stored in the cache portion of the remote storage device, the remote storage device causing the data to be fetched from the volume and returning one of: a disconnect or an indicator that the data was not found. Causing the data to be fetched from the volume may include creating a separate wait task that waits for the data to be fetched from the volume. The separate wait task may be created only if there is not already another wait task waiting for the same data. The wait task may post an error if the data is not fetched after a predetermined amount of time, such as four seconds.

Abstract: A method and apparatus for storing an associative key data set of associative elements representing a range, and an associated data set of associated elements, such that an associative element is extracted from memory in response to an input key, the range being represented by a lower boundary value and/or an upper boundary value, the method including: a) providing first and second storage areas for storing the respective data sets; b) ordering the associative elements according to priority precedence; c) storage a boundary value of each associative element in the first storage area in a location corresponding to this order, and d) storing each associated data set value in the second storage area in a location corresponding to the location of the associative element associated thereto.

Abstract: Architecture for a cache fabricated on a die with a processor including a plurality of cache banks, each containing a plurality of storage cell subarrays, the cache banks being arranged in physical relationship to a central location on the die that provides a point for information transfer between the processor and the cache. A data path provides synchronous transmission of data to/from the cache banks such that data requested by the processor in a given clock cycle is received at the central location a predetermined number of clock cycles later regardless of which cache bank in the cache the data is stored.

Abstract: A network processor application-specific integrated circuit (ASIC) includes a plurality of processor devices each adapted to generate a semaphore operation request. A request arbiter, having connections to the plurality of processor devices, is provided to determine the semaphore operation request from one of the plurality of processor devices to be forwarded. A content addressable memory (CAM) is provided to store a data set. A CAM control state machine interconnects the request arbiter and the CAM, and implements a semaphore operation requested by one of the plurality of processor devices to the content addressable memory to access the data set.

Abstract: Speculative memory commands are prepared for reduced latency. A system memory read request is sent for preparing a main memory read command and for performing a cache lookup. The main memory read command is prepared independent from the performance of the cache lookup.

Abstract: A method of handling a write operation in a multiprocessor computer system wherein each processing unit has a respective cache, by determining that a new value for a store instruction is the same as a current value already contained in the memory hierarchy, and discarding the store instruction without issuing any associated cache operation in response to this determination. When a store hit occurs, the current value is retrieved from the local cache. When a store miss occurs, the current value is retrieved from a remote cache by issuing a read request. The comparison may be performed using a portion of the cache line which is less than a granule size of the cache line. A store gathering queue can be use to collect pending store instructions that are directed to different portions of the same cache line.