Abstract: Technology is disclosed herein for a storage system and method for reducing current levels while maintaining performance during a sensing operation. While initially ramping up and subsequently discharging the bias level on a selected word line, a selected bit line is set to float to thereby reduce current levels. The word line is then biased at a read voltage for a data state and, after being allowed to settle, the selected memory cell is sensed by determining the current though the selected memory cell. To improve performance, when the word line is biased at the read voltage, a voltage spike or kick is applied to selected bit line, after which it is biased at bit line sensing voltage while the selected word line settles and sensing occurs.

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract: An electronic device comprises a host processor comprising a memory controller connected to a memory device comprising a near memory processing unit. The host processor is configured to detect a system memory shortage for an operation of an operating system (OS), configure a memory region of the memory device for use in a memory pool of the OS in response to the system memory shortage, identify a request to execute an acceleration logic, and configure the memory region of the memory device for direct access by the near memory processing unit in response to the request to execute the acceleration logic.

Abstract: A method and system for dynamic storage scaling based on automatically parallelizing access of names and data across multiple nodes or micro object stores (MOSs) is provided. A dynamic storage scaling device cluster is provisioned for a particular level of parallelism (e.g., N MOSs) when the cluster is created. The N MOSs may initially reside in a few physical servers (e.g., one server). When the data distribution causes peak resource usage of the physical servers, new server(s) can be added. Some micro object stores (MOSs) are moved to the new physical server(s) through a meiosis process. The storage devices associated with the moved MOSs are unmounted from the original servers and mounted to the new server(s). The meiosis continues until the cluster grows to full capacity. The scaling is dynamic and efficient since no data copy is involved in the meiosis and the initial resource cost is optimized.

Abstract: Techniques are described for identifying deleted keys during snapshot comparisons managed by a data platform. A computing system that implements the data platform comprising a memory and processing circuitry may be configured to perform the techniques. The memory may store metadata identifying, at least in part, one or more deleted keys representative of deleted data that has been deleted from a storage system. The processing circuitry may identify a first tree data structure corresponding to a first snapshot of the storage system at a first time, and identify a second tree data structure corresponding to a second snapshot of the storage system at a second later time. The processing circuitry may traverse the first tree data structure and second tree data structures to identify the one or more deleted keys, and perform, based on the deleted keys, a data protection operation.

Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.

Abstract: An electronic device is provided. The electronic host includes: a host; a memory package including a plurality of memory devices and a first accelerator circuit configured to receive first data from the plurality of memory devices and perform a coarse acceleration operation based on the first data to obtain second data; and a memory controller including a second accelerator circuit configured to receive the second data from the first accelerator circuit and perform a fine acceleration operation based on a neural network and the second data to obtain an inference result.

Abstract: The present disclosure discloses memory controllers, operation methods thereof, and memory systems. The memory controller comprises: a first buffer configured to buffer a valid data table and mapping information to be updated, wherein the valid data table is to record a plurality of valid transmission unit counts, the valid transmission unit count indicates the number of transmission units that store valid data in a corresponding block, the mapping information to be updated comprises at least one piece of mapping information from a logical address to a physical address, and each transmission unit corresponds to one physical address; a second buffer configured to buffer a mapping table, wherein the mapping table is to record a plurality of pieces of mapping information; and an acceleration processing circuit configured to: update the mapping table based on the mapping information; and update the valid data table based on the mapping information to be updated.

Abstract: Data storage devices and controllers are disclosed. In an embodiment of the disclosed technology, an occupied logical memory address for loading an overlay code stored in a memory into a buffer memory is allocated and set in advance, and the loading of the overlay code is performed using the occupied logical memory address. Therefore, the overlay code can be loaded without allocating in advance a buffer area of the buffer memory, and thus the buffer memory may be efficiently used and the loading of the overlay code may be effectively performed.

Abstract: Data protection super-slices with super-parity p are created from sets of two RAID slices a, b of width W that each include slice parity a, b. The tracks of each super-slice are distributed across the disks of a disk cluster of width 2W+1, and the same number of indexed sequences. Each of the indexed sequences contains one super-slice with the slice tracks a, b distributed according to a fixed sequence in order from a start pointer to a stop pointer. The start pointer and the stop pointer are shifted one place for each successive indexed sequence. The fixed sequence may be characterized by slice track adjacency or be interleaved, e.g., (a b b a a a a a b b b b a b b b a a b a b b a a b a p) or (a a b a b b a b b b b a a a b a a a b a a a b b b b p).

Abstract: Provided are a method, system, and computer program product in which operations are performed to provide a plurality of configurations that indicate storage requirements of different storage tiers of a tiered storage system for a plurality of sites, wherein each of the plurality of configurations has an associated priority. Operations are performed to determine a configuration with a highest priority of the plurality of configurations, wherein storage tiers at each site of the plurality of sites are configurable in an identical manner in accordance with the determined configuration. The storage tiers of each site of the plurality of sites are configured in the identical manner in accordance with the determined configuration.

Abstract: A memory device includes a cell region, a buffer region, and a control circuit configured to: sequentially store read commands in a queue, and control the cell region and the buffer region to perform grouped read operations of outputting respective data blocks requested by the respective read commands.

Abstract: A computing system for performing runtime data handling optimization for generative models is provided. The computing system comprises at least one processor and memory comprising a first memory and a second memory, wherein the memory stores instructions that, when executed by the at least one processor, cause the at least one processor to execute a generative model. The computing system computes a first value matrix entry based upon the processing of an input to the generative model. The first value matrix entry is stored in a first memory wherein a first group of value matrix entries is identified. The computing system executes data quantization on the first group of value matrix entries which results in a first quantized value matrix. The first quantized value matrix is added to a second memory where it can be used during generation of the generative model.

Abstract: A storage system stores data on a persistent storage device and intent log on a high performance persistent storage device. The storage system receives requests to write data and in response, writes the data to the persistent storage device. The storage system receives a request to write data and a request to read data before the write request is processed. The storage system determines whether the data being read by the read request overlaps the data being written by the write request. If the data being read overlaps the data being written, the storage system writes the data being written in the intent log stored on the high performance persistent storage device. Subsequent to storing the data in the intent log on the high performance persistent storage device, the storage system sends the data being read to the client that sent the read request.

Abstract: A system stores and sequentially reconstruct a set of data. The system divides the set of data into the plurality of blocks and adds, for each block, a block pointer to a zone group index corresponding to a zone group of the block. In response to allocating a final block for a zone group, the system writes the zone group index in a same transaction group as the data in the respective zone group. The system stores a block pointer for the zone group index in a set of zone group metadata. The system sequentially reconstructs the set of data by loading the zone group metadata associated with one or more zone groups of the set of data and iterating, for each of the one or more zone groups, through a respective zone group index. The storage reconstructs each block referenced in a respective zone group index.

Abstract: A memory control system includes front-end circuitries, a traffic control circuitry, and back-end circuitries. Each of the front-end circuitries is configured to receive access requests from a corresponding device in devices, and sequentially output the access requests to be a corresponding one of first requests. The traffic control circuitry is configured to output the first requests to be second requests. The back-end circuitries are configured to adjust a task schedule of a memory according to the second requests, in which performances of the devices have different sensitivities to an access delay time of the memory.

Abstract: A processor comprising storage, execution circuitry and a handling unit configured to obtain task data that describes a task to be executed, comprising a plurality of operations representable as a directed graph of operations. The plurality of operations comprises: a set of production operations comprising generating a set of blocks comprising an intermediate block generated by a production operation in determining a final block; and a consumption operation. The handling unit generates a set of location data indicative of respective physical storage locations allocated to store respective blocks, traverses the set of location data to obtain location data indicative of a physical storage location for storing the intermediate block, and generates and sends execution instructions to instruct the execution circuitry to execute at least part of the consumption operation to read the intermediate block from the physical storage location, the execution instructions comprising the location data.

Abstract: A dynamic bifurcated bus width RAID storage system includes storage devices coupled to a root port on a processor via a switch that provides a respective bifurcated bus to transfer data between each storage device and the root port. A bifurcated bus width modification subsystem monitors the storage devices during their provisioning of a RAID storage system, determines that a RAID data movement operation is required, and retrieves a bifurcated bus width for each respective bifurcated bus provided by the switch to transfer data between each storage device and the root port. The bifurcated bus width modification subsystem then identifies a first storage device to which data will be written as part of the RAID data movement operation and, prior to its performance, increases a first bifurcated bus width for a first bifurcated bus provided by the switch to transfer data between the first storage device and the root port.

Abstract: An example methodology includes provisioning memory of a storage array with cache memory including a plurality of cache slots and reading data from the memory of the storage array into a first cache slot of the plurality of cache slots, wherein the data in the first cache slot is in a first data format, the first data format being the format of data in the memory of the storage array. The method also includes converting the data in the first cache to a second data format distinct from the first data format and placing the data in the second data format into a second cache slot of the plurality of cache slots.

Abstract: Provided are a storage device, an operation method of the storage device, and an electronic system including the storage device. The storage device includes a non-volatile memory device, and a storage controller configured to control the non-volatile memory device, execute a command from a host, select a location to which a completion entry for the command is to be written from among a memory and at least one cache of the host, and transmit, to the host, an interrupt including an interrupt vector number indicating the location to which the completion entry is to be written.