Abstract: A method for programming memory cells in a memory and the associated memory system. The method applies program pulses to the memory cells, applies a series of program-verify pulses to the memory cells to identify the memory cells having improper voltage thresholds short of the program-verify pulse levels, for the memory cells having the improper voltage thresholds, applies a non-zero bias to bit lines of the memory cells to program the memory cells, having the improper voltage thresholds, to proper voltage thresholds, and selectively determines which memory cells are first subject to both the program pulses and the program-verify pulses based on a programming speed of the memory cells.

Abstract: Methods, systems, and devices for a light hibernation mode for memory are described. A memory system may include volatile memory and non-volatile memory and may be configured to operate according to a first mode of operation (e.g., associated with relatively high power consumption), a light hibernation mode (e.g., a second mode associated with decreased power consumption in comparison to the first mode), and a full hibernation mode (e.g., a third mode of operation associated with decreased power consumption in comparison to the light hibernation mode). While operating according to the light hibernation mode, the memory system may maintain a greater quantity of data in the volatile memory relative to the full hibernation mode, which may avoid at least some power consumption related to data transfers between the volatile memory and non-volatile memory that may occur in connection with entering and exiting the full hibernation mode.

Abstract: According to an embodiment of the present invention, a device for artificial neural network (ANN) may comprise: memories for read/write (R/W) of data related to an ANN model; and at least one operation unit which performs, based on the data, operations for multiple layers included in the ANN model, wherein the memories include at least one memory-subsystem corresponding to a combination of different types of multiple memories, and each operation unit performs R/W of the data through a memory-subsystem associated with the each operation unit among the at least one memory-subsystem.

Abstract: Examples may include techniques to predict or determine time-to-ready (TTR) for a storage device. TTR may be predicted or determined based on operating information included in a snapshot associated with a first time interval during operation of the storage device. The TTR predicted or determined indicates an amount of time the storage device will be at an operational state following a power loss recover of the storage device.

Abstract: A system is provided that includes a compression engine, a metadata processor, and a memory having a burst length. The compression engine compresses source data according to a compression ratio to form compressed data. The metadata processor processes the compressed data to form metadata having a size that is smaller than the burst length. The metadata processor generates autofill data responsive to the compression ratio and concatenates the autofill data with the metadata to form a metadata burst having a same size as the burst length. A memory controller may then write the metadata burst to the memory without triggering a read-modify-write operation.

Abstract: A method for data writing in a distributed storage system, and electronic device are provided. In response to determining that any storage node receives, via a client component, a write request with a large volume of written data, the storage node sends, via the client component, request information related to the written data with a small data volume to a storage engine. The storage engine then divides the written data into multiple written data blocks and allocates a physical address in an Object-based Storage Device (OSD) corresponding to each written data block. This allows the OSD corresponding to each written data block, upon receiving the data block, to write the written data block to its allocated physical address in the OSD. Besides, the written data does not pass through the storage engine, reducing the data transmission volume during the writing process and minimizes the waste of bandwidth.

Abstract: A ferroelectric memory chiplet in a multi-dimensional packaging. The multi-dimensional packaging includes a first die comprising a switch and a first plurality of input-output transceivers. The multi-dimensional packaging includes a second die comprising a processor, wherein the second die includes a second plurality of input-output transceivers coupled to the first plurality of input-output transceivers. The multi-dimensional packaging includes a third die comprising a coherent cache or memory-side buffer, wherein the coherent cache or memory-side buffer comprises ferroelectric memory cells, wherein the coherent cache or memory-side buffer is coupled to the second die via I/Os. The dies are wafer-to-wafer bonded or coupled via micro-bumps, copper-to-copper hybrid bond, or wire bond, Flip-chip ball grid array routing, chip-on-wafer substrate, or embedded multi-die interconnect bridge.

Abstract: Techniques and mechanisms for selectively configuring an integrated circuit (IC) chip to provide tag array functionality and/or cache array functionality. In an embodiment, an IC chip comprises a first array of memory cells, a second array of memory cells, and a cache controller. Based on whether the IC chip is coupled to another IC chip, selector circuitry of the IC chip configures one of multiple possible modes of the cache controller. A first mode of the multiple modes is to provide tag array functionality with the first array, and cache array functionality with the second memory cell array. A second mode of the multiple modes is to provide tag array functionality with the second memory cell array, and cache array functionality with a remote array of memory cells. In another embodiment, the cache controller is reconfigured to another mode based on a change to a power consumption characteristic.

Abstract: A system is provided for an improved cached STE invalidation. To track which STEs are updated, a memory is provided with a bitmap. Software identifies which STE are updated through the bitmap. Due to the update of the stored STE(s), corresponding STEs in a cache are stale. The software invalidates only the corresponding cached STEs as identified through the bitmap as opposed to invalidating all the cached STEs.

Abstract: An example of an apparatus may include memory organized as at least one bank that includes two or more arrays, and circuitry communicatively coupled to the memory to select respective rows of the two or more arrays of a bank for a memory access operation based on an access orientation signal. Other examples are disclosed and claimed.

Abstract: An analog memory device includes a first node and a second node. The first node includes a first floating gate, a second floating gate, and a capacitor. The first node first floating gate is connected to the first node second floating gate via the capacitor. The second node includes a first floating gate, a second floating gate, and a capacitor. The second node first floating gate is connected to the second node second floating gate via the capacitor. The second node is connected to the first node, and an analog state of the first node and an analog state of the second node continuously and synchronously decay with respect to time.

Abstract: Technology is disclosed herein for a storage system and method for reducing current levels while maintaining performance during a sensing operation. While initially ramping up and subsequently discharging the bias level on a selected word line, a selected bit line is set to float to thereby reduce current levels. The word line is then biased at a read voltage for a data state and, after being allowed to settle, the selected memory cell is sensed by determining the current though the selected memory cell. To improve performance, when the word line is biased at the read voltage, a voltage spike or kick is applied to selected bit line, after which it is biased at bit line sensing voltage while the selected word line settles and sensing occurs.

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract: An electronic device comprises a host processor comprising a memory controller connected to a memory device comprising a near memory processing unit. The host processor is configured to detect a system memory shortage for an operation of an operating system (OS), configure a memory region of the memory device for use in a memory pool of the OS in response to the system memory shortage, identify a request to execute an acceleration logic, and configure the memory region of the memory device for direct access by the near memory processing unit in response to the request to execute the acceleration logic.

Abstract: A method and system for dynamic storage scaling based on automatically parallelizing access of names and data across multiple nodes or micro object stores (MOSs) is provided. A dynamic storage scaling device cluster is provisioned for a particular level of parallelism (e.g., N MOSs) when the cluster is created. The N MOSs may initially reside in a few physical servers (e.g., one server). When the data distribution causes peak resource usage of the physical servers, new server(s) can be added. Some micro object stores (MOSs) are moved to the new physical server(s) through a meiosis process. The storage devices associated with the moved MOSs are unmounted from the original servers and mounted to the new server(s). The meiosis continues until the cluster grows to full capacity. The scaling is dynamic and efficient since no data copy is involved in the meiosis and the initial resource cost is optimized.

Abstract: Techniques are described for identifying deleted keys during snapshot comparisons managed by a data platform. A computing system that implements the data platform comprising a memory and processing circuitry may be configured to perform the techniques. The memory may store metadata identifying, at least in part, one or more deleted keys representative of deleted data that has been deleted from a storage system. The processing circuitry may identify a first tree data structure corresponding to a first snapshot of the storage system at a first time, and identify a second tree data structure corresponding to a second snapshot of the storage system at a second later time. The processing circuitry may traverse the first tree data structure and second tree data structures to identify the one or more deleted keys, and perform, based on the deleted keys, a data protection operation.

Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.

Abstract: An electronic device is provided. The electronic host includes: a host; a memory package including a plurality of memory devices and a first accelerator circuit configured to receive first data from the plurality of memory devices and perform a coarse acceleration operation based on the first data to obtain second data; and a memory controller including a second accelerator circuit configured to receive the second data from the first accelerator circuit and perform a fine acceleration operation based on a neural network and the second data to obtain an inference result.

Abstract: The present disclosure discloses memory controllers, operation methods thereof, and memory systems. The memory controller comprises: a first buffer configured to buffer a valid data table and mapping information to be updated, wherein the valid data table is to record a plurality of valid transmission unit counts, the valid transmission unit count indicates the number of transmission units that store valid data in a corresponding block, the mapping information to be updated comprises at least one piece of mapping information from a logical address to a physical address, and each transmission unit corresponds to one physical address; a second buffer configured to buffer a mapping table, wherein the mapping table is to record a plurality of pieces of mapping information; and an acceleration processing circuit configured to: update the mapping table based on the mapping information; and update the valid data table based on the mapping information to be updated.

Abstract: Data storage devices and controllers are disclosed. In an embodiment of the disclosed technology, an occupied logical memory address for loading an overlay code stored in a memory into a buffer memory is allocated and set in advance, and the loading of the overlay code is performed using the occupied logical memory address. Therefore, the overlay code can be loaded without allocating in advance a buffer area of the buffer memory, and thus the buffer memory may be efficiently used and the loading of the overlay code may be effectively performed.