Abstract: A ferroelectric memory chiplet in a multi-dimensional packaging. The multi-dimensional packaging includes a first die comprising a switch and a first plurality of input-output transceivers. The multi-dimensional packaging includes a second die comprising a processor, wherein the second die includes a second plurality of input-output transceivers coupled to the first plurality of input-output transceivers. The multi-dimensional packaging includes a third die comprising a coherent cache or memory-side buffer, wherein the coherent cache or memory-side buffer comprises ferroelectric memory cells, wherein the coherent cache or memory-side buffer is coupled to the second die via I/Os. The dies are wafer-to-wafer bonded or coupled via micro-bumps, copper-to-copper hybrid bond, or wire bond, Flip-chip ball grid array routing, chip-on-wafer substrate, or embedded multi-die interconnect bridge.

Abstract: Deploying client-specific applications in a storage system utilizing redundant system resources, including: identifying a redundant controller in the storage system, wherein the storage system includes at least a first controller and the redundant controller; and executing one or more applications on the redundant controller, wherein the one or more applications are executed in a container.

Abstract: A node of a container system is made immutable to containers (e.g., to applications operating in the containers) running on the node. For example, the node may be made immutable by performing a method comprising: mounting, by a container runtime operating on a node within a container system, a volume comprising a container image, wherein the node comprises storage resources; creating, on the node and based on access to the volume, an instance of a container associated with the container image; and mapping, with respect to the container, accesses to the storage resources to one or more volumes stored remotely from the node, where the storage resources on the node are immutable to the container based on the mapping the accesses to the storage resources to the one or more volumes.

Abstract: A method and system for dynamic storage scaling based on automatically parallelizing access of names and data across multiple nodes or micro object stores (MOSs) is provided. A dynamic storage scaling device cluster is provisioned for a particular level of parallelism (e.g., N MOSs) when the cluster is created. The N MOSs may initially reside in a few physical servers (e.g., one server). When the data distribution causes peak resource usage of the physical servers, new server(s) can be added. Some micro object stores (MOSs) are moved to the new physical server(s) through a meiosis process. The storage devices associated with the moved MOSs are unmounted from the original servers and mounted to the new server(s). The meiosis continues until the cluster grows to full capacity. The scaling is dynamic and efficient since no data copy is involved in the meiosis and the initial resource cost is optimized.

Abstract: In a method for storing index metadata associated with stored data, a storage device provides a first metadata storage unit and a second metadata storage unit, wherein a size of the first metadata storage unit is greater than a size of the second metadata storage unit. When a size of target data reaches a specified threshold, the storage device stores index metadata of the target data based on the first metadata storage unit. When the size of the target data is less than the specified threshold, the storage device stores the index metadata of the target data based on the second metadata storage unit.

Abstract: A data storage device includes multiple storage modules. Each storage module includes a storage which having a memory device and a first memory controller and a second memory controller. The first memory controller is coupled to the memory device for accessing the memory device. The second memory controller is coupled to the storage for accessing the storage. The first memory controller includes a first transmission interface. The second memory controller includes a second transmission interface. The first memory controller and the second memory controller communicate with each other through the first transmission interface and the second transmission interface.

Abstract: The disclosed technologies provide functionality for collecting quality of service (“QoS”) statistics for in-use child physical functions of multiple physical function (“PF”) non-volatile memory devices (“MFNDs”). A host computing device creates a child PF on a MFND and configures the child PF on the MFND to provide a specified QoS level to an associated VM executing on the host computing device. The MFND then collects child PF QoS statistics for the child PF that describe the utilization of resources provided by child PF to an assigned VM. The MFND provides the child PF QoS statistics from the MFND to the host computing device. The collected child PF QoS statistics can be utilized to inform decisions regarding reallocation of MFND-provided resources, provisioning of new MFND-provided resources, and for other purposes.

Abstract: The present disclosure generally relates to an efficient manner of fetching data for write commands. The data can be fetched prior to classification, which is a fetch before mode. The data can alternatively be fetched after classification, which is a fetch after mode. When the data is fetched after classification, the write commands are aggregated until sufficient data associated with any command is split between memory devices. When in fetch before mode, the data should properly align such that data associated with any command is not split between memory devices. Efficiently toggling between the fetch before and fetch after modes will shape how writes are performed without impacting latency and bandwidth without significantly increasing write buffer memory size.

Abstract: A method for performing configuration management of a memory device in predetermined communications architecture with aid of electronic fuse (eFuse) data preparation, associated apparatus and computer-readable medium are provided. The method may include: utilizing a memory controller to receive a first command from a host device through a transmission interface circuit of the memory controller; utilizing the memory controller to execute at least one procedure regarding MP initialization of the memory device, for example, operations of a first procedure among the at least one procedure may include obtaining eFuse information from an eFuse circuit, preparing protected eFuse data according to the eFuse information, and storing the protected eFuse data into a non-volatile (NV) memory; and utilizing the memory controller to send a first response to the host device through the transmission interface circuit, wherein the first response is sent to the host device in response to the first command.

Abstract: An illustrative method of container recovery using layer prioritization includes identifying a set of immutable layers of container images included in a dataset used by a container system to run containerized applications on a first cluster; copying the set of immutable layers of container images to a second cluster in preparation for a recovery event; receiving, after the set of immutable layers of container images are copied to the second cluster, a recovery request to recover the containerized applications; and copying, in response to the recovery request, a set of mutable layers included in the dataset to the second cluster, the second cluster configured to use the copied set of immutable layers and the copied set of mutable layers to recover the containerized applications on the second cluster.

Abstract: One or both of read and write accesses to a fabric-attached memory module via a fabric interconnect are monitored. In one or more implementations, offloading of one or more tasks accessing the fabric-attached memory module to a processor of a routing system associated with the fabric-attached memory module is initiated based on the read and write accesses to the fabric-attached memory module. Additionally or alternatively, replicating memory of the fabric-attached memory module to a cache memory of a computing node in the disaggregated memory system executing one or more tasks of a host application is initiated based on the write accesses to the fabric-attached memory module.

Abstract: Techniques are disclosed relating to upgrade groups. A node of a computer system may access metadata assigned to the node during deployment of the node. The node may be one of a plurality of nodes associated with a service that is implemented by the computer system. The node may perform an operation on the metadata to derive a group identifier for the node and the group identifier may indicate the node's membership in one of a set of groups of nodes managed by the service. The node may then store the group identifier in a location accessible to the service.

Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.

Abstract: A data processing system includes a first server and a second server. The first server includes a first processor group, a first memory space and a first interface circuit. The second server includes a second processor group, a second memory space and a second interface circuit. The first memory space and the second memory space are allocated to the first processor group. The first processor group is configured to perform memory error detection to generate an error log corresponding to a memory error. When the memory error occurs in the second memory space, the first interface circuit is configured to send the error log to the second interface circuit, and the second processor group is configured to log the memory error according to the error log received by the second interface circuit. The data processing system is capable of realizing memory reliability architecture supporting operations across different servers.

Abstract: A method may include receiving, from a process, a memory allocation request for a memory system comprising a first channel having a first channel utilization and a second channel having a second channel utilization, selecting, based on the first channel utilization and the second channel utilization, the first channel, and allocating, to the process, a page of memory from the first channel. The selecting may include selecting the first channel based on a balanced random policy. The selecting may include generating a ticket based on a random number and a number of free pages, comparing the ticket to a number of free pages of the first channel, and selecting the first channel based on the comparing. The selecting may include selecting the first channel based on a least used channel policy.

Abstract: A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.

Abstract: A method comprising: receiving, at a management application, a first definition of a control window, the first definition specifying the control window in a local time of a time zone where the management application is being executed, wherein the first definition identifies: (i) a first start time for the control window, (ii) a first end time for the control window, and (iii) one or more days of the week when the control window should be enforced; detecting an applicable time in the time zone, the applicable time being one of standard time or daylight savings time; generating a second definition of the control window that corresponds to the applicable time, the second definition specifying the control window in a standardized time format, the second definition being generated based on the first definition; and causing the control window to be enforced in a storage array in accordance with the second definition.

Abstract: In some examples, a system causes execution, in each respective storage node of a cluster of storage nodes, of a respective frontend service that provides a frontend to a client over a network for access by the client of a storage volume accessible by the cluster of storage nodes. The system obtains node-specific configuration data portions from a configuration data repository, the node-specific configuration data portions being for respective storage nodes of the cluster of storage nodes, and sends the node-specific configuration data portions to the respective frontend services for configuring the frontend services.

Abstract: Methods, systems, and devices for on-die termination configuration for a memory device are described. In some examples, a memory device may determine a connection option from a set of connections options for which an ODT pin of the memory device is configured. Each connection option may correspond to a termination configuration for a different pin, such as a command and address (CA) pin, a clock (CK) pin, or a chip select (CS). Based on the determined connection option, the memory device may identify a respective termination option for each of the different pins, such as a first termination option for the CA pin, a second termination option for the CK pin, and a third termination option for the CS pin, and configure each of the different pins according to the respective termination option for that pin.

Abstract: The functions of a mainframe environment are expanded by leveraging the functions of an open environment.