Patents Examined by Midys Rojas
  • Patent number: 10474367
    Abstract: A storage array in one embodiment is configured to communicate over one or more networks with a plurality of host devices. The storage array is further configured to detect process tags assigned to respective input-output operations by a given one of the host devices, the process tags being of at least first and second distinct types so as to distinguish at least respective first and second distinct processes generating corresponding ones of the input-output operations on the given host device. Responsive to a particular one of the detected process tags being of the first type, the storage array provides a first level of priority for processing of the corresponding input-output operation, and responsive to a particular one of the detected process tags being of the second type, the storage array provides a second level of priority different than the first level of priority for processing of the corresponding input-output operation.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: November 12, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Sanjib Mallick, Krishna Deepak Nuthakki, Vinay Rao, Arieh Don, Maneesh Pusalkar
  • Patent number: 10474583
    Abstract: An information handling system may implement a method for controlling cache flush size by limiting the amount of modified cached data in a data cache at any given time. The method may include keeping a count of the number of modified cache lines (or modified cache lines targeted to persistent memory) in the cache, determining that a threshold value for modified cache lines is exceeded and, in response, flushing some or all modified cache lines to persistent memory. The threshold value may represent a maximum number or percentage of modified cache lines. The cache controller may include a field for each cache line indicating whether it targets persistent memory. Limiting the amount of modified cached data at any given time may reduce the number of cache lines to be flushed in response to a power loss event to a number that can be flushed using the available hold-up energy.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: November 12, 2019
    Assignee: Dell Products L.P.
    Inventors: John E. Jenne, Stuart Allen Berke, Vadhiraj Sankaranarayanan
  • Patent number: 10459650
    Abstract: A data operation method and an electronic device are provided. The method includes assigning a reserved area of a memory of an electronic device, which receives power associated with maintaining a data write state when the supply of a main power is blocked to a file system of a RAMDisk associated with processing a data input/output (I/O) and controlling file processing of the file system of the RAMDisk.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: October 29, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woo Joong Lee, Dae Ho Jeong
  • Patent number: 10452298
    Abstract: Reading and copying data as file data in a persistent memory storage device. A method may be practiced in a virtual machine environment. The virtual machine environment includes a persistent memory storage device. The persistent memory storage device has the ability to appear as a memory device having available memory to a virtual machine on a host and as a file to the host. The method includes acts for copying data stored in the persistent memory storage device for a first virtual machine. The method includes the host reading data from the persistent memory storage device as file data. The method further includes the host writing the data from the persistent memory storage device as file data.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 22, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Matthew David Kurjanowicz, Attilio Mainetti, Scott Chao-Chueh Lee
  • Patent number: 10445236
    Abstract: A thread on a processor core executes one or more instructions to write file data for a file into a persistent memory save area. The instructions to write the file data have the effect of storing the file data for the file in the cache associated with the processor core. The thread running on the processor core flushes the file data from the cache to the persistent memory save area while retaining the file data in the cache. The thread running on the processor core copies the file data from the cache for the processor core into a persistent copy of the file that is stored in persistent memory.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: October 15, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventor: Thomas Boyle
  • Patent number: 10417098
    Abstract: For accessing files from block-level backups of a virtual disk, an apparatus is disclosed. The apparatus includes a changed block module that obtains a list of changed blocks between a previous and a current backup of a virtual disk. The apparatus includes a mapping module that maps logical clusters of the virtual disk to the changed blocks and identifies files corresponding to the logical clusters. The apparatus further includes a changed file module that designates the files corresponding to the logical clusters as changed files, unless current attributes of the files for the current backup match attributes of the files in a backup file index corresponding to the previous backup of the virtual disk. The changed file module further stores the current attributes and extents for the changed files within blocks of a backup storage device for updating in the backup file index.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: September 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Fruchtman, Avishai H. Hochberg, Vadzim I. Piletski, James P. Smith
  • Patent number: 10417132
    Abstract: In general, embodiments of the technology relate to method for resolving a library path in a distributed system. The method includes receiving a path resolution request, issuing a first request to a first node server to obtain a first library name index (LNI) associated with a first portion of the library path, obtaining the first LNI, and generating, based on the first LNI, a second request to a second node server of the plurality of node servers, where the second request is associated with a second portion of the library path. The method further includes after not receiving a second response to the second request: issuing a request message to a set of node servers, receiving, from one of the node servers, a third response to the request message, and resolving the entire library path using, at least in part, the third response.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 17, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Petr Olegovich Pleshachkov, Valery Maltsev, Ewout Graswinckel
  • Patent number: 10417067
    Abstract: A forwarding pipeline of a forwarding engine includes a mirror bit mask vector with one bit per supported independent mirror session. Each bit in the mirror bit mask vector can be set at any point in the forwarding pipeline when the forwarding engine determines that conditions for a corresponding mirror session are met. At the end of the forwarding pipeline, if any of the bits in the mirror bit mask vector is set, then a packet, the mirror bit mask vector and a pointer to the start of a mirror destination linked list are forwarded to the multicast replication engine. The mirror destination linked list typically defines a rule for mirroring. The multicast replication engine mirrors the packet according to the mirror destination linked list and the mirror bit mask vector.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: September 17, 2019
    Assignee: Cavium, LLC
    Inventors: Gerald Schmidt, Harish Krishnamoorthy, Tsahi Daniel
  • Patent number: 10402334
    Abstract: In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetch circuit with features designed to improve prefetching accuracy and/or reduce power consumption. In an embodiment, the prefetch circuit may be configured to detect that pointer reads are occurring (e.g. “pointer chasing.”) The prefetch circuit may be configured to increase the frequency at which prefetch requests are generated for an access map in which pointer read activity is detected, compared to the frequency at which the prefetch requests would be generated in the pointer read activity is not generated. In an embodiment, the prefetch circuit may also detect access maps that are store-only, and may reduce the frequency of prefetches for store only access maps as compared to the frequency of load-only or load/store maps.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: September 3, 2019
    Assignee: Apple Inc.
    Inventors: Stephan G. Meier, Mridul Agarwal
  • Patent number: 10394596
    Abstract: An identification of one or more memory pages that are associated with the guest operating system may be received by a hypervisor and from a guest operating system. The hypervisor may receive a request from the guest operating system to initiate a tracking operation for the one or more memory pages. The tracking operation may be initiated for the one or more memory pages in response to receiving the request from the guest operating system. Furthermore, the one or more memory pages may be freed in view of the tracking operation that has been initiated by the hypervisor.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: August 27, 2019
    Assignee: Red Hat, Inc.
    Inventors: Michael Tsirkin, Henri Han van Riel
  • Patent number: 10394461
    Abstract: Systems and methods for optimizing storage system performance are disclosed. A method includes: determining an expected lifetime of each of at least one computing instance; determining a disk data extent evaluation period for each of the at least one computing instance based on the determined expected lifetime; determining an input/output (I/O) wait time threshold for each of the at least one computing instance; determining an I/O wait time of each of the at least one computing instance using the determined disk data extent evaluation period; and in response to the determined I/O wait time of one or more of the at least one computing instance exceeding the determined I/O wait time threshold of the computing instance, moving at least one data extent associated with the one or more computing instance exceeding the determined I/O wait time threshold from hard disk drive storage to solid state drive storage.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edward R. Bernal, Ivan M. Heninger
  • Patent number: 10395044
    Abstract: In general, embodiments of the invention include methods and apparatuses for securely storing computer system data. Embodiments of the invention encrypt and decrypt SATA data transparently to software layers. That makes it unnecessary to make any software modifications to the file system, device drivers, operating system, or application. Encryption key management is performed either remotely on a centralized Remote Management System or locally. Embodiments of the invention implement background disk backups using snapshots. Additional security features that are included in embodiments of the invention include virus scanning, a virtual/network drive, a RAM drive and a port selector that provides prioritized and/or background access to SATA mass storage to a secure subsystem.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: August 27, 2019
    Assignee: Janus Technologies, Inc.
    Inventors: Michael Wang, Joshua Porten, Sofin Raskin, Mikhail Borisov
  • Patent number: 10387305
    Abstract: Techniques and computing devices for compression memory coloring are described. In one embodiment, for example, an apparatus may include at least one memory, at least on processor, and logic for compression memory coloring, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to determine whether data to be written to memory is compressible, generate a compressed data element responsive to determining data is compressible, the data element comprising a compression indicator, a color, and compressed data, and write the compressed data element to memory. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: August 20, 2019
    Assignee: INTEL CORPORATION
    Inventors: David M. Durham, Sergej Deutsch, Saeedeh Komijani, Alpa T. Narendra Trivedi, Siddhartha Chhabra
  • Patent number: 10387068
    Abstract: Implementations of the disclosure provide for size adjustable volumes for containers. A method of the disclosure includes determining, by a processing device of the PaaS system, a size used space in a storage volume with respect to a container associated with an execution of an application. The size is a summation of current usage of disk space for the storage volume by the application. This size of the used space is compared to a threshold size. The threshold size indicates a determined amount of the storage volume allocated to the container. Responsive to the size meeting the threshold size, an increase in the allocated amount of the storage volume associated with the container is regulated by the processing device.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: August 20, 2019
    Assignee: Red Hat, Inc.
    Inventors: Daniel J. Walsh, Vivek Goyal, Shishir Mahajan
  • Patent number: 10379768
    Abstract: In one embodiment, a memory interface employs selective memory mode authorization enforcement in accordance with the present description to ensure that memory modes of operation which have not been authorized, are not permitted to proceed. In one embodiment, mode control logic receives from memory control logic of the memory interface, memory mode selection data which is compared to a mode authorization classification structure to determine if the memory mode being selected in association with a memory transaction request is authorized or otherwise permitted. Memory mode enablement logic of the mode control logic enables the requested memory mode associated with a memory transaction request if it is determined that the selected memory mode associated with the memory transaction request is authorized. Other aspects are described herein.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 13, 2019
    Assignee: INTEL CORPORATION
    Inventors: Mahesh S. Natu, Vedaraman Geetha
  • Patent number: 10380035
    Abstract: Provided are a computer program product, system, and method for using an access increment number to control a duration during which tracks remain in cache. Tracks in a storage in the cache are indicated in a cache list. For each of the tracks indicated in the cache list, an access value is updated when one of the tracks is accessed in the cache. An access to a track in the cache indicated in the cache list is received. A determination is made as to whether an access increment number for the accessed track, wherein the access increment number is greater than one. The access value for the accessed track is incremented by the determined access increment number in response to the track being accessed in the cache. The access value for one of the tracks is used to determine whether to initiate to demote the track from the cache.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Matthew J. Kalos
  • Patent number: 10372377
    Abstract: A memory controller includes a memory interface that is connected to a non-volatile memory that includes a plurality of memory cells, and a control unit. The control unit controls the memory interface to perform writing of data that has a first number of bits to a first memory cell in an n-bit write mode (where n is 2 or more), and when performing reading of the data written into the first memory cell, to control the memory interface to perform reading of data in an m-bit read mode (where m is less than n), as a result of which data that has a second number of bits which is smaller than the first number of bits, is returned from the first memory cell.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: August 6, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Katsuhiko Iwai
  • Patent number: 10372378
    Abstract: Technology is described herein for operating non-volatile storage. In one aspect, a memory controller replaces an original data buffer pointer(s) to a host memory data buffer(s) with a replacement data buffer pointer(s) to a different data buffer(s) in the host memory. The original data buffer pointer(s) may be associated with a specific read command. For example, the original data buffer pointer(s) may point to data buffer(s) to which data for some range of logical addresses (which may be read from the non-volatile storage) is to be transferred by a memory controller of the non-volatile storage. The replacement data buffer pointer(s) could be associated with a different read command. However, it is not required for the replacement data buffer pointer(s) to be associated with a read command. The replacement data buffer pointer(s) may point to a region of memory that is allocated for exclusive use of the memory controller.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: August 6, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Judah Gamliel Hahn, Alon Marcu, Ariel Navon, Alexander Bazarsky
  • Patent number: 10373667
    Abstract: A technique includes determining that a row of memory has been activated at a threshold rate. Upon reaching the threshold rate, a refresh rate for the row of memory and an adjacent row of memory may be increased. Subsequent to the increase, the refresh rate may be returned to a default rate.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: August 6, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Melvin K. Benedict, Eric L. Pope
  • Patent number: 10372364
    Abstract: A storage enclosure includes a plurality of hard drive sub-boards, each configured to include a plurality of hard drives. A local logic device manages each hard drive sub-board. A master logic device manages the local logic devices. The master logic device receives management commands from a host computer system coupled to the storage enclosure, and routes those commands to specific local logic devices. The local logic devices then relay the commands to specifically targeted hard drives. Thus, each hard drive within the storage enclosure can be independently controlled, allowing a single hard drive to be powered down without powering down other hard drives in the enclosure.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: August 6, 2019
    Assignee: SUPER MICRO COMPUTER, INC.
    Inventors: RS Hsiao, Kelvin Tseng, Lawrence H. Liang, Richard Chen