Abstract: A memory controller is for controlling operations of a nonvolatile memory including a first memory block group for storing a first type of data and a second memory block group for storing a second type of data. The memory controller includes a garbage collection management unit configured to execute a garbage collection policy in which a first garbage collection criteria is applied to the first memory block group, and a second garbage collection criteria is applied to the second memory block group, where first garbage collection criteria is different than the second garbage collection criteria.

Abstract: In certain embodiments, a computer system can create first and second pluralities of disk groups in a hyperconverged infrastructure (HCI) cluster, where each disk group in the first plurality has capacity storage devices of a first type and each disk group in the second plurality has capacity storage devices of a second type. The computer system can further tag each disk group in the first plurality with a first disk group tag, tag each disk group in the second plurality with a second disk group tag, and create a storage policy that includes a placement rule identifying the first disk group tag. Then, at a time of provisioning a virtual machine (VM) in the HCI cluster that is associated with the storage policy, the computer system can place the VM on one or more of the first plurality of disk groups in accordance with the placement rule identifying the first disk group tag.

Abstract: Disclosed is a register data checking device including: an original parity-bit generator generating an original parity bit according to register data to be inputted into a register, and then writing the original parity bit to the register; and a detecting circuit. The detecting circuit includes: a scanning circuit reading the register data and the original parity-bit from the register; an arbitrator enabling the scanning circuit when an access status of the register is free, and thereby forwarding the register data and the original parity bit from the scanning circuit; at least one controlled parity-bit generator generating a controlled parity bit according to the register data from the arbitrator when the access status of the register is free; and at least one parity-bit checking circuit comparing the original parity bit from the arbitrator with the controlled parity bit when the access status is free, and thereby outputting a check result.

Abstract: Techniques are provided for asynchronous semi-inline deduplication. A multi-tiered storage arrangement comprises a first storage tier, a second storage tier, etc. An in-memory change log of data recently written to the first storage tier is evaluate to identify a fingerprint of a data block recently written to the first storage tier. A donor data store, comprising fingerprints of data blocks already stored within the first storage tier, is queried using the fingerprint. If the fingerprint is found, then deduplication is performed for the data block to create deduplicated data based upon a potential donor data block within the first storage tier. The deduplicated data is moved from the first storage tier to the second storage tier, such as in response to a determination that the deduplicated data has not been recently accessed. The deduplication is performed before cold data is moved from first storage tier to second storage tier.

Abstract: A current memory access voltage distribution is measured for a memory page of a block family associated with a first voltage bin of a plurality of voltage bins at a memory device. The first voltage bin is associated with a first voltage offset. A current value for a reference voltage is determined based on the current memory access voltage distribution measured for the memory page. An amount of voltage shift for the memory page is determined based on the current value for the reference voltage a prior value for the reference voltage. The prior value for the reference voltage is associated with a prior memory access voltage distribution for the memory page. In response to a determination that the amount of voltage shift satisfies a voltage shift criterion, the block family is associated with a second voltage bin of the plurality of voltage bins. The second voltage bin is associated with a second voltage offset.

Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.

Abstract: The present disclosure generally relates to efficient data transfer management of zone-append commands for a zoned namespace (ZNS). The ZNS storage device comprises a memory device having a plurality of memory dies, and a controller coupled to the memory device The controller receives a plurality of zone append commands, each zone append command being associated with a zone identification identifying a zone of a plurality of zones, and fetches and aggregates data associated with each zone append command by the zone identification in an append write buffer. The aggregated data is written to the memory device upon the aggregated data for each zone reaching a predetermined programming chunk size, or to a temporary buffer if the predetermined write size is not met. Each zone uses a separate channel when sending the aggregated data for programming to the memory device, allowing multiple channels to be utilized in parallel.

Abstract: Disclosed in some examples are improved storage, replication, and distribution of data related to network-based meetings (e.g., media) in hierarchical records. Data for one or more components of the meeting (e.g., media) may be stored in a child record (called a component record). The network-based meeting may be described by a parent record with links to, and in some examples descriptions of, the meeting component records (the child records). The meeting object may point to local, and/or replicated copies of the child records. As noted, the child records may be or include media objects and, in some examples, the child records may be replicated to one or more locations based upon a demand for the media object. By replicating the media to a location that is close to demand for the media, this provides for more efficient delivery of media of the meeting.

Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

Abstract: A memory system has a memory, a first substrate on which the memory is mounted and which is set to a temperature of ?40[° C.] or lower, a controller configured to control the memory; and a second substrate on which the controller is mounted, which is set to a temperature of ?40[° C.] or higher, and which transmits and receives a signal to and from the first substrate via a signal transmission cable.

Abstract: The functions of a mainframe environment are expanded by leveraging the functions of an open environment.

Abstract: A virtual memory management method applied to an intelligent processor including an operation accelerator includes: determining m storage units from a physical memory, the m storage units forming a virtual memory; dividing the m storage units into n storage groups; determining an address mapping relationship for each storage group to obtain n address mapping relationships, the n address mapping relationship being correspondence of between n virtual addresses of the virtual memory and physical addresses of the m storage units, where m and n are dynamically updated according to requirements of the operation accelerator. In the method, the number of the storage units in each storage group can be configured according to requirements of the operation accelerator, and a data storage bit width and a data storage depth of the virtual memory are dynamically updated to thereby improve data access efficiency.

Abstract: A method and system for dynamic storage scaling based on automatically parallelizing access of names and data across multiple nodes or micro object stores (MOSs) is provided. A dynamic storage scaling device cluster is provisioned for a particular level of parallelism (e.g., N MOSs) when the cluster is created. The N MOSs may initially reside in a few physical servers (e.g., one server). When the data distribution causes peak resource usage of the physical servers, new server(s) can be added. Some micro object stores (MOSs) are moved to the new physical server(s) through a meiosis process. The storage devices associated with the moved MOSs are unmounted from the original servers and mounted to the new server(s). The meiosis continues until the cluster grows to full capacity. The scaling is dynamic and efficient since no data copy is involved in the meiosis and the initial resource cost is optimized.

Abstract: A data storage device includes a memory device having a plurality of endurance groups and a controller coupled to the memory device. The controller includes at least one decoder or at least one decoder group. The controller is configured to allocate a plurality of tokens to each endurance group of the plurality of endurance groups, receive a payment of tokens from an endurance group to access the at least one decoder or the at least one decoder group, and grant access to the at least one decoder or the at least one decoder group to the endurance group based on the payment of tokens. Each decoder or each decoder group is associated with the same or different payment of tokens and each endurance group has a maximum capacity of tokens.

Abstract: Methods, apparatus, and processor-readable storage media for unified host-based data migration are provided herein. An example computer-implemented method includes identifying a first storage array and a second storage array associated with a host device; determining a set of characteristics related to the host device for migrating data from the first storage array to the second storage array; and migrating the data based at least in part on the set of characteristics, wherein the migrating comprises: creating a set of target devices on the second storage array and provisioning the set of target devices to the host device; and moving the data from a set of source devices on the first storage array to the target devices on the second storage array.

Abstract: A data storage method and apparatus are provided. First information of to-be-stored data is first obtained. The first information includes at least one piece of information: a type of the to-be-stored data, a name of the to-be-stored data, and a user identifier corresponding to the to-be-stored data; An expected storage location of the to-be-stored data is determined based on whether the first information of the to-be-stored data meets a condition. At least one data packet in a plurality of data packets of the to-be-stored data is stored in the expected storage location.

Abstract: A novel and useful system and method of improved power performance and lowered memory requirements for an artificial neural network based on packing memory utilizing several structured sparsity mechanisms. The invention applies to neural network (NN) processing engines adapted to implement mechanisms to search for structured sparsity in weights and activations, resulting in a considerably reduced memory usage. The sparsity guided training mechanism synthesizes and generates structured sparsity weights. A compiler mechanism within a software development kit (SDK), manipulates structured weight domain sparsity to generate a sparse set of static weights for the NN. The structured sparsity static weights are loaded into the NN after compilation and utilized by both the structured weight domain sparsity mechanism and the structured activation domain sparsity mechanism.

Abstract: In a storage system including a plurality of nodes that provide a storage area and a drive that physically stores data, a parity group is configured with a plurality of data including user data stored in the storage area and redundant data for protecting the user data, a plurality of data in the parity group are stored in a storage area within one predetermined range across a plurality of nodes, and processing for dividing the predetermined range or processing for merging a plurality of predetermined ranges is performed based on a state of the predetermined range.

Abstract: A memory management method includes determining a memory page that needs to be swapped out of a memory, for each memory page that needs to be swapped out, generating, based on the memory page, a work task reclaiming the memory page, and allocating each work task to a dedicated worker thread for execution.

Abstract: A tape may be mounted into a tape drive. Mounting the tape into the tape drive may include loading the tape from a storage slot. The tape drive may request a first record of the tape from a tape storage subsystem. The tape drive may determine whether the first record of the tape exists in the tape storage subsystem. The tape drive may load the first record of the tape in random access memory (RAM) of the tape drive. The first record may include one or more data entries. The tape drive may append a new data entry to the first record. The first record may be transitioned to a second record upon being appended with the new data entry. The tape may be unmounted from the tape drive.