Abstract: An input data pre-alignment circuit includes a first amplifier, a second amplifier, a clock control unit, a feedback signal generator, and a signal alignment unit. The first amplifier includes a first input terminal for receiving a data signal, a second input terminal for receiving a reference signal, a first output terminal, and a second output terminal. The second amplifier is coupled to the first output terminal of the first amplifier and the second output terminal of the first amplifier. The clock control unit is used for receiving pair-wised clock signals. The feedback signal generator is coupled to the second amplifier and the clock control unit. The signal alignment unit is coupled to the second input terminal of the first amplifier, the first output terminal of the first amplifier, the second output terminal of the first amplifier, and the feedback signal generator.

Abstract: A memory device has a plurality of bit cells, each of which includes an SRAM cell having a storage node selectively connectable to a first bit line in response to a control signal received on a first word line. Each bit cell further includes an MRAM cell selectively connectable to the storage node of the SRAM cell in response to a control signal received on a second word line.

Abstract: Disclosed herein is a method for controlling a refresh period of an extension memory pool. The method includes collecting information about each of preset unit DRAM cell sets of an extension memory pool, setting an initial refresh period for each of the DRAM cell sets, and adjusting the refresh period based on the information collected from the DRAM cell sets.

Abstract: An apparatus for processing an input signal from a memory includes an attenuator circuit and an analog front end (AFE) circuit. The attenuator circuit attenuates the input signal from the memory to produce an attenuated signal. The AFE circuit includes a first amplification stage and a second amplification stage. The first amplification stage has an n-type metal-oxide semiconductor (NMOS) transistor. The NMOS transistor has a gate that receives the attenuated signal from the attenuator circuit. The second amplification stage has a p-type metal-oxide semiconductor (PMOS) transistor. The PMOS transistor has a gate that receives the attenuated signal from the attenuator circuit. Outputs of the first amplification stage and the second amplification stage are electrically coupled to a common output of the AFE circuit.

Abstract: A semiconductor memory may include: a first variable resistance element including a first terminal and a second terminal; a second variable resistance element including a first terminal, a second terminal, and a third terminal; a first transistor configured to control an electrical connection between a first conductive line and the first terminal of the first variable resistance element; a second transistor configured to control an electrical connection between the first conductive line and the first terminal of the second variable resistance element; a connection layer structured to electrically connect the second terminal of the first variable resistance element to the second and third terminals of the second variable resistance element; and a third conductive line is electrically connected to the connection layer.

Abstract: A semiconductor apparatus includes a memory cell array and a control circuit. The control circuit is configured to perform a program operation on target cells within the memory cell array, the program operation including a plurality of loops. The control circuit may be configured to apply a bit line voltage having a predetermined level to bit lines in loops in which a pass voltage having a first level is applied among the plurality of loops, and configured to apply the bit line voltage having a higher level than the predetermined level to the bit lines in loops in which the pass voltage having a second level higher than the first level is applied among the plurality of loops.

Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

Abstract: According to an embodiment, a semiconductor memory device includes a first chip, a second chip, and a third chip. In a case where a first command sequence including a first address indicating the first chip is received from the first device, the third chip performs transfer of a second command sequence including the first address via the first channel and transfer of a third command sequence including a second address indicating the second chip via the second channel. After a first time elapses from completion of the transfers of the second and third command sequences, the third chip transfers first read enable signals to the first and second channels in parallel, and acquires pieces of first status information in parallel via the first and second channels. The third chip outputs first status information to the first device.

Abstract: A dual-port static random access memory (SRAM) cell is provided. The dual-port SRAM cell includes: P-type active patterns that are spaced apart from one another along a first direction, each of the P-type active patterns extending in a second direction perpendicular to the first direction and including at least one transistor. The P-type active patterns include first through sixth P-type active patterns which are sequentially arranged along the first direction. A first cutting area is provided between the second P-type active pattern and a first boundary of the dual-port SRAM cell that extends along the first direction, and a second cutting area is provided between the fifth P-type active pattern and a second boundary that is opposite to the first boundary and extends along the first direction.

Abstract: A comparator circuit includes a first transistor, a second transistor, a load circuit, a first adjustment circuit and a second adjustment circuit. A terminal of the first transistor is coupled to a first node, another terminal of the first transistor is coupled to a first control node, and a gate of the first transistor is configured to receive a first control signal. A terminal of the second transistor is coupled to the first node, another terminal of the second transistor is coupled to a second control node, and a gate of the second transistor is configured to receive a second control signal. A terminal of the load circuit is coupled to a second node, and another terminal of the load circuit is coupled to the first control node and the second control node.

Abstract: A three-dimensional non-volatile memory includes memory blocks including layers. A data method for erasure verification of the three-dimensional non-volatile memory includes selecting a first layer from the layers on which an erase operation has been performed. The method also includes applying a first local verification voltage to a word line corresponding to the first layer to verify the erase operation on the first layer. When a full block erasure verification is performed on the memory blocks corresponding to the first layer, a voltage applied to the word line corresponding to the memory blocks is a global verification voltage, and the first local verification voltage is lower than the global verification voltage.

Abstract: A transmitter circuit includes a first driver circuit configured to drive an input/output pad in an integrated circuit device, the first driver circuit including a thin-oxide transistor configured to couple the input/output pad to a first voltage rail when the transmitter circuit is operated in a first mode; a gate pullup transistor configured to couple a gate of the thin-oxide transistor to a second voltage rail when voltage of a third voltage rail is collapsed to a zero-volt level; and a switch configured to block transmission of a gating signal to the gate of the thin-oxide transistor when the voltage of the third voltage rail is collapsed to the zero-volt level.

Abstract: Methods, systems, and devices supporting an interface for refreshing non-volatile memory are described. In some examples, a host system may communicate with a memory system, where both the host system and the memory system may be included within a vehicle (e.g., an automotive system). The host system may receive an indication that the vehicle is powering down (e.g., shutting off an engine or lowering power output from a battery). The host system may switch from a first mode corresponding to a first power usage to a second mode corresponding to a second, lower power usage in response to the vehicle powering down, the second mode supporting initiation of a refresh operation at the memory device. The host system may transmit a refresh command to the memory system to refresh non-volatile memory while the vehicle is powered down if the host system is operating in the second mode of operation.

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

Abstract: This application discloses a mechanism to securely store and compute with a matrix of numbers or any two-dimensional array of binary values in a storage entity called a matrix space. A matrix space is designed to store matrices or arrays of values into arrays of volatile or non-volatile memory cells with accessibility in two or three dimensions. Any row or column or line of storage elements in the storage entity is directly accessible for writing, reading, or clearing via row bit lines and column bit lines, respectively. The elements in rows of the arrays are selected or controlled for access using row address lines and the elements in columns of the arrays are selected or controlled for access using column address lines. Access control methods and mechanisms with keys to secure, share, lock, and unlock regions in the matrix space for matrices and arrays under the control of an operating system or a virtual-machine hypervisor by permitted threads and processes are also disclosed.

Abstract: A system includes a memory device with microbumps and a processing device. The processing device is operatively coupled with the memory device to perform operations. The operations include receiving information indicating a current condition of the machine learning operation while data for the machine learning operation is being transmitted using a first set of microbumps of the plurality of microbumps. Furthermore, the operations include, in response to a change in the condition of the machine learning operation, transmitting subsequent data using a second set of microbumps of the plurality of microbumps, wherein a number of microbumps included in the second set of microbumps is based on the received information.

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.

Abstract: A refresh address generation circuit includes: a refresh control circuit and an address generator. The refresh control circuit receives multiple first refresh commands in sequence and performs multiple first refresh operations accordingly, outputs a first clock signal when the number of first refresh operations is less than m, and outputs a second clock signal when the number of first refresh operation is equal to m. The address generator is coupled to the refresh control circuit, and configured to prestore a first address and receive the first clock signal or the second clock signal, and during each first refresh operation, output an address to be refreshed in response to the first clock signal and change the first address in response to the second clock signal. The address to be refreshed includes a first address and a second address with the lowest bit opposite to that of the first address.

Abstract: A memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. A first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. The first bitcell is coupled to a first of the source lines. The second bitcell is coupled to a second of the source lines. The first source line is different from the second source line.

Abstract: A variable resistance memory device includes a first conductive line extending on a substrate in a first horizontal direction; a second conductive line extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction; and a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell including a selection element and a variable resistor, wherein the variable resistor includes a first variable resistance layer having a senary component represented by CaGebSbcTedAeXf, in which A and X are each a group 13 element different from each other, and 1?a?18, 13?b?26, 15?c?30, 35?d?55, 0.1?e?8, 0.1?f?8, and a+b+c+d+e+f=100.