Patents Examined by Min Huang
  • Patent number: 11120865
    Abstract: Apparatuses and methods for implementing access line loads for sense amplifiers for open access line sensing. An example apparatus may include a memory array comprising a plurality of sense amplifiers. A first sense amplifier is coupled to a first access line segment and to a second access line segment and a second sense amplifier is coupled to a third access line segment and to a load segment. The first, second, and third access line segments are coupled to a respective plurality of memory cells. The load segment comprise load circuitry configured to provide a capacitive load to the second sense amplifier based on a capacitive load of the third access line segment.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Simone Levada
  • Patent number: 11120843
    Abstract: A memory device includes a first semiconductor chip including a memory cell array disposed on a first substrate, and a first bonding metal on a first uppermost metal layer of the first semiconductor chip, and a second semiconductor chip including circuit devices disposed on a second substrate and a second bonding metal on a second uppermost metal layer of the second semiconductor chip, the circuit devices providing a peripheral circuit operating the memory cell array. The first and second semiconductor chips are electrically connected to each other by the first bonding metal and the second bonding metal in a bonding area. A routing wire electrically connected to the peripheral circuit is disposed in one or both of the first and second uppermost metal layers and is disposed in a non-bonding area in which the first and second semiconductor chips are not electrically connected to each other.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: September 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jooyong Park, Chanho Kim, Daeseok Byeon
  • Patent number: 11107549
    Abstract: A volatile memory device is configured to self-document by identifying its own bad or at-risk excludable memory locations in a nonvolatile identification embedded in itself, without using additional board real estate. The identification of bad or at-risk memory is readable by firmware outside the device. The device includes volatile memory cells that have respective failure susceptibility values, some of which indicate bad or at-risk memory cells. The memory device also includes read logic and write logic, and may include refresh logic. The identification may be embedded in the device by blowing fuses in an adaptation of self-repair activity, or by writing identification data into a serial presence detect logic, for example. The configured memory device may efficiently, persistently, and reliably provide detailed memory test results regarding itself, thereby allowing customers to accept and safely use memory that would otherwise have been discarded to prevent software crashes.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: August 31, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Timothy B. Cowles, Terry M. Grunzke
  • Patent number: 11100978
    Abstract: There is provided a method for accessing a memory cell of a plurality of memory cells that are part of a memory unit, the memory cells being grouped into a plurality of memory cell groups, wherein each memory cell group is associated with one or more local bit lines with each of the one or more local bit lines being operatively connected to a corresponding global bit line via a passgate comprising a PMOS transistor. The method comprises connecting each of the one or more local bit lines to the corresponding global bit line by decreasing a gate voltage that is applied to a gate of the corresponding PMOS transistor to a value that is sufficient to allow the PMOS transistor to conduct, wherein the value of the gate voltage that is sufficient to allow the PMOS transistor to conduct is either a positive or negative voltage.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: August 24, 2021
    Assignee: Surecore Limited
    Inventors: Stefan Cosemans, Bram Rooseleer
  • Patent number: 11101006
    Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: August 24, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard David Barndt, Aldo Giovanni Cometti, Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran, Anthony Dwayne Weathers
  • Patent number: 11094357
    Abstract: A memory device includes a memory array with memory blocks each having a plurality of memory cells, and one or more current monitors configured to measure current during post-deployment operation of the memory device; and a controller configured to identify a bad block within the memory blocks based on the measured current, and disable the bad block for preventing access thereof during subsequent operations of the memory device.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Aaron S. Yip, Theodore T. Pekny
  • Patent number: 11094367
    Abstract: Provided are a sub-amplifier, a switching device and a semiconductor device capable of simultaneously reading or writing many data items, while suppressing an increase in chip surface area, by using a single end signal line. A sub-amplifier SAP comprises: a first pre-charge circuit 110 that releases pre-charges of a pair of local wires LIOT/LIOB; a local inversion drive circuit 120 that, on the basis of a write signal WT, inverts and transfers write data to a sense amplifier SA from a main wire MIOB via one of the local wires LIOT/LIOB; a local non-inversion drive circuit 130 that, on the basis of the write signal WT, transfers the write data to the sense amplifier SA from the main wire MIOB via the other one of the local wires LIOT/LIOB; and a main inversion drive circuit 140 that, on the basis of a read signal RT, inverts and transfers read data to the main wire MIOB from one of the local wires LIOT/LIOB.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: August 17, 2021
    Assignee: ULTRAMEMORY INC.
    Inventor: Yasutoshi Yamada
  • Patent number: 11094395
    Abstract: An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: August 17, 2021
    Assignee: Apple Inc.
    Inventors: Shahzad Nazar, Mohamed H. Abu-Rahma, Amrinder S. Barn
  • Patent number: 11088204
    Abstract: A memory device includes a first electrode, a non-volatile memory element having a first terminal and a second terminal, where the first terminal is coupled to the first electrode. The memory device further includes a selector having a first terminal, a second terminal and a sidewall between the first and second terminals, where the second terminal of the selector is coupled to the first terminal of the non-volatile memory element. A second electrode is coupled to the second terminal of the selector and a third electrode laterally adjacent to the sidewall of the selector.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: August 10, 2021
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Willy Rachmady
  • Patent number: 11087812
    Abstract: A MRAM includes a plurality of memory cells, an operation unit, a voltage generator, and an input/output circuit. The operation unit includes multiple groups of memory cells among the plurality of memory cells. The voltage generator is configured to provide a plurality of control signals by voltage-dividing a voltage control signal and selectively output the plurality of control signals to the input/output circuit. The input/output circuit is configured to output a plurality of switching pulse signals to the multiple groups of memory cells according to the plurality of control signals, wherein each switching pulse signal differs in pulse width or level.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: August 10, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Hui Lee, I-Ming Tseng, Chiu-Jung Chiu, Chung-Liang Chu, Yu-Chun Chen, Ya-Sheng Feng, Yi-An Shih, Hsiu-Hao Hu, Yu-Ping Wang
  • Patent number: 11081189
    Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums for compensating for charge loss effects. In some examples, a charge loss may be estimated by a charge loss monitor for a particular unit of a NAND device and may be utilized to select a charge loss compensation scheme. The charge loss may be estimated by the charge loss estimation process by determining a reference read voltage and calculating a bit count resulting from a read at that reference read voltage. The number of bits returned may be used to select the particular charge loss compensation scheme.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kalyan Chakravarthy C. Kavalipurapu, Jung Sheng Hoei
  • Patent number: 11074972
    Abstract: A semiconductor circuit of the present disclosure includes: a first circuit that is configured to apply an inverted voltage of a voltage at a first node to a second node; a second circuit that is configured to apply an inverted voltage of a voltage at the second node to the first node; a first transistor that is configured to couple the first node to a third node to which a first memory element is coupled; a second transistor having a drain coupled to the third node and a gate coupled to a first predetermined node; a third transistor having a drain coupled to the third node and a gate coupled to a second predetermined node; a fourth transistor that is configured to couple the second node to a fourth node to which a second memory element is coupled; a fifth transistor having a drain coupled to the fourth node and a gate coupled to the second predetermined node; and a sixth transistor having a drain coupled to the fourth node and a gate coupled to the first predetermined node.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: July 27, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yusuke Shuto
  • Patent number: 11074985
    Abstract: A semiconductor device including at least an OTP unit cell is disclosed. The OTP unit cell includes a read select transistor, a data storage transistor serially connected to the read select transistor, and a program select transistor. The drain of the program select transistor is electrically coupled to the gate of the data storage transistor. The programming path for programming the three-transistor unit cell is different from the reading path for reading the OTP unit cell.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: July 27, 2021
    Assignee: HeFeChip Corporation Limited
    Inventor: Geeng-Chuan Chern
  • Patent number: 11074963
    Abstract: A non-volatile memory includes a memory cell array, an amplifying circuit and a first multiplexer. The memory cell array includes m×n memory cells. The memory cell array is connected with a control line, m word lines and n local bit lines, wherein m and n are positive integers. The amplifying circuit includes n sensing elements. The n sensing elements are respectively connected between the n local bit lines and n read bit lines. The first multiplexer is connected with the n local bit lines and the n read bit lines. According to a first select signal, the first multiplexer selects one of the n local bit lines to be connected with a first main bit line and selects one of the n read bit lines to be connected with a first main read bit line.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: July 27, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Yu-Ping Huang, Chun-Hung Lin, Cheng-Da Huang
  • Patent number: 11069394
    Abstract: Methods, apparatuses, and systems for staggering refresh operations to memory arrays in different dies of a three-dimensional stacked (3DS) memory device are described. A 3DS memory device may include one die or layer of that controls or regulates commands, including refresh commands, to other dies or layers of the memory device. For example, one die of the 3DS memory may delay a refresh command when issuing the multiple concurrent memory refreshes would cause some problematic performance condition, such as high peak current, within the memory device.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Matthew A. Prather, Thomas H. Kinsley
  • Patent number: 11069413
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller that controls operation of the nonvolatile memory. The nonvolatile memory is configured to receive, from the memory controller, a first command for execution of at least one of an erase operation and a program operation; in response to receiving a second command from the memory controller during execution of a first operation requested by the first command, execute a second operation for suspending the first operation before the first operation reaches a given section; and in response to receiving a third command from the memory controller during the execution of the first operation, suspend the first operation after the given section.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: July 20, 2021
    Assignee: Kioxia Corporation
    Inventors: Suguru Nishikawa, Riki Suzuki, Yoshihisa Kojima
  • Patent number: 11069390
    Abstract: Spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) cells that undergo perpendicular magnetization switching in the absence of an in-plane magnetic field and methods for their operation are provided. The SOT-MRAM cells use cobalt-iron-boron alloys, cobalt-iron alloys, metallic cobalt, and/or metallic iron as the ferromagnetic free layer in a magnetic tunnel junction. By designing the ferromagnetic layer with appropriate lateral dimensions and operating the SOT-MRAM cells with an appropriate charge current density, deterministic perpendicular magnetization switching is achieved without the need to apply an external in-plane bias collinear with the charge current.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: July 20, 2021
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Jiamian Hu, Minyi Dai
  • Patent number: 11061617
    Abstract: Fractional bit storage is disclosed herein which allows for storage of additional bits distributed over multiple SSD cells and maximizes data stored for SSD cells with non-binary amounts of allowable threshold voltages while minimizing required bits dedicated to error correction code (ECC). For an SSD cell with twenty-four levels of threshold voltage, set partitioning is used to create three equal subsets of levels each corresponding to eight levels of threshold voltage and each partitioned subset able to encode three bits. Each partitioned subset is designed with eight allowable threshold voltage ranges, each of which is separated from any other allowable threshold voltage range by at least two of the twenty-four levels of maximum threshold voltage. By choosing both set partitioning and assigning bit values determined via code modulation, bits stored within a partitioned subset are protected without the need for additional ECC.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: July 13, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Vijay Ahirwar, B Hari Ram, Sri Varsha Rottela, Nilesh N Khude
  • Patent number: 11061577
    Abstract: A system on chip includes a first clock generator that generates a first clock to be sent to a memory device, a second clock generator that generates a second clock to be sent to the memory device, a command and address generator that generate a code for adjusting a duty cycle of a third clock generated within the memory device based on the second clock and generates a command for storing the code to mode registers of the memory device, the third clock being used for a data input/output of the memory device, a data receiver that receives a data strobe signal and a data input/output signal output from the memory device receiving the command and the code synchronized with the first clock, and a training circuit that calculates a plurality of valid window margins for the code based on the data strobe signal and the data input/output signal.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: July 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yongseob Kim
  • Patent number: 11056159
    Abstract: A data acquisition method of acquiring and latching data with a timing based on an input signal supplied to an input port, the method including: acquiring and retaining the data with a timing of when an edge of the input signal is detected, and starting a timer; and at the time of expiration of the timer, if the level of the input signal is a first level that is unchanged from start of the timer, latching the retained data and if the level of the input signal is a second level that is changed from the start of the timer, discarding the retained data.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: July 6, 2021
    Assignee: OMRON Corporation
    Inventor: Kotaro Asaba