Patents Examined by Min Huang
  • Patent number: 10559376
    Abstract: A data storage device can have at least a buffer memory, a selection module, and a non-volatile memory. The buffer memory and non-volatile memory may consist of different types of memory while the non-volatile memory has one or more rewritable in-place memory cells. The buffer memory and non-volatile memory may each store data associated with a pending data request as directed by the selection module until a settle time of the rewritable in-place memory cell has expired.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: February 11, 2020
    Assignee: Seagate Technology LLC
    Inventors: Timothy Canepa, Mark Ish, David S. Ebsen
  • Patent number: 10559356
    Abstract: A memory circuit includes a plurality of memory tiles. Each memory tile in the plurality of memory tiles includes a plurality of bit cells and a control circuit coupled to the plurality of bit cells. The control circuit is configured to provide latched data to the plurality of bit cells during write operations. A first write control line is coupled to the control circuit in a first memory tile, and the first write control line is configured to initiate a first write operation in the first memory tile. And a second write control line is coupled to the control circuit in a second memory tile, and the second write control line configured to initiate a second write operation in the second memory tile. The second write operation may be initiated before the first write operation is completed.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: February 11, 2020
    Assignee: NXP USA, INC.
    Inventors: Perry H. Pelley, Anirban Roy, Gayathri Bhagavatheeswaran
  • Patent number: 10559336
    Abstract: A memory controller is used to control a first storage block having a first data rate and a second storage block having a second data rate. The memory controller includes; a memory interface that transceives a data signal and a data strobe signal with the first and second storage blocks, and a sub controller that stores access information about the first data rate and the second data rate. The sub controller may include a delay lookup table storing access information including first strobe adjustment timing information defining a first data strobe signal provided to the first storage block, and second strobe adjustment timing information defining a second data strobe signal provided to the second storage block.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: February 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeon-Wu Kim, Seok-Won Ahn, Chan-Ho Yoon
  • Patent number: 10552755
    Abstract: Techniques for improving the performance of a quantum processor are described. Some techniques employ reducing intrinsic/control errors by using quantum processor-wide problems specifically crafted to reveal errors so that corrections may be applied. Corrections may be applied to physical qubits, logical qubits, and couplers so that problems may be solved using quantum processors with greater accuracy.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: February 4, 2020
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Trevor Michael Lanting, Andrew King
  • Patent number: 10552328
    Abstract: There are provided a memory controller for controlling a memory device to perform a more stable sensing operation, a storage device including the memory controller, and an operating method of the storage device. A memory controller includes: a processor for transmitting a cache read command to a memory device and then transmitting a status read command to the memory device; and a cache read controller for outputting a data-out command to the memory device according to a sensing section code included in a status read response transmitted by the memory device in response to the status read command.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: February 4, 2020
    Assignee: SK hynix Inc.
    Inventor: Sok Kyu Lee
  • Patent number: 10541033
    Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: January 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Taeck Jung, Sang-Wan Nam, Jinwoo Park, Jaeyong Jeong
  • Patent number: 10541021
    Abstract: Apparatuses and methods for implementing access line loads for sense amplifiers for open access line sensing. An example apparatus may include a memory array comprising a plurality of sense amplifiers. A first sense amplifier is coupled to a first access line segment and to a second access line segment and a second sense amplifier is coupled to a third access line segment and to a load segment. The first, second, and third access line segments are coupled to a respective plurality of memory cells. The load segment comprise load circuitry configured to provide a capacitive load to the second sense amplifier based on a capacitive load of the third access line segment.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: January 21, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Simone Levada
  • Patent number: 10535386
    Abstract: Various implementations described herein refer to an integrated circuit having level shifting circuitry and bypass switching circuitry. The level shifting circuitry is arranged for translating an input signal from a first voltage domain to an output signal for a second voltage domain. The bypass switching circuitry is arranged for activating and deactivating the level shifting circuitry based on a bypass control signal.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: January 14, 2020
    Assignee: ARM Limited
    Inventors: Andy Wangkun Chen, Yew Keong Chong, Rahul Mathur, Abhishek Baradia, Hsin-Yu Chen
  • Patent number: 10520557
    Abstract: Systems, devices, and methods for recording and transmitting data are provided. The systems, devices, and methods can be used in a variety of contexts, including in conjunction with swinging devices and prosthetics. In one exemplary embodiment, the sensor is configured in a manner that allows it be omni-directional such that its orientation with respect to the object for which it is detecting data is irrelevant to the ability to accurately record and transmit data. In another exemplary embodiment, the system allows a user to use the same sensor across multiple platforms, such as using it for golf and prosthetics, for golf and tennis, or for a regular golf swing and a putting stroke. Other devices, systems, methods, and uses of the same are also provided.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: December 31, 2019
    Assignee: ARTHROKINETIC INSTITUTE, LLC
    Inventors: Eric Sanchez, Robert Woods, John Stump, Daniel Price
  • Patent number: 10520427
    Abstract: A method for evaluating the quality of a component produced by means of an additive laser sintering and/or laser melting method, in particular a component for an aircraft engine comprises at least the steps of providing a first data set, which comprises spatially resolved color values, which each characterize the temperature of the component at an associated component location during the laser sintering and/or laser melting of the component, providing a second data set, which comprises spatially resolved color values corresponding to the first data set, which color values each characterize the temperature of a reference component at an associated reference component location during the laser sintering and/or laser melting of the reference component.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: December 31, 2019
    Assignee: MTU Aero Engines AG
    Inventors: Thomas Hess, Gunter Zenzinger, Wilhelm Satzger
  • Patent number: 10520304
    Abstract: The present invention relates to a distance sensor suitable for calculating a processed distance of a target object without contact, including: a contactless measuring circuit suitable for emitting an output signal proportional to the distance of said target object for a plurality of time intervals, so as to obtain a plurality of measurements of the distance of said target object without contact; a first processor circuit suitable for processing said output signals coming from said measuring circuit, so as to calculate a first average distance from said target object based on the average of N distance measurements in output coming from said measuring circuit, said N measurements being consecutive in time and including the last distance measurement emitted by said measuring circuit; a second processor circuit suitable for processing said output signals coming from said measuring circuit, so as to calculate a second average distance from said target object based on the average of M distance measurements in outp
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: December 31, 2019
    Assignee: Datalogic IP Tech, S.r.l.
    Inventors: Salvatore Valerio Cani, Enrico Lorenzoni
  • Patent number: 10522195
    Abstract: There are provided a memory system and a method for operating the same. A memory system includes: a controller configured to generate and output a first command corresponding to a normal operation or a second command corresponding to a deep power down (DPD) mode; and a semiconductor memory device configured to perform the normal operation in response to the first command, wherein the normal operation is performed using an internal power voltage generated by down-converting a first external power voltage, and operate in the DPD mode in response to the second command, wherein, in the DPD mode, the semiconductor memory device operates using a second external power voltage as the internal powervoltage.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: December 31, 2019
    Assignee: SK hynix Inc.
    Inventor: Hyun Chul Lee
  • Patent number: 10504570
    Abstract: When the same processing as initial training is executed to cope with fluctuation in the timing of a signal, the performance of a semiconductor device utilizing the relevant memory is degraded. A delay adjustment circuit adjusts a delay amount of write data to a memory device. A control circuit sets a delay amount of the delay adjustment circuit. A storage unit stores a delay amount. The control circuit corrects the delay amount stored in the storage unit based on a writing result of write data obtained when the delay amount stored in the storage unit or an amount based on that delay amount is set on the delay adjustment circuit.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: December 10, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takayuki Hotaruhara
  • Patent number: 10497446
    Abstract: According to one embodiment, a memory system includes a memory and controller. The controller repeatedly performs an erase voltage application process for data stored in a target area in the memory. The controller performs an erase verification process for determining whether the erase is successful using erase verification voltage. The controller determines whether an erase time is longer than a first threshold value. The controller sets the target area to a use prohibition state when the erase time is longer than the first threshold value.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: December 3, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kazutaka Takizawa, Masaaki Niijima
  • Patent number: 10490602
    Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Russell L. Meyer, Agostino Pirovano, Lorenzo Fratin
  • Patent number: 10489068
    Abstract: The disclosure proposes a circuit including a memory which has a multiplicity of memory cells, the memory having a first area and a second area, at least one memory cell comprising a part of the first area and a part of the second area, the first area having a lower reliability than the second area, and the circuit being set up in such a manner that first bits are stored in the first area and second bits are stored in the second area. A circuit for reading the memory and methods for writing to and reading the memory are also disclosed.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: November 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Michael Goessel, Albrecht Mayer
  • Patent number: 10490242
    Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Masoud Zamani, Bilal Zafar, Venkatasubramanian Narayanan
  • Patent number: 10481659
    Abstract: An approach to managing power distribution to computing devices, the approach involving monitoring power consumption of a plurality of computing devices and power draw on a plurality of power distribution units, wherein the plurality of power distribution units distribute power to the plurality of computing devices, determining that any of the plurality of power distribution units are approaching respective power thresholds and responsive to determining that any of the plurality of power distribution units are approaching the respective power thresholds, taking one or more actions to manage power distribution to the plurality of computing devices, wherein the one or more actions are based on a set of rules and the one or more actions comprise configuring a drawing of unequal amounts of power.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kenneth T. Gambon, Bret W. Lehman, Christopher L. Molloy, Tenley D. Jackson
  • Patent number: 10481676
    Abstract: The systems and methods provided herein acquire a command over multiple clock cycles and fires it. When a chip select signal (CS) transitions, a first portion of a command address is captured in a first clock cycle after the CS transitions. Then, a second portion of the command address is captured in a second clock cycle immediately after the first clock cycle or in a third clock cycle immediately following the second clock cycle. An internal command is fired, using the first portion of the command address and the second portion of the command address.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kallol Mazumder, Parthasarathy Gajapathy
  • Patent number: 10482954
    Abstract: A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Roberto Bez, Ferdinando Bedeschi, Roberto Gastaldi