Abstract: A synchronization circuit for an interconnection protocol, a controller and a storage device are provided. The synchronization circuit includes a first synchronization circuit module and a second synchronization circuit module. The first synchronization circuit module converts first control information of a first clock domain output by a data link layer receiver of the first device into second control information of a second clock domain, and outputs the second control information of the second clock domain. The second synchronization circuit module is coupled to the first synchronization circuit module, and converts the second control information of the second clock domain output by the first synchronization circuit module into third control information of a third clock domain to be output to a data link layer transmitter of the first device. Any two among the first, second and third clock domains are asynchronous.

Abstract: Apparatuses including a level shifter circuit are disclosed. An example apparatus according to the disclosure includes a plurality of array access control circuits and a level shifter circuit. The plurality of array access control circuits receive an access control signal and a respective plurality of section enable signals. An array access control circuit of the plurality of array access control circuits provides a section access control signal responsive to the access control signal when a respective section enable signal is in an active state. The level shifter circuit receives a control signal and provides an access control signal responsive to the first signal. A first logic level of the control signal is represented by a first power supply voltage and a first logic level of the access control signal is represented by a second power supply voltage greater than the first power supply voltage.

Abstract: An arbiter is operable to pick commands from a command queue for dispatch to a memory. The arbiter includes a traffic throttle circuit for mitigating excess power usage increases in coordination with one or more additional arbiters. The traffic throttle circuit includes a monitoring circuit and a throttle circuit. The monitoring circuit is for measuring a number of read and write commands picked by the arbiter and the one or more additional arbiters over a first predetermined period of time. The throttle circuit, responsive to a low activity state, limits a number of read and write commands issued by the arbiter during a second predetermined period of time.

Abstract: Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a method can include receiving a command to perform a precharge operation on a set of memory cells in a memory device. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The method can further include accessing one or more sets of bits in a mode register. The one or more sets of bits in the mode register indicate address locations of the plurality of sets of memory cells to disable the flip on precharge operation. The method can further include performing the precharge operation on the set of memory cells. The flip on precharge operation associated with the precharge operation can be disabled for those sets of the plurality of sets of memory cells whose address locations are in the mode register.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cell strings, a peripheral circuit configured to, using a plurality of read voltages, perform a read operation that reads data that is stored in a selected memory cell that is included in a selected memory cell string, and an operation controller configured to control the peripheral circuit to perform the read operation by using a first read voltage, a first potential adjustment operation, and the read operation by using a second read voltage that is lower than the first read voltage, wherein the first potential adjustment operation is an operation that applies a first turn-on voltage to unselected source select lines that are coupled to unselected memory cell strings for a first period and thereafter applies a ground voltage to the unselected source select lines.

Abstract: A memory such as a 3D NAND array, having a page buffer having page buffer cells coupled to bit lines has a search word input such as a search word buffer coupled to word lines. A circuit, such as string select gates, is provided to connect a selected set of memory cells in the array to the page buffer. The page buffer includes sensing circuitry configured to apply a match sense signal to a latch in a plurality of storage elements for a stored data word and an input search word. Logic circuitry uses storage elements in the plurality of storage elements of the page buffer to accumulate the match sense signals output by the sensing circuitry over a sequence matching a plurality stored data words to one or more input search words. A match for a search is based on a threshold and the accumulated match sense signals.

Abstract: Disclosed herein are molecular storage systems and methods of reading molecules that include integrity markers. A molecular storage system may comprise read hardware configured to read molecules storing data, and at least one processor coupled to the read hardware. The processor is configured to determine whether a molecule being read by the read hardware includes an expected integrity marker, and, in response to a determination that the molecule being read by the read hardware does not include the expected integrity marker, instruct the read hardware to abandon a read operation associated with the molecule being read by the read hardware. The partial readback can be placed in a buffer and used in an assembly process only if an intact molecule is not available.

Abstract: A resistive random access memory structure includes a first inter-layer dielectric layer; a bottom electrode disposed in the first inter-layer dielectric layer; a capping layer disposed on the bottom electrode and on the first inter-layer dielectric layer; and a through hole disposed in the capping layer. The through hole partially exposes a top surface of the bottom electrode. A variable resistance layer is disposed within the through hole. A top electrode is disposed within the through hole and on the variable resistance layer. A second inter-layer dielectric layer covers the top electrode and the capping layer.

Abstract: A nonvolatile memory device having a multi-stack memory block includes: a memory cell array divided into a plurality of memory stacks disposed in a vertical direction; and a control circuit configured to perform a channel voltage equalization operation of the plurality of memory stacks, wherein inter-stack portions are between the plurality of memory stacks, and a channel hole passes through the word lines of each of the plurality of memory stacks. The control circuit determines, as inter-stack word lines, some word lines adjacent to the inter-stack portions among the word lines of each of the plurality of memory stacks and differently controls setup time points for applying a pass voltage, or recovery time points for applying a ground voltage, to the inter-stack word lines, according to sizes of the channel hole of the inter-stack word lines.

Abstract: A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input/output (I/O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.

Abstract: A method for determining a target locking time for a delay locked loop of a memory apparatus are provided. The method includes, a system inputting a first set of input signals to the memory apparatus in accordance with a first set of first operational parameters and a set of second operational parameters, the system measuring a first set of output signals from the memory apparatus in response to the first set of input signals to determine whether the delay locked loop fails at any combination of the first set of first operational parameters and the set of second operational parameters, the system determining a first candidate operational parameter from the first set of first operational parameters under which the delay locked loop does not fail for each of the set of second operational parameters, and the system determining the target locking time based on the first candidate operational parameter.

Abstract: The present application provides a sense amplifier, a memory, and a control method. The sense amplifier includes: an amplification module, configured to amplify a voltage difference between a bit line and a reference bit line when the sense amplifier is at an amplification stage; and a controlled power module, connected to the amplification module, and configured to: determine a drive parameter according to a rated compensation voltage range between the bit line and the reference bit line, and supply power to the amplification module according to the drive parameter, so as to control the amplification module to pull a compensation voltage between the bit line and the reference bit line to be a rated compensation voltage at an offset cancellation stage, where the rated compensation voltage is within the rated compensation voltage range.

Abstract: A method including obtaining temperature values of at least one region of the non-volatile memory, each temperature value obtained at a given time instant, for each obtained temperature value at each given time instant, calculating the value of an operating function representative of an operating condition of the non-volatile memory, the value such operating function being time-dependent according to the temperature time-variation of such at least one region of the non-volatile memory, summing subsequent computed values of said operating function to obtain an accumulated value being representative of an elapsed fraction of a time limit associated with the at least one region of the non-volatile memory, comparing the accumulated value with a threshold value, and, based on said comparison, performing a management operation on the cells of the at least one region of the non-volatile memory when the accumulated value has a magnitude equal or greater than the threshold value.

Abstract: In order to decrease the width of threshold voltage distributions of programmed memory cells without unreasonably increasing the time needed to complete programming, a non-volatile memory uses a zone based program speed adjustment. The non-volatile memory starts programming a first set of the non-volatile memory cells until a minimum number of memory cells of the first set of non-volatile memory cells reach a first threshold voltage. In response to the minimum number of memory cells reaching the first threshold voltage, the first set of non-volatile memory cells are categorized into zones/groups based on threshold voltage. The speed of programming is then adjusted differently for each zone/group and programming is completed for the first set of non-volatile memory cells.

Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.

Abstract: A semiconductor memory device includes a memory cell array and a control circuit configured to receive a first command set, reject a second command set related to a write operation or an erase operation, in a first time period of executing a first operation on the memory cell array in response to the first command set, receive a third command set related to a read operation in the first time period, and execute the read operation on the memory cell array in response to the third command set.

Abstract: A memory device is provided. A first sub-block of the memory device includes first memory cells arranged in a first row and connected to a first bit line and second of memory cells arranged in a second row and connected to a first complementary bit line. The first memory cells and the second memory cells are connected to word lines in a first connection pattern. A second sub-block of the memory device includes third memory cells arranged in a third row and connected to a second bit line and fourth memory cells arranged in a fourth row and connected to a complementary second bit line. The third memory cells and the fourth memory cells are connected to the word lines in a second connection pattern that is different from the first connection pattern.

Abstract: Semiconductor devices are provided. A memory cell includes a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor, and a second pass-gate transistor formed over a P-type well region, and a first pull-up transistor, a second pull-up transistor, a first isolation transistor, and a second isolation transistor formed over an N-type well region. The first and second pull-down transistors and the first and second pass-gate transistors share a first active region. The first and second pull-up transistors and the first and second isolation transistors share a second active region. The gates of the first and second isolation transistors are electrically connected to a VDD line. The gates of the first and second pass-gate transistors are electrically connected to a WL landing pad. The sources of the first and second pass-gate transistors are electrically connected to the first bit line and the second bit line, respectively.

Abstract: A computing device in some examples includes an array of memory cells, such as 8-transisor SRAM cells, in which the read bit-lines are isolated from the nodes storing the memory states such that simultaneous read activation of memory cells sharing a respective read bit-line would not upset the memory state of any of the memory cells. The computing device also includes an output interface having capacitors connected to respective read bit-lines and have capacitance that differ, such as by factors of powers of 2, from each other. The output interface is configured to charge or discharge the capacitors from the respective read bit-lines and to permit the capacitors to share charge with each other to generate an analog output signal, in which the signal from each read bit-line is weighted by the capacitance of the capacitor connected to the read bit-line. The computing device can be used to compute, for example, sum of input weighted by multi-bit weights.

Abstract: A memory device includes: a memory bank including a plurality of memory cells; and a memory interface circuit configured to store data in the plurality of memory cells based on a command/address signal and a data signal, wherein the memory interface circuit includes: first, second, third and fourth pads configured to receive first, second, third and fourth clock signals, respectively; a first buffer circuit configured to sample the command/address signal in response to an activation time of the first and third clock signals which have opposite phases from each other; and a second buffer circuit configured to sample the data signal in response to the activation time of the first clock signal, an activation time of the second clock signal, the activation time of the third clock signal and an activation time of the fourth clock signal.