Patents Examined by Min Huang
  • Patent number: 11456030
    Abstract: A static random access memory SRAM unit and a related apparatus are provided, to reduce power consumption of an SRAM when the SRAM memory is accessed. The SRAM unit is located in an SRAM memory, and the SRAM memory includes an SRAM storage array including a plurality of SRAM units. The SRAM unit includes: a storage circuit, connected to each of a write circuit and a read circuit, and configured to store data; the write circuit, configured to write data into the storage circuit; and the read circuit, configured to: after a read enabling signal is valid, enable data on a read bit line connected to the SRAM unit to be the data stored in the storage circuit.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: September 27, 2022
    Assignees: Huawei Technologies Co., Ltd., Tsinghua University
    Inventors: Han Xu, Fei Qiao, Miao Zheng
  • Patent number: 11450401
    Abstract: A location of at least one fail bit to be repaired in a memory block of a memory is extracted from at least one memory test on the memory block. An available repair resource in the memory for repairing the memory block is obtained. It is determined whether a Constraint Satisfaction Problem (CSP) containing a plurality of constraints is solvable. The constraints correspond to the location of the at least one fail bit in the memory block, and the available repair resource. In response to determining that the CSP is not solvable, the memory block is marked as unrepairable or the memory is rejected. In response to determining that the CSP is solvable and has a solution satisfying the constraints, the at least one fail bit is repaired using the available repair resource in accordance with the solution of the CSP.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Katherine H. Chiang, Chien-Hao Huang, Cheng-Yi Wu, Chung-Te Lin
  • Patent number: 11450391
    Abstract: A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: September 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Karl D. Schuh, Jiangang Wu, Devin M. Batutis, Xiangang Luo
  • Patent number: 11450672
    Abstract: An ultra-deep compute Static Random Access Memory (SRAM) with high compute throughput and multi-directional data transfer capability is provided. Compute units are placed in both horizontal and vertical directions to achieve a symmetric layout while enabling communication between the compute units. An SRAM array supports simultaneous read and write to the left and right section of the same SRAM subarray by duplicating pre-decoding logic inside the SRAM array. This allows applications with non-overlapping read and write address spaces to have twice the bandwidth as compared to a baseline SRAM array.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: September 20, 2022
    Assignee: Intel Corporation
    Inventors: Charles Augustine, Somnath Paul, Muhammad M. Khellah, Chen Koren
  • Patent number: 11450383
    Abstract: A semiconductor storage device includes: a first memory cell and a second memory cell that are adjacent to each other and connected to each other in series; a first word line connected to the first memory cell; a second word line connected to the second memory cell; and a control circuit. The control circuit is configured to, in a first read operation to read a first bit stored in the first memory cell, apply a first voltage to the first word line, and then, apply a first read voltage lower than the first voltage, to the first word line, and apply a second voltage to the second word line, and then, apply a third voltage lower than the second voltage and higher than the first voltage, to the second word line. The third voltage is applied to the second word line after the first read voltage is applied to the first word line.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: September 20, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Hiroki Date, Takeshi Nakano
  • Patent number: 11443782
    Abstract: An electronic device may include: a column control circuit configured to generate a column control pulse and a mode register enable signal, each with a pulse that is generated based on logic levels of a chip selection signal and a command address; and a control circuit configured to generate a read control signal to perform a read operation and a mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal and configured to generate a mode register control signal to perform the mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: September 13, 2022
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 11443795
    Abstract: A SRAM system having an address scheme and/or wire control layout. By preferentially accessing a defined address range mapped to SRAM array blocks located near a controller, significant power savings can be realized. In one embodiment, the address scheme determines a range physically closer to a central control location. In another embodiment, the wire control layout reduces number and length of active wires, further reducing power consumption.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: September 13, 2022
    Assignee: Ambiq Micro, Inc.
    Inventor: Christophe J. Chevallier
  • Patent number: 11430493
    Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: August 30, 2022
    Assignee: QUALCOMM INCORPORATED
    Inventors: Seyed Arash Mirhaj, Ankit Srivastava, Sameer Wadhwa, Ren Li, Suren Mohan
  • Patent number: 11430501
    Abstract: According to one embodiment, a memory system is disclosed. The system includes a nonvolatile memory, a controller which controls the nonvolatile memory and to which a first voltage is supplied, and a circuit to which first and second signals from a host device are input, or the first signal is not input and the second signal is input from the host device, when the memory system is connected to the host device. The circuit converts a second voltage of the second signal into the first voltage when the first and second signal have the second voltage and the second voltage is lower than the first voltage, and does not convert a voltage of the second signal into the first voltage when the first signal is not input and the voltage of the second signal is the first voltage.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: August 30, 2022
    Assignee: Kioxia Corporation
    Inventor: Hajime Matsumoto
  • Patent number: 11430511
    Abstract: In an example, a method may include comparing input data to stored data stored in a memory cell and determining whether the input data matches the stored data based on whether the memory cell snaps back in response to an applied voltage differential across the memory cell.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Hernan A. Castro
  • Patent number: 11423956
    Abstract: The present invention provides a sensitivity amplifier, its control method, a memory read-write circuit and a memory device. The sensitivity amplifier includes: a first PMOS transistor and a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, a first input/output terminal, and a second input/output terminal; four switch unit, the first PMOS and the first NMOS transistors are respectively connected to the first input/output terminal through one switch unit, the second PMOS and the second NMOS transistors are respectively connected to the second input/output terminal through another switch unit. The switch units configure each PMOS transistor and each NMOS transistor in an amplifier mode or in a diode mode. The first NMOS transistor's gate connects to the bit line, and the second NMOS transistor's gate connects to the reference bit line. The disclosed sensitivity amplifier has improved performance.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 23, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: WeiBing Shang, KanYu Cao
  • Patent number: 11417671
    Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a semiconductor material, a pillar extending through the semiconductor material, a select gate located along a first portion of the pillar, memory cells located along a second portion of the pillar, and transistors coupled to the select gate through a portion of the semiconductor material. The transistors include sources and drains formed from portions of the semiconductor material. The transistors include gates that are electrically uncoupled to each other.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 11410717
    Abstract: The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes first sensing circuitry coupled to the first subset, the first sensing circuitry including a sense amplifier and a compute component configured to perform an in-memory operation. The memory device includes second sensing circuitry coupled to the second subset, the second sensing circuitry including a sense amplifier. The memory device also includes a controller configured to direct a first movement of a data value to a selected subarray in the first subset based on the first sensing circuitry including the compute component.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Perry V. Lea, Richard C. Murphy
  • Patent number: 11410718
    Abstract: A memory device includes a common gate input buffer circuit. The input buffer circuit includes an input node configured to receive a signal representative of data to be stored in the memory device and a voltage reference node. The input buffer circuit further includes an amplification circuit electrically coupled to the input node and to the voltage reference node and configured to amplify the signal to provide for an amplified signal. The input buffer circuit additionally includes an equalization circuit electrically coupled to the amplification circuit and configured to process the amplified signal to provide for a filtered signal and an output circuit electrically coupled to equalization circuit and configured to provide for at least one output signal based on the filtered signal, wherein the output signal comprises a differential output signal and wherein the common gate input buffer circuit does not include a common mode feedback (CMFB) loop.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Shin Deok Kang
  • Patent number: 11398272
    Abstract: Along with the miniaturization of the semiconductor memory device, the resistor and parasitic capacitance of the wires become large, which prevents the semiconductor memory device from being speeded up. In a semiconductor memory device having a semiconductor substrate having a main surface, a first memory cell row having a plurality of first memory cells arranged in parallel to a first direction in plan view on the main surface, a first word line connected to the plurality of first memory cells, a first word line driver for changing a potential of the first word line, and a control circuit for outputting a first predecode signal to the first word line driver via the first predecode line in response to a clock signal and an address signal, a repeater is inserted between the control circuit and the first word line driver.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: July 26, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Makoto Yabuuchi
  • Patent number: 11393515
    Abstract: An apparatus is provided which comprises: a stack comprising a magnetic insulating material (MI such as EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene), wherein the magnetic insulating material has a first magnetization; a magnet with a second magnetization, wherein the magnet is adjacent to the TMD of the stack; and an interconnect comprising a spin orbit material, wherein the interconnect is adjacent to the magnet.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Chia-Ching Lin, Sasikanth Manipatruni, Tanay Gosavi, Dmitri Nikonov, Benjamin Buford, Kaan Oguz, John J. Plombon, Ian A. Young
  • Patent number: 11392322
    Abstract: A memory system may include a memory device comprising a memory device including a plurality of nonvolatile memories, each nonvolatile memory including a plurality of blocks; and a controller configured to: perform a background read operation on a select nonvolatile memory among the plurality of nonvolatile memories using an initial read voltage; store the initial read voltage, as a history read voltage, in a history table; select the history read voltage from the history table in response to a read request from a host; and perform an initial read operation on the select nonvolatile memory using the history read voltage.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: July 19, 2022
    Assignee: SK hynix Inc.
    Inventor: Yu Mi Kim
  • Patent number: 11392326
    Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory cell array including multiple planes, a peripheral circuit configured to perform an operation on the multiple planes, a control memory configured to store control codes for controlling the peripheral circuit, and a plurality of independent control logic configured to, when a command corresponding to each of the planes is received from a memory controller, control the peripheral circuit with reference to a control code corresponding to the command in response to the command. The control memory includes a common memory configured to be accessible in common by the plurality of independent control logic, and a temporary storage including areas respectively corresponding to the planes.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: July 19, 2022
    Assignee: SK hynix Inc.
    Inventor: Kyu Tae Park
  • Patent number: 11380394
    Abstract: An integrated circuit memory device having: a memory cell; a current sensor connected to the memory cell; a voltage driver connected to the memory cell; and a bleed circuit connected to the voltage driver. During an operation to read the memory cell, the voltage driver drives a voltage applied on the memory cell. The bleed circuit is activated to reduce the voltage during a time period in which the current sensor operates to determine whether or not at least a predetermined level of current is presented in the memory cell.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Mingdong Cui, Hongmei Wang, Michel Ibrahim Ishac
  • Patent number: 11380407
    Abstract: According to one or more embodiments, a memory system includes a nonvolatile semiconductor memory, a capacitor, a constant current circuit, a measurement circuit, and a controller. The capacitor stores charges to be supplied to the nonvolatile semiconductor memory. The constant current circuit extracts the charge from the capacitor at a constant current. The measurement circuit measures a terminal voltage of the capacitor. The controller controls the nonvolatile semiconductor memory. The controller calculates a capacitance value of the capacitor based both on a resistance value of a leakage resistance of the capacitor and a change in the measured terminal voltage over time in each of a first period during which the capacitor naturally discharges and a second period during which the constant current circuit extracts the charge from the capacitor.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: July 5, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Hiroki Yamasaki