Patents Examined by Min Huang
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Patent number: 11862236Abstract: In a memory component programmed to operate in a first operating mode and having a page buffer and a fixed-width data interface, N bits of a command/address value are decoded to access one of 2N columns of data within the page-buffer, with that column of data output via the fixed-width data interface over a first burst interval. If programmed to operate in a second operating mode, M bits of the command/address value are decoded to access a larger column of data—one of 2M columns of data within the page buffer, where M<N—with that larger column of data output via the fixed-width data interface over a second burst interval longer than the first burst interval.Type: GrantFiled: January 31, 2022Date of Patent: January 2, 2024Assignee: Rambus Inc.Inventors: Frederick A. Ware, John Eric Linstadt, Kenneth L. Wright
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Patent number: 11862233Abstract: The present application relates to the field of semiconductors, in particular, to the field of Dynamic Random Access Memories (DRAMs), and provides a method and system for detecting a mismatch of a sense amplifier. The method creates a sense amplifier by delaying switch-on of a positive channel-metal-oxide-semiconductor (PMOS) transistor or a negative channel-metal-oxide-semiconductor (NMOS) transistor in the sense amplifier and shortening a row precharge command period (tRP).Type: GrantFiled: May 19, 2022Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Dong Liu, Tianhao Diwu, Xikun Chu
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Patent number: 11862265Abstract: A method of tuning a resonant frequency of a nano-electromechanical systems (NEMS) drum device is performed by applying a gate voltage between the drum membrane [100] and a back gate [104] to alter the resonant frequency of the membrane to a desired frequency; photoionizing the drum membrane with a laser to detune the membrane resonant frequency to a ground state frequency; and releasing the gate voltage to set the membrane to the desired resonant frequency. The method provides the basis for various applications including NEMS memory and photodetection techniques. The NEMS device may be implemented as a graphene/hBN membrane [100] suspended on a SiO2 layer [102] deposited on a Si substrate [104].Type: GrantFiled: May 27, 2020Date of Patent: January 2, 2024Assignee: University of OregonInventors: Benjamín J. Alemán, David J. Miller
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Patent number: 11853880Abstract: One aspect of this description relates to a convolutional neural network (CNN). The CNN includes a memory cell array including a plurality of memory cells. Each memory cell includes at least one first capacitive element of a plurality of first capacitive elements. Each memory cell is configured to multiply a weight bit and an input bit to generate a product. The at least one first capacitive element is enabled when the product satisfies a predetermined threshold. The CNN includes a reference cell array including a plurality of second capacitive elements. The CNN includes a memory controller configured to compare a first signal associated with the plurality of first capacitive elements with a second signal associated with at least one second capacitive element of the plurality of second capacitive elements, and, based on the comparison, determine whether the at least one first capacitive element is enabled.Type: GrantFiled: August 25, 2020Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Jaw-Juinn Horng, Szu-Chun Tsao
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Patent number: 11854644Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a parameter value of a select gate associated with a first set of memory cells; responsive to determining that the parameter value satisfies a threshold criterion, marking the first block in a grown bad block (GBB) data structure; performing one or more pulse operations on the first block to invalidate data stored on the block; receiving, from a host system, an enhanced erase command referencing a second block; and responsive to determining that the second block is marked in the GBB data structure, discarding the enhanced erase command.Type: GrantFiled: December 14, 2021Date of Patent: December 26, 2023Assignee: Micron Technology, Inc.Inventors: Zhongguang Xu, Zhenlei Shen, Murong Lang
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Patent number: 11854607Abstract: Embodiments of the present application provide a memory structure and a memory layout. The memory structure includes: memory arrays, each including a plurality of memory cells; read-write conversion circuits, each disposed between two adjacent ones of the memory arrays in a first direction, being arranged in a second direction, having a symmetry axis in the second direction, and configured to write external data into the memory cells, or read data from the memory cells, and the first direction being perpendicular to the second direction; sense amplification circuits, symmetrically disposed between two adjacent ones of the memory arrays based on the symmetry axis, coupled to the memory cells in the adjacent ones of the memory arrays; and bias contact point structures, disposed in gaps between the read-write conversion circuits, and configured to set a bias voltage of a well region where the bias contact point structures are located.Type: GrantFiled: April 29, 2022Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Yang Zhao, Jaeyong Cha
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Patent number: 11848052Abstract: The present disclosure discloses a ternary content addressable memory based on a memory diode, which includes a plurality of kernel units having functions of storing data, erasing/writing data, and comparing data; the kernel units are arranged in an array, all kernel units in a unit of row are connected to a same matching line, and all kernel units in a unit of column are connected to a same pair of complementary search signal lines; the kernel unit includes two memory diodes; top electrodes of a first memory diode and a second memory diode are respectively connected to a pair of complementary search signal lines, and bottom electrodes of the first memory diode and the second memory diode are connected to a same matching line.Type: GrantFiled: March 25, 2022Date of Patent: December 19, 2023Assignee: ZHEJIANG UNIVERSITYInventors: Yi Zhao, Bing Chen
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Patent number: 11842784Abstract: A semiconductor device includes a test command generation circuit that generates a test write command and a test read command when entering a test mode, and an input/output control circuit that controls a memory block, the memory block including a plurality of banks such that write operations are simultaneously performed on the plurality of banks based on the test write command and read operations are simultaneously performed on the plurality of banks based on the test read command.Type: GrantFiled: December 10, 2021Date of Patent: December 12, 2023Assignee: SK hynix Inc.Inventors: Seung Woo Lee, Dong Hee Han
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Patent number: 11837278Abstract: Disclosed are a dynamic random access memory (DRAM) device, an on-die termination (ODT) resistance value setting method thereof, and a computer program therefor, and the DRAM device includes at least one DRAM module and a memory controller configured to measure a resistance value of an ODT resistor corresponding to one of a rank included in the DRAM module, a chipset included in the rank, and a DQ included in the chipset and set a resistance value of an ODT resistor corresponding to one of the rank, the chipset, and the DQ on the basis of the measured resistance value.Type: GrantFiled: February 23, 2022Date of Patent: December 5, 2023Inventors: Sang-Seok Kang, Young-Hee Jung, Sun-Young Lee
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Patent number: 11837276Abstract: Apparatuses and methods for 1T and 2T memory cell architectures. A memory array includes a word line which has both 1T and 2T portions. In the 1T portion, each sense amplifier is coupled to one memory cell along the word line. In the 2T portion, sense amplifiers are coupled to more than one memory cell along the word line each. For example, each sense amplifier in the 2T portion may be coupled to two bit lines, each of which intersect a memory cell along the word line. In some embodiments, the 2T portion may store a count value which represents an access count to the word line.Type: GrantFiled: December 14, 2021Date of Patent: December 5, 2023Assignee: Micron Technology, Inc.Inventors: Hiroki Takahashi, Toru Ishikawa
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Patent number: 11837274Abstract: A method and apparatus for improving a system DRAM reliability, and a non-transitory computer-readable storage medium. The method comprises: obtaining an apparent voltage of a DRAM, and performing a reliability check on a voltage value of the apparent voltage (S100); according to a verification result of the reliability check, calculating a voltage deviation value of a power supply voltage under an ideal DRAM model (S200); and according to the voltage deviation value, adjusting the power supply voltage of the DRAM (S300).Type: GrantFiled: May 19, 2020Date of Patent: December 5, 2023Assignee: ZTE CORPORATIONInventors: Fengpeng Liu, Dongmei Liu
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Patent number: 11830563Abstract: The present disclosure includes methods and apparatuses comprising a memory component having an independent structure and including an array of memory cells with associated decoding and sensing circuitry of a read interface, a host device coupled to the memory component through a communication channel, a JTAG interface in the array of memory cells, and an additional register in the JTAG interface. The additional register is configured to store a page address associated with the array of memory cells, the memory component is configured to load the page address at the power-on of the apparatus, and the host device is configured to perform a read sequence at the page address.Type: GrantFiled: May 2, 2022Date of Patent: November 28, 2023Assignee: Micron Technology, Inc.Inventors: Antonino Mondello, Alberto Troia
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Patent number: 11823743Abstract: A variety of applications can include a memory device designed to perform sensing of a memory cell of a string of memory cells using a modified shielded bit line sensing operation. The modified shielded bit line sensing operation includes pre-charging a data line corresponding to the string with the string enabled to couple to the data line. The modified shielded bit line sensing operation can be implemented in a hybrid initialization routine for the memory device. The hybrid initialization routine can include a sensing read routine corresponding to an all data line configuration of data lines of the memory device and a modified sensing read routine corresponding to a shielded data line configuration of the data lines with selected strings enabled during pre-charging. A read retry routine associated with the modified sensing read routine can be added to the hybrid initialization routine. Additional devices, systems, and methods are discussed.Type: GrantFiled: May 18, 2022Date of Patent: November 21, 2023Assignee: Micron Technology, Inc.Inventors: Shannon Marissa Hansen, Fulvio Rori, Andrea D'Alessandro, Jason Lee Nevill, Chiara Cerafogli
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Patent number: 11823735Abstract: A semiconductor device includes a main circuit and a peripheral circuit inputting/outputting a signal from/to the main circuit, the main circuit including: a memory cell array; a sense amplifier; a first output holding circuit holding the read data output from the sense amplifier; a second output holding circuit receiving the read data as its input output from the first output holding circuit; and a delay circuit outputting a delay signal for activating the second output holding circuit to be later than the first output holding circuit. The delay circuit includes an element applying a load capacitance to a wiring of the delay signal. A power-supply voltage being a first voltage is supplied to the memory cell array, the sense amplifier and the first output holding circuit. A power-supply voltage being a second voltage is supplied to the delay circuit, the second output holding circuit and the peripheral circuit.Type: GrantFiled: November 5, 2021Date of Patent: November 21, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yohei Sawada
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Patent number: 11817162Abstract: Disclosed are hardware configurations of the Register Aliasing Table (RAT) which are suitable for use in structures such as modern microprocessor, microcontroller, CPU etc. that use pipe line technique, perform multi-command operations, prevents Write After Read (WAR), Write After Write (WAW), Read After Write (RAW) dependencies. The Register Aliasing Table provides a circuit which consumes less energy, uses less space and has low latency compared to the applications in the state of the art.Type: GrantFiled: August 5, 2020Date of Patent: November 14, 2023Inventors: Oguz Ergin, Ilker Polat
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Patent number: 11817142Abstract: Embodiments of the present application provide a refresh circuit and a memory. The refresh circuit includes: a refresh control module configured to receive and execute a refresh command to output a row address refresh signal; and further configured to receive a process corner signal to adjust an execution proportion of the refresh command, the faster a process corner represented by the process corner signal, the higher the adjusted execution proportion; a row addresser configured to receive the row address refresh signal and output a to-be-refreshed single-row address; and an array refresh device configured to perform a single-row refresh operation according to the single-row address and output a single-row refresh end signal after the end of single-row refresh. The embodiments of the present application help reduce the consumption of refresh currents.Type: GrantFiled: September 21, 2021Date of Patent: November 14, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Yinchuan Gu, Geyan Liu
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Patent number: 11804262Abstract: A machine memory includes multiple memory cells. Word lines, each with at least one word line driver, are coupled to the memory cells along rows. The word line drivers of at least some adjacent pairs of the word lines are coupled together by a pull-down transistor, in a manner that reduces read disturb of the memory cells.Type: GrantFiled: June 17, 2021Date of Patent: October 31, 2023Assignee: NVIDIA CORP.Inventors: Lalit Gupta, Andreas Jon Gotterba, Jesse Wang, Stefan P Sywyk
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Patent number: 11804256Abstract: According to one embodiment, a memory system is disclosed. The system includes a nonvolatile memory, a controller which controls the nonvolatile memory and to which a first voltage is supplied, and a circuit to which first and second signals from a host device are input, or the first signal is not input and the second signal is input from the host device, when the memory system is connected to the host device. The circuit converts a second voltage of the second signal into the first voltage when the first and second signal have the second voltage and the second voltage is lower than the first voltage, and does not convert a voltage of the second signal into the first voltage when the first signal is not input and the voltage of the second signal is the first voltage.Type: GrantFiled: July 22, 2022Date of Patent: October 31, 2023Assignee: Kioxia CorporationInventor: Hajime Matsumoto
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Patent number: 11804258Abstract: A semiconductor memory apparatus includes a first memory cell array, a second memory cell array, and a hammering control circuit. The first memory cell array includes a first row hammer memory cell. The second memory cell array includes a second row hammer memory cell. The hammering control circuit controls the number of active operations on a first word line to be stored in the second row hammer memory cell and controls the number of active operations on a second word line to be stored in the first row hammer memory cell.Type: GrantFiled: December 10, 2021Date of Patent: October 31, 2023Assignee: SK hynix Inc.Inventor: Yo Sep Lee
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Patent number: 11798649Abstract: Disclosed are a defect repair circuit and a defect repair method. The defect repair circuit includes: a test module, configured to perform defect test on a memory cell array in a test module to determine a defective memory cell, and output test address information and defect flag signal corresponding to the memory cell; a defect information storage module, connected with the test module, configured to store defect address information responsive to the defect flag signal, the defect address information being the test address information of the defective memory cell, and further configured to output first address information responsive to an externally input repair selection signal, the first address information being one of multiple pieces of defect address information; and a repair module, connected with the defect information storage module and configured to repair a corresponding defective memory cell according to the received first address information.Type: GrantFiled: September 7, 2021Date of Patent: October 24, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Liang Zhang