Patents Examined by Min Huang
  • Memory sub-system self-testing operations
    Patent number: 10984881
    Abstract: A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Nathan A. Eckel, Keith A. Benjamin
  • Adaptive application of voltage pulses to stabilize memory cell voltage levels
    Patent number: 10971228
    Abstract: A request to apply a plurality of voltage pulses to memory cells of a memory device can be received. A number of the voltage pulses can be applied the memory cells of the memory device, where a voltage pulse of the number of the voltage pulses places the memory cells of the memory device at a voltage level associated with a defined voltage state. A set of bit error rates associated with the memory cells of the memory device at the voltage level can be determined. Responsive to determining that the set of bit error rates does not satisfy a threshold condition, an additional number of the voltage pulses to the memory cells of the memory device can be applied.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: April 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Murong Lang, Tingjun Xie, Zhenming Zhou
  • Refresh testing circuit and method
    Patent number: 10957376
    Abstract: A refresh testing circuit and method are provided. The refresh testing circuit includes an internal clock generator, a counter, and an address detection circuit. The internal clock generator transmits a control clock signal to a refresh controller to generate a bank selection signal and a row address signal for a refresh operation. The counter counts variations of the bank selection signal to generate a count value. The address detection circuit detects whether a value of the row address signal is sequentially increased during the refresh operations to generate a detection signal.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: March 23, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Kan-Yuan Cheng
  • Interconnect system
    Patent number: 10957418
    Abstract: A variety of applications can include a system having a system platform to which a memory system can be attached for operation of the system. With the memory system removed from the system platform or before being attached to the system platform, an interposer can be connected at the location for the memory system on the system platform to facilitate testing of the system with respect to the memory system. The interposer can include a set of electrical connectors embedded on a first side of the interposer to connect to the system platform and a connector embedded on a second side of the interposer opposite the first side, where the connector allows coupling to an external platform to convey signals between the system platform and the external platform. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Andrea Vigilante
  • Reconfigurable memory architectures
    Patent number: 10936221
    Abstract: Techniques are described herein for a reconfigurable memory device that is configurable based on the type of interposer used to couple the memory device with a host device. The reconfigurable memory device may include a plurality components for a plurality of configurations. Various components of the reconfigurable memory die may be activated/deactivated based on what type of interposer is used in the memory device. For example, if a first type of interposer is used (e.g., a high-density interposer), the data channel may be eight data pins wide. In contrast, if second type of interposer is used (e.g., an organic-based interposer), the data channel may be four data pins wide. As such, a reconfigurable memory device may include data pins and related drivers that are inactive in some configurations.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, James Brian Johnson
  • Voltage profile for reduction of read disturb in memory cells
    Patent number: 10930345
    Abstract: An integrated circuit memory device having: a memory cell; a current sensor connected to the memory cell; a voltage driver connected to the memory cell; and a bleed circuit connected to the voltage driver. During an operation to read the memory cell, the voltage driver drives a voltage applied on the memory cell. The bleed circuit is activated to reduce the voltage during a time period in which the current sensor operates to determine whether or not at least a predetermined level of current is presented in the memory cell.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Mingdong Cui, Hongmei Wang, Michel Ibrahim Ishac
  • Peak current management in a memory array
    Patent number: 10923199
    Abstract: An electronic device comprises a multi-chip package including multiple memory dice that include a memory array, charging circuitry, polling circuitry and a control unit. The charging circuitry is configured to perform one or more memory events in a high current mode using a high current level or in a low current mode using a lower current level. The polling circuitry is configured to poll a power status node common to the multiple memory dice to determine availability of the high current mode. The control unit is configured to operate the charging circuitry in the high current mode to perform the one or more memory events when the polling circuitry indicates that the high current mode is available, and operate the charging circuitry in the low current mode to perform the one or more memory events when the polling circuitry indicates that the high current mode is unavailable.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michele Piccardi, Xiaojiang Guo, Kalyan Kavalipurapu
  • Nonvolatile semiconductor memory device
    Patent number: 10910059
    Abstract: According to the present embodiment, a nonvolatile semiconductor memory device includes a memory string group including k stacked memory strings, each of the memory strings including a plurality of nonvolatile memory cells connected in series, a selection transistor group including k selection transistors, each of the k selection transistors corresponding to each of the k memory strings respectively, the selection transistor group divided into n selection transistor sub-groups, each of the n selection transistor sub-groups including k/n selection transistors, n bit lines arranged in parallel to each of the k memory strings, and n bit line contacts arranged perpendicularly, each of the n bit line contacts connected to each of the n bit lines, respectively, each of the n bit line contacts connected to the k/n selection transistors belonging to the each of the n selection transistor sub-group respectively.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: February 2, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Hidehiro Shiga
  • Method of exchanging data with memory cells
    Patent number: 10910053
    Abstract: A method of switching a cell of a memory that consists of cell components formed in a three-dimensional crystal with their own electrical connections and logical cell switching circuits, said method involving the exchange of data with the cells, wherein said exchange is carried out simultaneously with the aid of logical switching circuits and a focused stream of charged particles or electromagnetic radiation, which is directed at one or several of the faces of the crystal onto which a portion of mutually perpendicular electrical connection lines exit. The method simplifies cell switching and does not necessitate switching circuits on all of the faces of a three-dimensional crystal.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: February 2, 2021
    Inventors: Vjacheslav Alekseevich Kosuhin, Vladimir Grigor'evich Dmitrienko
  • Determination of a match between data values stored by several arrays
    Patent number: 10908876
    Abstract: Apparatuses, systems, and methods related to determination of a match between data values stored by several arrays are described. A system using the data values may manage performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on whether the data values match. For instance, one apparatus described herein includes a plurality of arrays of memory cells formed on a single memory chip. The apparatus further includes comparator circuitry configured to compare data values stored by two arrays selected from the plurality to determine whether there is a match between the data values stored by the two arrays. The apparatus further includes an output component configured to output data values of one of the two arrays responsive to determination of the match between the data values stored by the two arrays.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: February 2, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Aaron P. Boehm
  • Accurate self-calibrated negative to positive voltage conversion circuit and method
    Patent number: 10910072
    Abstract: Apparatuses and techniques are described for calibrating a negative voltage source. A ground voltage is applied to a multi-stage amplifier from the negative voltage source while an offset voltage measurement (OVM) is made at the output of the multi-stage amplifier. The OVM is recorded and subsequently used by a calibration circuit when the negative voltage source applies a range of negative voltages to the input of the multiple stage amplifier. The calibration circuit subtracts the OVM from measurements obtained at the output of the multi-stage amplifier to obtain corrected measurements, and uses the corrected measurements to calibrate the negative voltage source, e.g., by adjusting a relationship between digital values input to the negative voltage source and the output voltages.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: February 2, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Xiaofeng Zhang, Steve Choi, Gyusung Park
  • Method and device for evaluating the quality of a component produced by means of an additive laser sintering and/or laser melting method
    Patent number: 10900890
    Abstract: A method for evaluating the quality of a component produced by means of an additive laser sintering and/or laser melting method, in particular a component for an aircraft engine, includes at least the steps of providing a first data set, which comprises spatially resolved color values, which each characterize the temperature of the component at an associated component location during the laser sintering and/or laser melting of the component, providing a second data set, which comprises spatially resolved color values corresponding to the first data set, which color values each characterize the temperature of a reference component at an associated reference component location during the laser sintering and/or laser melting of the reference component.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: January 26, 2021
    Assignee: MTU Aero Engines AG
    Inventors: Thomas Hess, Gunter Zenzinger, Wilhelm Satzger
  • Semiconductor memory device and method of controlling the same
    Patent number: 10896733
    Abstract: A semiconductor memory device comprises: a memory transistor; a first wiring connected to a gate electrode of the memory transistor; and a control device that executes a read operation to read data of the memory transistor and a write operation to write data in the memory transistor. In the read operation or the write operation, the control device: increases a voltage of the first wiring to a first voltage from a first timing to a second timing; and adjusts a length from the first timing to the second timing corresponding to at least one of a voltage of the first wiring, a current of the first wiring, and an amount of charge flowed through the first wiring.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: January 19, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Keita Kimura, Hidehiro Shiga
  • Memory device operating based on a write current for a given operation condition and a method of driving the write current
    Patent number: 10891998
    Abstract: A memory device including: a memory cell array including a memory cell, the memory cell configured to store first data based on a first write current; a write driver configured to output the first write current based on a control value; and a current controller including a replica memory cell, the current controller configured to generate the control value based on a state of second data which is stored in the replica memory cell, wherein an intensity of the first write current is adjusted based on the control value.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: January 12, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chankyung Kim, Taehyun Kim, Seongui Seo, Sangjung Jeon
  • Method and circuit for protecting a DRAM memory device from the row hammer effect
    Patent number: 10885966
    Abstract: A method of protecting a DRAM memory device from the row hammer effect includes the memory device comprising a plurality of banks composed of memory rows, the method being implemented by at least one logic prevention device configured to respectively associate contiguous sections of rows of a bank with sub-banks and to execute, on each activation of a row of a sub-bank (b) of the memory, an increment step of a required number of preventive refreshments (REFRESH_ACC; REFRESH_ACC/PARAM_D) of the sub-bank (b) using an activation threshold (PARAM_D) of the sub-bank (b). The prevention logic is also configured to execute a preventive refresh sequence of the sub-banks according to their required number of preventive refreshes. A DRAM memory device, a buffer circuit or a controller of such a memory may comprise the logic for preventing the row hammer effect.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: January 5, 2021
    Assignee: UPMEM
    Inventors: Fabrice Devaux, Renaud Ayrignac
  • Apparatuses and methods for in-memory operations
    Patent number: 10878885
    Abstract: The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes first sensing circuitry coupled to the first subset, the first sensing circuitry including a sense amplifier and a compute component configured to perform an in-memory operation. The memory device includes second sensing circuitry coupled to the second subset, the second sensing circuitry including a sense amplifier. The memory device also includes a controller configured to direct a first movement of a data value to a selected subarray in the first subset based on the first sensing circuitry including the compute component.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Perry V. Lea, Richard C. Murphy
  • SRAM-based authentication circuit
    Patent number: 10880103
    Abstract: A memory device includes a memory block that includes a plurality of memory bits, wherein each bit is configured to present a first logical state; and an authentication circuit, coupled to the plurality of memory bits, wherein the authentication circuit is configured to access a first bit under either a reduced read margin or a reduced write margin condition to determine a stability of the first bit by detecting whether the first logical state flips to a second logical state, and based on the determined stability of at least the first bit, to generate a physically unclonable function (PUF) signature.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Chen Lin, Shih-Lien Linus Lu, Wei Min Chan
  • Integrated circuit and memory
    Patent number: 10872657
    Abstract: An integrated circuit may include an amplifier circuit configured to receive a pull-up voltage in response to a pull-up enable signal, receive a pull-down voltage in response to a pull-down enable signal, and amplify a voltage difference between a first line and a second line through the pull-up and pull-down voltages; a first delay path configured to generate the pull-up enable signal by delaying an input signal; and a second delay path configured to generate the pull-down enable signal by delaying the input signal, wherein a change in a delay of the first delay path due to variation of a power supply voltage is smaller than a change in a delay of the second delay path due to the variation.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: December 22, 2020
    Assignee: SK hynix Inc.
    Inventor: Jeong-Jik Na
  • Memory modules, memory systems, and methods of operating memory modules
    Patent number: 10872653
    Abstract: A memory module includes semiconductor memory devices mounted on a circuit board and a control device mounted on the circuit board. The control device receives a command, an address, and a clock signal from an external device, and provides the command, the address, and the clock signal to the semiconductor memory devices. The control device, in a hidden training mode during a normal operation, performs a command/address training on at least one semiconductor memory device of the semiconductor memory devices by transmitting a first command/address and a first clock signal to the at least one semiconductor memory device and receiving a second command/address and a second clock signal in response to the first command/address and the first clock signal, from the at least one semiconductor memory device.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 22, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Hoon Kim, Young Yun, Wang-Soo Kim, Yoo-Jeong Kwon, Si-Hoon Ryu, Young-Ho Lee, Sung-Joo Park
  • Comparing input data to stored data
    Patent number: 10867670
    Abstract: In an example, a method may include comparing input data to stored data stored in a memory cell and determining whether the input data matches the stored data based on whether the memory cell snaps back in response to an applied voltage differential across the memory cell.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: December 15, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Hernan A. Castro