Abstract: A load monitoring system for a facility includes a computer system configured to execute a model of the object, the model configured to estimate a state of the object as a function of measured values of at least one characteristic of the object, receive at least one measured value of the at least one characteristic of the object, and execute, by the computer system, the model to compute an estimated state of the object.

Abstract: A read control method of a memory controller for controlling a memory device including a plurality of memory pages respectively connected to a plurality of word lines includes identifying a selected memory page connected to a selected word line among the plurality of memory pages has undergone a suspend operation, determining a read offset level of the selected memory page based on suspend operation information associated with the selected memory page according to a result of the identifying the selected memory page, and controlling a read operation of the memory device based on a read voltage associated with the read offset level that was determined.

Abstract: Techniques for training a command/address (C/A) bus, including training internal command/address (C/A) signal lines of a memory module are described. In one example, a method of training a C/A bus involves a memory controller transmitting a first command to a DRAM with parity checking enabled, the first command to include valid parity and chip select asserted. The memory controller transmits commands in cycles before and after the first command to at least one DRAM with parity checking disabled, the commands to include invalid parity and chip select asserted. In response to detecting a parity error, the memory controller modifies a timing parameter to adjust timing for the internal C/A signal lines of the memory module.

Abstract: An apparatus including a memory subsystem. The memory subsystem includes a data input and a clock input. The apparatus also includes a variable delay circuit coupled to one of the data input or the clock input. Additionally, the apparatus includes a controller coupled to the variable delay circuit. The controller is configured to dynamically control the delay of the variable delay circuit. The controller may adjust the delay of the variable delay circuit based on at least one of timing data for a memory subsystem design of the memory subsystem, timing data for the memory subsystem, a voltage applied to the memory subsystem, or a temperature of the memory subsystem.

Abstract: A method populates a parameter set for dynamically adjusting an operating condition in a memory block of a non-volatile memory circuit. A desired condition limit is identified, and a first parameter is computed as a function of a first memory operation to be performed on the memory block. The first parameter is included in a parameter set, and the memory block is cycled until the operating condition reaches the desired condition limit. After cycling, a second parameter is determined as a function of a second memory operation to be performed on the memory block, and the second parameter is included in the parameter set. The steps of cycling, and determining and the including the second parameter may be repeated until a desired number of cycles/parameters are reached. A retention bake may also be performed on the memory circuit, and a bit error rate resulting from a read operation verified.

Abstract: A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.

Abstract: This invention uses a novel mechanism to store a matrix of numbers or any two dimensional array of binary values in a novel storage entity called a Matrix Space. A matrix space which may reside in a processing unit, is designed to store a plurality of matrices or arrays of values into arrays of volatile or non-volatile memory cells or latch or flip-flop elements much like in a memory, but with accessibility in two or three dimensions. In this invention any row and/or any column of storage elements in a storage array is directly accessible for writing, reading or clearing via row bit lines and column bit lines, respectively. The elements in rows of arrays are selected or controlled for access using row address lines and the elements in columns of arrays are selected or controlled for access using column address lines. This allows access to data stored in matrix space arrays for use in matrix and array computations, by both rows and columns of the arrays.

Abstract: In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.

Abstract: Systems and methods for cache invalidation, with support for different modes of cache invalidation include receiving a matchline signal, wherein the matchline signal indicates whether there is a match between a search word and an entry of a tag array of the cache. The matchline signal is latched in a latch controlled by a function of a single bit mismatch clock, wherein a rising edge of the single bit mismatch clock is based on delay for determining a single bit mismatch between the search word and the entry of the tag array. An invalidate signal for invalidating a cacheline corresponding to the entry of the tag array is generated at an output of the latch. Circuit complexity is reduced by gating a search word with a search-invalidate signal, such that the gated search word corresponds to the search word for a search-invalidate and to zero for a Flash-invalidate.

Abstract: A circuit, where a first end of a resistive random access memory (RRAM) included in the circuit includes a first end of the circuit, and a second end of the RRAM is coupled to a first end of a first switch and a first end of a second switch, a second end of the first switch includes a second end of the circuit, and a first control end of the first switch and a second control end of the second switch are configured to make the first switch closed and the second switch open at the same time. Therefore, a working status of the RRAM is flexibly controlled.

Abstract: Methods and systems to detect power outage are provided herein. The system includes a Cable Modem Termination System (CMTS) to periodically poll cable modems and determine cable modems of the plurality of cable modems that are offline based on the poll. The system correlates and aggregates locations of the cable modems that are offline to determine a geographic area where a percentage of the cable modems that are offline is higher than a predetermined threshold. A report is generated indicating a power outage in the geographic area when the percentage is above the pre-determined threshold.

Abstract: A memory management method is provided. The method includes selecting a target physical programming unit; using a first read voltage corresponding to a first type physical page of the target physical programming unit to read a plurality of target memory cells of the target physical programming unit, so as to calculate a first bit value ratio; if the first bit value ratio is not smaller than a first preset threshold, using a second read voltage corresponding to the first type physical page of the target physical programming unit to read the plurality of target memory cells of the target physical programming unit, so as to calculate a second bit value ratio; and determining whether the first type physical page of the target physical programming unit is empty by comparing the first bit value ratio and the second bit value ratio.

Abstract: Disclosed embodiments include a testing system that electrically connects to an integrated circuit (IC) having ferroelectric memory (FRAM) cells. The testing system programs the FRAM cells to a first data state and then iteratively reads the programmed cells at a plurality of reference voltages to identify a reference voltage limit that indicates a first occurrence at which at least one of the cells fails to return the first data state when read. Iteratively reading the cells includes reading each cell at an initial reference voltage at which all the cells return the first data state, and then reading each of the programmed cells at each of the remaining reference voltages by incrementally changing the initial reference voltage in one direction until the reference voltage limit is identified. The testing system sets the reference in the IC at an operating level based on the reference voltage limit.

Abstract: A PUF code providing apparatus includes a non-volatile memory cell pair and a data sensing circuit. The sensing circuit is coupled to the non-volatile memory cell pair, reads two initial statuses of the non-volatile memory cell pair and generates a PUF code by comparing the two initial statuses of the non-volatile memory cell pair.

Abstract: An energy monitoring and analysis system is provided. Sensors are attached to circuit breakers to collect energy consumption data. The energy consumption data is analyzed to determine events associated with the circuit. An energy monitoring system comprising a paddle having one or more sensors can be affixed to existing circuit breakers and provide communication with the energy analysis system. From the events notifications and alerts can be generated to inform consumers such as a utility, monitoring company or end user.

Abstract: A data storage device can have at least a buffer memory, a selection module, and a non-volatile memory. The buffer memory and non-volatile memory may consist of different types of memory while the non-volatile memory has one or more rewritable in-place memory cells. The buffer memory and non-volatile memory may each store data associated with a pending data request as directed by the selection module until a settle time of the rewritable in-place memory cell has expired.

Abstract: A memory circuit includes a plurality of memory tiles. Each memory tile in the plurality of memory tiles includes a plurality of bit cells and a control circuit coupled to the plurality of bit cells. The control circuit is configured to provide latched data to the plurality of bit cells during write operations. A first write control line is coupled to the control circuit in a first memory tile, and the first write control line is configured to initiate a first write operation in the first memory tile. And a second write control line is coupled to the control circuit in a second memory tile, and the second write control line configured to initiate a second write operation in the second memory tile. The second write operation may be initiated before the first write operation is completed.

Abstract: A memory controller is used to control a first storage block having a first data rate and a second storage block having a second data rate. The memory controller includes; a memory interface that transceives a data signal and a data strobe signal with the first and second storage blocks, and a sub controller that stores access information about the first data rate and the second data rate. The sub controller may include a delay lookup table storing access information including first strobe adjustment timing information defining a first data strobe signal provided to the first storage block, and second strobe adjustment timing information defining a second data strobe signal provided to the second storage block.

Abstract: Techniques for improving the performance of a quantum processor are described. Some techniques employ reducing intrinsic/control errors by using quantum processor-wide problems specifically crafted to reveal errors so that corrections may be applied. Corrections may be applied to physical qubits, logical qubits, and couplers so that problems may be solved using quantum processors with greater accuracy.

Abstract: There are provided a memory controller for controlling a memory device to perform a more stable sensing operation, a storage device including the memory controller, and an operating method of the storage device. A memory controller includes: a processor for transmitting a cache read command to a memory device and then transmitting a status read command to the memory device; and a cache read controller for outputting a data-out command to the memory device according to a sensing section code included in a status read response transmitted by the memory device in response to the status read command.