Abstract: Examples of the present disclosure relate to a device, method, and medium storing instructions for execution by a processor for refreshing memory blocks of solid state memory through a temperature compensated refresh rate. Techniques discussed herein include a solid state memory to store data and a temperature sensor to identify a temperature of the solid state memory. The memory device with solid state memory also includes a memory controller that periodically refreshes memory blocks of the solid state memory at an adjustable refresh rate, wherein memory controller is to adjust the adjustable refresh rate based on the temperature of the solid state memory.

Abstract: A data acquisition method of acquiring and latching data with a timing based on an input signal supplied to an input port, the method including: acquiring and retaining the data with a timing of when an edge of the input signal is detected, and starting a timer; and at the time of expiration of the timer, if the level of the input signal is a first level that is unchanged from start of the timer, latching the retained data and if the level of the input signal is a second level that is changed from the start of the timer, discarding the retained data.

Abstract: Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A capacitor is electrically coupled to the second source/drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region. The non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.

Abstract: Various apparatuses, systems, methods, and media are disclosed to provide over-voltage protection to a data interface of a multi-protocol memory card that includes a first communication interface and a second communication interface that enable communication using different protocols. An interface voltage protection circuit includes a control circuit configured to receive a first supply voltage for operating the first communication interface. The interface voltage protection circuit further includes a pull-down circuit operatively connected with the control circuit, configured to pull down a voltage at a supply voltage rail of the second communication interface such that a voltage at a plurality of connector terminals of the second communication interface is lower than the first supply voltage.

Abstract: Methods, systems, and devices for low power mode for a memory device are described. A memory device may identify a pattern of data configured to be stored in an array of memory cells and determine if the pattern of data satisfies a criterion. The pattern of data may satisfy the criterion if each of the bits of data include a same logic value. If the pattern of data satisfies the criterion, the memory device may disable a driver of an internal bus of the memory device if the data satisfies the criterion, isolate a data line from the internal bus, or couple the data line with a voltage source, or a combination thereof. The memory device may further disable a signal of a clock tree based on identifying that the pattern of data satisfies the criterion.

Abstract: A load monitoring system for a facility includes a computer system configured to execute a model of the object, the model configured to estimate a state of the object as a function of measured values of at least one characteristic of the object, receive at least one measured value of the at least one characteristic of the object, and execute, by the computer system, the model to compute an estimated state of the object.

Abstract: A nonvolatile memory apparatus performs a plurality of read operations by using a plurality of read voltages. A first read operation is performed by applying a first read voltage to a memory cell. A second read operation is selectively performed based on whether a snap-back of the memory cell occurs during the first read operation. The second read operation is performed by applying a second read voltage having a higher voltage level than the first read voltage to the memory cell.

Abstract: According to one embodiment, a memory system includes: a semiconductor memory including a memory cell array, the memory cell array including a memory cell, and a controller configured to issue a first read command sequence after a lapse of a first time period from access to the semiconductor memory, and issue a second read command sequence after a lapse of a second time period from access to the semiconductor memory. When the controller issues the first read command sequence, the semiconductor memory applies a first voltage and a second voltage to the memory cell. When the controller issues the second read command sequence, the semiconductor memory applies a third voltage and a fourth voltage to the memory cell.

Abstract: An electronic apparatus including flash memory and a flash controller is provided. The flash controller is coupled to the flash memory and used to manage data access to the flash memory. The flash controller includes a timer, memory and a microcontroller coupled to the timer and the memory. The timer is used to generate clock interrupts. The memory is used to retain for a predetermined period of time a list of entries of data programmed into the flash memory. Upon each clock interrupt, the microcontroller is used to write an entry of data being programmed into the flash memory to update the list of entries.

Abstract: Embodiments herein provide a Static Random-Access Memory (SRAM) system with a delay tuning circuitry and a delay control circuitry and a method thereof. Delay tuning circuitry in the SRAM system may provide a tuning of reset time in the generation of an internal clock by introducing a delay. The delay is introduced according to a process state of periphery circuitry in the SRAM. A delay control circuitry provides a control over delay in reset time of the internal clock by varying a discharge rate for each of a Dummy Bit Line (DBL) circuitry and Complementary Bit Line Circuitry (CDBL), by connecting a stack of NMOS transistors over discharge NMOS transistors.

Abstract: The disclosure provides a circuit structure for storage and retrieval of data, and related methods. The circuit structure may include drive transistor having a source terminal, a drain terminal, and a gate terminal coupled to a word line. A first resistive memory element coupled between the source terminal of the drive transistor and a first bit line may be in a first memory state. A second resistive memory element coupled between the drain terminal of the drive transistor and a second bit line may be in a second memory state opposite the first memory state. The structure may also include a read transistor having a source terminal coupled to the drain terminal of the drive transistor, a drain terminal coupled to ground, and a gate terminal coupled to a select line.

Abstract: The systems and methods provided herein relate to a command interface/memory device that supports multiple modes of command acquisition. A current command acquisition mode from a set of supported command acquisition modes that each define a corresponding command execution frequency is identified. Based upon the identified mode, clock cycles that will be used to acquire portions of a command address from are identified. The portions of the command address are acquired from the identified clock cycles and a command based upon the acquired portions of the command address is executed.

Abstract: A storage device includes a nonvolatile memory device including a memory block and a memory controller. The memory block includes a first memory region connected with a first word line and a second memory region connected with a second word line. The memory controller sets a read block voltage based on a first read voltage of the first memory region. The memory controller determines a second read voltage of the second memory region based on variation information and the read block voltage.

Abstract: A data structure is generated that identifies a shape of a valley that is located between programming distributions of the memory component. The data structure identifies read level thresholds at the valley associated with a logical page type of the memory component. For each of the read level thresholds the data structure associates a respective error count. A read level threshold is estimated using the data structure. A read operation is performed at the memory component using the read level threshold identified using the data structure.

Abstract: The disclosed technology relates generally to magnetic random access memory, and more particularly to spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM). According to an aspect, a MRAM device comprises a first transistor, a second transistor, and a resistive memory element. The resistive memory element comprises a magnetic tunnel junction (MTJ) pillar arranged between a top electrode and bottom electrode having a first terminal and a second terminal. According to another aspect, a method of using the MRAM device is disclosed.

Abstract: An operating method of a memory device includes: instructing, by a master chip, a first memory chip and a second memory chip to perform a read operation; transferring, by the first memory chip, data stored in the first memory chip to the master chip through a first through-chip channel in response to the read operation instruction, and transferring, by the second memory chip, data stored in the second memory chip to the master chip through a second through-chip channel in response to the read operation instruction; comparing, by the master chip, a phase of the data transferred through the first through-chip channel with a phase of the data transferred through the second through-chip channel; and adjusting a delay value of a data transmission channel of at least one of the first memory chip and the second memory chip based on a result of the comparing.

Abstract: A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.

Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.

Abstract: A serial interface circuit, a semiconductor device, and a serial-parallel conversion method are provided. The disclosure is to generate first to nth timing signals respectively indicating timings that differ by 1 bit cycle of the bit string when receiving a serial signal including the bit string in a serial form and converting the bit string into a parallel form to obtain a parallel bit group. Each bit in the bit string is held at the timings of the first to tth timing signals as the standby bit group, the standby bit group is acquired at the timing of any one of the (t+1)th to nth timing signals as a part of the parallel bit group, and each bit in the bit string is held at the timings of the (t+1)th to nth timing signals and the held bit group is set as another part of the parallel bit group.

Abstract: A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.