Patents Examined by Minh Loan Tran
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Patent number: 9676999Abstract: The present invention relates to an Mn4+-activated complex fluoride phosphor with improved moisture resistance due to modification of the particle surface, and a light emitting element and light emitting device having excellent color rendering properties and stability due to the use of this phosphor. The phosphor of the present invention is characterized in that it is represented by the general formula: A2MF6:Mn4+, wherein element A is an alkali metal element comprising at least K, element M is one or more metal elements chosen from among Si, Ge, Sn, Ti, Zr and Hf, F is fluorine, and Mn is manganese, wherein the phosphor comprises Ca in a concentration range of at least 20 ppm and at most 10,000 ppm or Cl in a concentration range of at least 20 ppm and at most 300 ppm.Type: GrantFiled: February 25, 2015Date of Patent: June 13, 2017Assignee: DENKA COMPANY LIMITEDInventors: Hideyuki Emoto, Shinichi Yanagi, Masayoshi Ichikawa, Kazuhiro Ito
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Patent number: 9679942Abstract: A light emitting device includes: a ceramic substrate; a plurality of LED chips; a printed resistor(s) connected in parallel with the plurality of LED chips; a dam resin made of a resin having a low optical transmittance; a fluorescent-material-containing resin layer; and an anode-side electrode and a cathode-side electrode, (a) which are provided on a primary surface of the ceramic substrate so as to face each other along a first direction on the primary surface and (b) which are disposed below at least one of the dam resin and the fluorescent-material-containing resin layer. With the configuration in which a plurality of LEDs, which are connected in a series-parallel connection, are provided on a substrate, it is possible to provide a light emitting device which can achieve restraining of luminance unevenness and an improvement in luminous efficiency.Type: GrantFiled: June 21, 2016Date of Patent: June 13, 2017Assignee: Sharp Kabushiki KaishaInventors: Shinya Ishizaki, Makoto Agatani, Tomokazu Nada, Toshio Hata
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Patent number: 9680055Abstract: A hetero-substrate, a nitride-based semiconductor light emitting device, and a method of manufacturing the same are provided. The hetero-substrate may include a substrate including a silicon semiconductor, a buffer layer disposed on the substrate, a first semiconductor layer disposed on the buffer layer and including a nitride semiconductor, a second semiconductor layer disposed on the first semiconductor layer and including a first conductive type nitride semiconductor having a first doping concentration, and a stress control structure disposed between the first semiconductor layer and the second semiconductor layer and including at least one stress compensation layer and at least one third semiconductor layer including a first conductive type nitride semiconductor having a second doping concentration that is the same or lower than the first doping concentration.Type: GrantFiled: October 30, 2013Date of Patent: June 13, 2017Assignee: LG ELECTRONICS INC.Inventors: Kiseong Jeon, Hojun Lee, Kyejin Lee
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Patent number: 9680066Abstract: The present invention relates to an Mn4+-activated complex fluoride phosphor with improved moisture resistance due to modification of the particle surface, and a light emitting element and light emitting device having excellent color rendering properties and stability due to the use of this phosphor. The phosphor of the present invention is characterized in that it is represented by the general formula: A2MF6:Mn4+, wherein element A is an alkali metal element comprising at least K, element M is one or more metal elements chosen from among Si, Ge, Sn, Ti, Zr and Hf, F is fluorine, and Mn is manganese, wherein the phosphor comprises a Ca-containing compound on a particle surface.Type: GrantFiled: February 25, 2015Date of Patent: June 13, 2017Assignee: DENKA COMPANY LIMITEDInventors: Hideyuki Emoto, Shinichi Yanagi, Masayoshi Ichikawa, Kazuhiro Ito
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Patent number: 9673257Abstract: A method is provided that includes forming a transistor by forming a first a rail gate disposed in a first direction above a substrate, forming a second rail gate disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a bridge section disposed between the first rail gate and the second rail gate.Type: GrantFiled: June 3, 2016Date of Patent: June 6, 2017Assignee: SanDisk Technologies LLCInventors: Seje Takaki, Manabu Hayashi, Akira Nakada, Ryousuke Itou, Takuro Maede, Kengo Kajiwara, Tetsuya Yamada
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Patent number: 9666708Abstract: Techniques related to III-N transistors having enhanced breakdown voltage, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a hardmask having an opening over a substrate, a source, a drain, and a channel between the source and drain, and a portion of the source or the drain disposed over the opening of the hardmask.Type: GrantFiled: March 26, 2014Date of Patent: May 30, 2017Assignee: Intel CorporationInventors: Han Wui Then, Benjamin Chu-Kung, Sansaptak Dasgupta, Robert S. Chau, Seung Hoon Sung, Ravi Pillarisetty, Marko Radosavljevic
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Patent number: 9666665Abstract: A semiconductor device includes a body zone in a semiconductor mesa, which is formed between neighboring control structures that extend from a first surface into a semiconductor body. A drift zone forms a first pn junction with the body zone. In the semiconductor mesa, the drift zone includes a first drift zone section that includes a constricted section of the semiconductor mesa. A minimum horizontal width of the constricted section parallel to the first surface is smaller than a maximum horizontal width of the body zone. An emitter layer between the drift zone and the second surface parallel to the first surface includes at least one first zone of a conductivity type of the drift zone.Type: GrantFiled: April 9, 2014Date of Patent: May 30, 2017Assignee: Infineon Technologies AGInventors: Johannes Georg Laven, Roman Baburske, Matteo Dainese, Peter Lechner
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Patent number: 9666585Abstract: Semiconductor devices are provided. The semiconductor device includes a bit line contact plug and a storage node contact plug electrically connected to an active region of a substrate. A bit line structure is disposed on the bit line contact plug to extend in a first direction. The bit line structure is disposed in a trench pattern that intrudes into a side of the storage node contact plug. Related methods and systems are also provided.Type: GrantFiled: October 28, 2015Date of Patent: May 30, 2017Assignee: SK HYNIX INC.Inventors: Jin Ki Jung, Myoung Soo Kim
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Patent number: 9660067Abstract: III-N transistors with epitaxial semiconductor heterostructures having steep subthreshold slope are described. In embodiments, a III-N HFET employs a gate stack with balanced and opposing III-N polarization materials. Overall effective polarization of the opposing III-N polarization materials may be modulated by an external field, for example associated with an applied gate electrode voltage. In embodiments, polarization strength differences between the III-N materials within the gate stack are tuned by composition and/or film thickness to achieve a desired transistor threshold voltage (Vt). With polarization strengths within the gate stack balanced and opposing each other, both forward and reverse gate voltage sweeps may generate a steep sub-threshold swing in drain current as charge carriers are transferred to and from the III-N polarization layers and the III-N channel semiconductor.Type: GrantFiled: March 25, 2014Date of Patent: May 23, 2017Assignee: Intel CorporationInventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Robert S. Chau
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Patent number: 9646988Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers and a first step portion, the first step portion having the plurality of electrode layers provided stepwise; a column provided in a region of the stacked body other than a region in the first step portion provided; and a plurality of insulating portions provided in the first step portion. The stacked body includes a metal silicide portion provided between the plurality of insulating portions and the plurality of electrode layers, a plurality of terraces provided on a top surface of each of the plurality of electrode layers of the first step portion, and a plurality of contact portions provided on the plurality of terraces.Type: GrantFiled: September 4, 2015Date of Patent: May 9, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Sadatoshi Murakami, Hiroomi Nakajima
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Patent number: 9647004Abstract: A display is disclosed. The display includes a display panel including pixel units in an image-displaying region. Each of the pixel units includes an AND gate and a pixel electrode electrically connected to an output terminal of the AND gate.Type: GrantFiled: August 3, 2015Date of Patent: May 9, 2017Assignee: E INK HOLDINGS INC.Inventors: Ian French, Chi-Ming Wu, Po-Chun Chuang, Chun-Wei Chang, Kun-Lung Huang, Wu-Liu Tsai, Pei-Lin Huang
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Patent number: 9647139Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.Type: GrantFiled: September 4, 2015Date of Patent: May 9, 2017Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
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Patent number: 9647123Abstract: A semiconductor structure including vertical transistors is provided in which a sigma shaped source/drain extension region is formed between a top faceted surface of a first region of an epitaxial semiconductor channel material and a bottom faceted surface of a second region of the epitaxial semiconductor channel material. The sigma shaped source/drain extension region is formed after formation of a functional gate structure on each side of an epitaxial semiconductor channel material by first removing a sacrificial bottom spacer layer of a bottom spacer material stack, performing a sigma etch on an exposed lower portion of the epitaxial semiconductor channel material to provide the first region of epitaxial semiconductor channel material and the second region of the epitaxial semiconductor channel material, and then epitaxially growing the sigma shaped source/drain extension region from the faceted surfaces of the first and second regions of epitaxial semiconductor channel material.Type: GrantFiled: October 14, 2016Date of Patent: May 9, 2017Assignee: International Business Machines CorporationInventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
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Patent number: 9640523Abstract: A lateral p-n diode in the center of and surrounded by a vertical Silicon-Controlled Rectifier (SCR) forms an Electro-Static-Discharge (ESD) protection structure. The lateral p-n diode has a cross-shaped P+ diode tap with four rectangles of N+ diode regions in each corner of the cross. A P-well under the P+ diode tap is also an anode of a vertical PNPN SCR that has a deep N-well in a P-substrate. The deep N-well surrounds the lateral diode. Triggering MOS transistors are formed just beyond the four ends of the cross shaped P+ diode tap. Each triggering MOS transistor has N+ regions at the edge of the deep N-well and in the P-substrate that act as the cathode terminals. A deep P+ implant region under the N+ region at the edge of the deep N-well decreases a trigger voltage of the vertical SCR.Type: GrantFiled: September 8, 2015Date of Patent: May 2, 2017Assignee: Hong Kong Applied Science and Technology Research Institute Company LimitedInventors: Xiaowu Cai, Beiping Yan, Zhongzi Chen
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Patent number: 9640539Abstract: An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.Type: GrantFiled: December 16, 2015Date of Patent: May 2, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Steven Alan Lytle
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Patent number: 9640783Abstract: A light-emitting device according to an aspect of the present disclosure includes a light transmissive first electrode layer, a light transmissive second electrode layer, an electroluminescent layer between the first electrode layer and the second electrode layer, and a reflective layer located on a side opposite to the electroluminescent layer with respect to the second electrode layer. The reflective layer includes a base material having a refractive index equal to or higher than a refractive index of the electroluminescent layer, and fillers each having a refractive index different from that of the base material.Type: GrantFiled: September 4, 2015Date of Patent: May 2, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Masahito Yamana, Tetsushi Konda, Tatsuya Okuno
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Patent number: 9640490Abstract: Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.Type: GrantFiled: June 8, 2015Date of Patent: May 2, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Chieh Hsieh, Hung-An Teng, Shang-Yun Hou, Shin-Puu Jeng
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Patent number: 9640440Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.Type: GrantFiled: April 4, 2016Date of Patent: May 2, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Koji Maekawa, Tatsuyoshi Mihara
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Patent number: 9640652Abstract: A semiconductor device may include a semiconductor layer having a first conductivity type, a well region of a second conductivity type in the semiconductor layer wherein the first and second conductivity types are different, and a terminal region of the first conductivity type in the well region. An epitaxial semiconductor layer may be on the surface of the semiconductor layer including the well region and the terminal region with the epitaxial semiconductor layer having the first conductivity type across the well and terminal regions. A gate electrode may be on the epitaxial semiconductor layer so that the epitaxial semiconductor layer is between the gate electrode and portions of the well region surrounding the terminal region at the surface of the semiconductor layer.Type: GrantFiled: September 10, 2012Date of Patent: May 2, 2017Assignee: Cree, Inc.Inventors: Brett Adam Hull, Qingchun Zhang
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Patent number: 9633971Abstract: A method of making an assembly can include forming a first conductive element at a first surface of a substrate of a first component, forming conductive nanoparticles at a surface of the conductive element by exposure to an electroless plating bath, juxtaposing the surface of the first conductive element with a corresponding surface of a second conductive element at a major surface of a substrate of a second component, and elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles cause metallurgical joints to form between the juxtaposed first and second conductive elements. The conductive nanoparticles can be disposed between the surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers.Type: GrantFiled: July 10, 2015Date of Patent: April 25, 2017Assignee: Invensas CorporationInventor: Cyprian Emeka Uzoh