Patents Examined by Minh Loan Tran
  • Patent number: 9842878
    Abstract: A semiconductor device has a chip region including a back-side illumination type photoelectric conversion element, a mark-like appearance part, a pad electrode, and a coupling part. The mark-like appearance part includes an insulation film covering the entire side surface of a trench part formed in a semiconductor substrate. The pad electrode is arranged at a position overlapping the mark-like appearance part. The coupling part couples the pad electrode and mark-like appearance part. At least a part of the pad electrode on the other main surface side of the substrate is exposed through an opening reaching the pad electrode from the other main surface side of the substrate. The mark-like appearance part and coupling part are arranged to at least partially surround the outer circumference of the opening in plan view.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: December 12, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Terada, Shinya Hori
  • Patent number: 9825187
    Abstract: A bidirectional Zener diode of the present invention includes a semiconductor substrate of a first conductivity type, a first electrode and a second electrode which are defined on the semiconductor substrate, and a plurality of diffusion regions of a second conductivity type, which are defined at intervals from one another on a surface portion of the semiconductor substrate, to define p-n junctions with the semiconductor substrate, and the plurality of diffusion regions include diode regions which are electrically connected to the first electrode and the second electrode, and pseudo-diode regions which are electrically isolated from the first electrode and the second electrode.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: November 21, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Hiroki Yamamoto
  • Patent number: 9818922
    Abstract: Provided is a light emitting device package. It is a substrate comprising a top and a bottom surfaces being substantially parallel to each other; a light emitting diode chip on the substrate; a frame disposed around the light emitting diode chip and configured to reflect light emitted from the light emitting diode chip, the frame having an opening; a first metal layer disposed on the top surface of the substrate; a second metal layer disposed on the top surface of the substrate; a third metal layer disposed on the bottom surface of the substrate; a through hole connected between the first metal layer and the third metal layer; a material being filled in the opening of the frame; and a lens disposed on the material, wherein the substrate and the frame are separate from each other.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: November 14, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Wan Ho Kim
  • Patent number: 9818886
    Abstract: The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage Vth of 0.3 V to 0.7 V and a leakage current Jr of 1×10?9 A/cm2 to 1×10?4 A/cm2 in a rated voltage VR.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: November 14, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Masatoshi Aketa, Yuta Yokotsuji
  • Patent number: 9815978
    Abstract: A light diffuser includes: a thermoplastic resin base which has a thermal expansion coefficient of at least 4×10?5/K and at most 8×10?5/K; and a light diffusion layer which is disposed on a surface of the thermoplastic resin base and includes an acrylic resin film and an acrylic resin particle, the acrylic resin film including one or more acrylic resins having a glass transition temperature of at least 30° C. and at most 50° C., the acrylic resin particle being included in the acrylic resin film and having an average particle size of at least 1 ?m and at most 15 ?m.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: November 14, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Daigo Yamashina, Shuhei Uchiyama, Satoru Yamauchi
  • Patent number: 9812562
    Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yao-Chung Chang, Po-Chih Chen, Jiun-Lei Jerry Yu, Chun Lin Tsai
  • Patent number: 9806102
    Abstract: A display substrate, a method for fabricating the same, and a display device are disclosed. The display substrate comprises a plurality of pixels; and a plurality of slit patterns, which are arranged between at least two of the plurality of pixels, and comprise a plurality of slits arranged in a rubbing direction. Slit patterns are provided, and each of slit patterns comprises slits in the rubbing direction. Thus, during a rubbing alignment process, the slit patterns can guide a rubbing cloth to move in the rubbing direction. Accordingly, the alignment of the rubbing cloth is prevented from changing in the rubbing process, a good alignment layer is formed, rubbing Mura is avoided, and the lifetime of the rubbing cloth is extended.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: October 31, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Qian Zhang, Tingze Dong, Xiuliang Wang, Xuejiao Huang, Zhao Chen
  • Patent number: 9806240
    Abstract: Various embodiments may relate to a wavelength conversion element including at least one sintered wavelength converting material, wherein a grid is formed by channels within the sintered wavelength converting material, the channels are at least partially surrounded by the sintered wavelength converting material, the channels reach at least partially through the sintered wavelength converting material in a direction perpendicular or oblique to a main extension direction of the wavelength conversion element, and the channels contain a non-converting sintered separator material.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: October 31, 2017
    Assignee: OSRAM OPTO Semiconductors GmbH
    Inventors: Britta Goeoetz, Christopher A. Tarry
  • Patent number: 9797582
    Abstract: The invention relates to a printed circuit board (9) for a lamp (1), having a plurality of circuit paths having a multiplicity of light-emitting diodes (8, 12), wherein the light-emitting diodes in a circuit path are each connected up in series with one another and the circuit paths are connected in parallel with one another, wherein a first number of light-emitting diodes (LD11, LD15, LD21, LD25, LD31 LD35, LD41, LD45, LD51, LD55, LD61, LD65) in a circuit path are fitted on a front of the printed circuit board and a second number of light-emitting diodes (LDi11, LDi31, LDi52) in the same circuit path are fitted on a back of the printed circuit board.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: October 24, 2017
    Assignee: ZUMTOBEL LIGHTING GMBH
    Inventor: Mario Pohs
  • Patent number: 9799724
    Abstract: Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: October 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Min Lee, Jongryul Jun, Eun A Kim, Jung-Bum Lim
  • Patent number: 9799673
    Abstract: Disclosed is a method of manufacturing a semiconductor device, including: forming a stacked structure including first material layers and second material layers alternately stacked on each other; forming a pillar passing through the stacked structure, the pillar including a protruding portion protruding above an uppermost surface of the stacked structure; forming a conductive layer surrounding the protruding portion of the pillar; and forming a conductive pattern in contact with the protruding portion of the pillar by oxidizing a surface of the conductive layer.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: October 24, 2017
    Assignee: SK Hynix Inc.
    Inventor: Wan Cheul Shin
  • Patent number: 9799687
    Abstract: Manufacturing method including forming, over substrate, TFT layer, planarization layer, and display element in this order. Forming of TFT layer involves forming passivation layer to cover TFT layer electrode, such as upper electrode, and to come in contact with planarizing layer. Forming of display element involves forming bottom electrode to come in contact with planarizing layer. TFT layer electrode and bottom electrode are connected by: first forming, in planarizing layer, first contact hole exposing passivation layer at bottom thereof; then forming second contact hole exposing TFT layer electrode at bottom thereof through dry-etching passivation layer exposed at bottom of first contact hole using fluorine-containing gas; then forming liquid repellent film containing fluorine on passivation layer inner surface facing second contact hole; and forming bottom electrode along planarizing layer inner surface and passivation layer inner surface respectively facing first contact hole and second contact hole.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: October 24, 2017
    Assignee: JOLED INC.
    Inventor: Yuuki Abe
  • Patent number: 9786839
    Abstract: Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetoresistive random access memory (MRAM) chip magnetic shielding and vertical stacking capabilities processed at the wafer-level are disclosed. The method includes providing a magnetic shield in the through silicon vias and/or through silicon trenches surrounding or adjacent to magnetic tunnel junction (MTJ) array within the MRAM region and also at the front side and back side of the chip. Magnetic shield in the through silicon trenches connects front side and back side magnetic shield. Magnetic shield in the through silicon vias provides vertical stacking, magnetic shielding and electrical connection of the MRAM chips to form 3D IC packages. This magnetic shielding method is applicable for both in-plane and perpendicular MRAM chips. The MTJ array is formed in the MRAM region and in between adjacent inter layer dielectric (ILD) levels of the upper ILD layer in the back end of line (BEOL) of the MRAM chip.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: October 10, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bharat Bhushan, Juan Boon Tan, Wanbing Yi, Pak-Chum Danny Shum
  • Patent number: 9786762
    Abstract: A semiconductor device includes a semiconductor substrate; a gate insulating film provided on the semiconductor substrate; a gate electrode having a metal layer, a metal oxide layer and a silicon layer containing a dopant, provided sequentially on the gate insulating film; and a transistor having a gate insulating film and a gate electrode.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: October 10, 2017
    Assignee: LONGITUDE SEMICONDUCTOR S.A.R.L.
    Inventors: Hiromu Yamaguchi, Kazuaki Tonari
  • Patent number: 9780124
    Abstract: An active matrix display device having a pixel structure in which pixel electrodes, gate wirings and source wirings are suitably arranged in the pixel portions to realize a high numerical aperture without increasing the number of masks or the number of steps. The device comprises a gate electrode and a source wiring on an insulating surface, a first insulating layer on the gate electrode and on the source wiring, a semiconductor layer on the first insulating film, a second insulating layer on the semiconductor film, a gate wiring connected to the gate electrode on the second insulating layer, a connection electrode for connecting the source wiring and the semiconductor layer together, and a pixel electrode connected to the semiconductor layer.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: October 3, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai
  • Patent number: 9780086
    Abstract: A semiconductor device includes a semiconductor substrate defining a major surface. The device further includes a first region including at least a first pillar of a first conductivity type extending in a vertical orientation with respect to the major surface. The device further includes a second region of the first conductivity type. The first pillar includes a higher doping concentration than the second region. The device further includes a Schottky contact coupled to the second region.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: October 3, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume Roig Guitart, Samir Mouhoubi, Filip Bauwens
  • Patent number: 9774010
    Abstract: A light reflective material of the present disclosure includes a base material having light transmission property; and a porous particle located in the base material, the porous particle comprising a shell defining pores, the base material having a first refractive index, the shell having a second refractive index higher than the first refractive index. A light-emitting device of the present disclosure includes a light emitter that emits light; and a reflective layer that covers a portion of a surface of the light emitter, the reflective layer comprising a base material having light transmission property and a porous particle located in the base material, the porous particle comprising a shell defining pores, the base material having a first refractive index, the shell having a second refractive index higher than the first refractive index.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: September 26, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Tatsuya Okuno
  • Patent number: 9768359
    Abstract: A semiconductor device is disclosed, and the semiconductor device comprises: a semiconductor layer; and a transparent electrode which is formed from a resistance switching material and is formed on one side of the semiconductor layer, wherein the transparent electrode includes a channel on which an electron is capable of hopping and a conductive path formed by applying a voltage that is a threshold voltage or more, and the threshold voltage for forming the conductive path is lowered by the channel.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: September 19, 2017
    Assignee: INTELLECTUAL DISCOVERY CO., LTD.
    Inventors: Tae Geun Kim, Kyung Heon Kim
  • Patent number: 9761504
    Abstract: A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric layer. The doped dielectric layer includes a first doped layer and a second doped layer. The passivation structure further includes a top dielectric layer over the doped dielectric layer.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: September 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chi Chuang, Kun-Ming Huang, Hsuan-Hui Hung, Ming-Yi Lin
  • Patent number: 9761645
    Abstract: In the case where a material containing an alkaline-earth metal in a cathode, is used, there is a fear of the diffusion of an impurity ion (such as alkaline-earth metal ion) from the EL element to the TFT being generated and causing the variation of characteristics of the TFT. Therefore, as the insulating film provided between TFT and EL element, a film containing a material for not only blocking the diffusion of an impurity ion such as an alkaline-earth metal ion but also aggressively absorbing an impurity ion such as an alkaline-earth metal ion is used.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: September 12, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Murakami, Mitsuhiro Ichijo, Taketomi Asami