Patents Examined by Moazzam Hossain
  • Patent number: 11189530
    Abstract: A manufacturing method of chips from a workpiece including plural planned dividing lines on a front surface includes a cutting step of causing a cutting blade to cut into the workpiece for which a side of the front surface of the workpiece is held by a holding table in such a manner that a side of a back surface of the workpiece is exposed and forming a cut groove that does not reach the front surface of the workpiece on the side of the back surface of the workpiece along each planned dividing line, a sticking step of sticking an expanding sheet to the workpiece, and a dividing step of dividing the workpiece along each planned dividing line by expanding the expanding sheet to form the chips from the workpiece after the sticking step and the cutting step.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: November 30, 2021
    Assignee: DISCO CORPORATION
    Inventor: Naoko Yamamoto
  • Patent number: 11189485
    Abstract: A substrate oxidation assembly includes: a chamber body defining a processing volume; a substrate support disposed in the processing volume; a plasma source coupled to the processing volume; a steam source fluidly coupled to the processing volume; and a substrate heater. A method of processing a semiconductor substrate includes: initiating conformal radical oxidation of high aspect ratio structures of the substrate comprising: heating the substrate; and exposing the substrate to steam; and conformally oxidizing the substrate. A semiconductor device includes a silicon and nitrogen containing layer; a feature formed in the silicon and nitrogen containing layer having an aspect ratio of at least 40:1; and an oxide layer on the face of the feature having a thickness in a bottom region of the silicon and nitrogen containing layer that is at least 95% of a thickness of the oxide layer in a top region.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: November 30, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Christopher S. Olsen, Taewan Kim
  • Patent number: 11186770
    Abstract: The present disclosure provides II-VI based non-Cd visible light emitting quantum dots (QDs) and a manufacturing method thereof to solve the problems with broad full width at half maximum (FWHM) and low quantum efficiency. The present disclosure further provides a QD light emitting diode (QLED) using the II-VI based non-Cd visible light emitting QDs. The QDs according to the present disclosure include a II-VI based ternary ZnSeTe core, wherein a Se:Te ratio in the ZnSeTe core is 1:10 to 100:1. According to the present disclosure, it is possible to provide QDs that emit visible light ranging from red to blue by adjusting the Se:Te ratio in the II-VI based ternary ZnSeTe core.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 30, 2021
    Assignee: Hongik University Industry-Academia Cooperation Foundation
    Inventors: Hee-Sun Yang, Eun-Pyo Jang
  • Patent number: 11186478
    Abstract: A MEMS includes a substrate having a cavity, and a moveable element arranged in the cavity, the moveable element including a first electrode, a second electrode and a third electrode that is arranged between the first electrode and the second electrode and is fixed in an electrically insulated manner from the same at discrete areas. The moveable element is configured to perform a movement along a movement direction in a substrate plan in response to an electric potential between the first electrode and the third electrode or in response to an electric potential between the second electrode and the third electrode. A dimension of the third electrode perpendicular to the substrate plane is lower than a dimension of the first electrode and a dimension of the second electrode perpendicular to the substrate plane.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: November 30, 2021
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Sergiu Langa, Holger Conrad, Klaus Schimmanz
  • Patent number: 11183381
    Abstract: A semiconductor device of the embodiment includes first and second conductive layer; a silicon nitride layer between the first conductive layer and the second conductive layer; a silicon oxide layer between the silicon nitride layer and the second conductive layer; a silicon oxynitride layer between the silicon oxide layer and the second conductive layer; and a third conductive layer between the first conductive layer and the second conductive layer, the third conductive layer electrically connected to the first and second conductive layer, a first tilt angle of a plane where the third conductive layer is in contact with the silicon oxynitride layer with respect to an interface between the silicon nitride layer and the silicon oxide layer is smaller than a second tilt angle of a plane where the third conductive layer is in contact with the silicon oxide layer with respect to the interface.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 23, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Masaki Yamada
  • Patent number: 11183606
    Abstract: A solar module and a method for fabricating a solar module comprising a plurality of rear contact solar cells are described. Rear contact solar cells (1) are provided with a large size of e.g. 156×156 mm2, Soldering pad arrangements (13, 15) applied on emitter contacts (5) and base contacts (7) are provided with one or more soldering pads (9, 11) arranged linearly. The soldering pad arrangements (13, 15) are arranged asymmetrically with respect to a longitudinal axis (17). Each solar cell (1) is then separated into first and second cell portions (19, 21) along a line (23) perpendicular to the longitudinal axis (17).
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: November 23, 2021
    Assignee: REC SOLAR PTE. LTD.
    Inventors: Philipp Johannes Rostan, Robert Wade, Noel Gonzales Diesta, Shankar Gauri Sridhara, Anders Soreng
  • Patent number: 11177220
    Abstract: Electronics devices, having vertical and lateral redistribution interconnects, are disclosed. An electronics device comprises an electronics component (e.g., die, substrate, integrated device, etc.), a die(s), and a separately formed redistribution connection layer electrically coupling the die(s) to the electronics component. The redistribution connection layer comprises dielectric layers on either side of at least one redistribution layer. The dielectric layers comprise openings that expose contact pads of the at least one redistribution layer for electrically coupling die(s) and components to each other via the redistribution connection layer. The redistribution connection layer is flexible and wrap/folded around side edges of die(s) to minimize vertical vias. Various devices and associated processes are provided.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Georg Seidemann, Andreas Wolter, Bernd Waidhas, Thomas Wagner
  • Patent number: 11173486
    Abstract: A method for fabricating a fluidic device includes depositing a sacrificial material on a pillar array arranged on a substrate. The method also includes removing a portion of the sacrificial material. The method further includes depositing a sealing layer on the pillar array to form a sealed fluidic cavity.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Evan Colgan, Joshua T. Smith, Benjamin Wunsch
  • Patent number: 11177464
    Abstract: A display apparatus includes a lower substrate including a peripheral area around a display area, an upper substrate facing the lower substrate, a display unit in the display area including a pixel circuit and a display device electrically connected to the pixel circuit, a seal in the peripheral area to surround the display unit, the seal adhering the lower substrate to the upper substrate, a power supply line between the lower substrate and the seal such that at least a portion of the power supply line and the seal overlap each other, and a first thermally conductive layer between the power supply line and the lower substrate, at least a part of the first thermally conductive layer overlapping an end portion of the power supply line, the first thermally conductive layer being connected to the power supply line and extending toward an edge of the lower substrate.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: November 16, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Takyoung Lee, Jaewook Kang, Yunmo Chung
  • Patent number: 11171187
    Abstract: A display device may include a substrate, a thin film transistor, a first electrode, a second electrode, and a barrier. The thin film transistor is disposed on the substrate. The first electrode is electrically connected to the thin film transistor. The second electrode overlaps the first electrode. The barrier has a first portion and a second portion. The second portion is disposed between the first portion and the second electrode and is fluorine-doped. A side surface of the first portion is part of a boundary of an opening of the barrier and is hydrophilic. The opening of the barrier is disposed between the first electrode and the second electrode.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: November 9, 2021
    Inventors: Beom-Soo Shin, Suk Hoon Kang, Min-Jae Kim, Hee Ra Kim, Hong Yeon Lee
  • Patent number: 11167979
    Abstract: A method for manufacturing a microelectromechanical systems (MEMS) structure with sacrificial supports to prevent stiction is provided. A first etch is performed into an upper surface of a carrier substrate to form a sacrificial support in a cavity. A thermal oxidation process is performed to oxidize the sacrificial support, and to form an oxide layer lining the upper surface and including the oxidized sacrificial support. A MEMS substrate is bonded to the carrier substrate over the carrier substrate and through the oxide layer. A second etch is performed into the MEMS substrate to form a movable mass overlying the cavity and supported by the oxidized sacrificial support. A third etch is performed into the oxide layer to laterally etch the oxidized sacrificial support and to remove the oxidized sacrificial support. A MEMS structure with anti-stiction bumps is also provided.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chung-Yen Chou
  • Patent number: 11171204
    Abstract: A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: November 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Sanjay C. Mehta, Xin Miao, Chun-Chen Yeh
  • Patent number: 11171237
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line gate structures and methods of manufacture. The structure includes: a plurality of adjacent gate structures; a bridged gate structure composed of a plurality of the adjacent gate structures; source and drain regions adjacent to the bridged gate structure and comprising source and drain metallization features; and contacts to the bridged gate structure and the source and drain metallization features.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: November 9, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Yanping Shen, Halting Wang, Hui Zang, Jiehui Shu
  • Patent number: 11171150
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening extending through the alternating sack, and a memory opening fill structure located within the memory opening. The memory opening fill structure includes a pedestal channel portion, a memory film overlying the pedestal channel portion, a vertical semiconductor channel located inside the memory film, and a channel connection strap that extends through an opening of the memory film and contacting the pedestal channel portion and the vertical semiconductor channel. The channel connection strap has a topmost surface located below a horizontal plane including a top surface of the vertical semiconductor channel.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: November 9, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Takashi Yuda, Hiroyuki Kamiya
  • Patent number: 11168407
    Abstract: In one example, an electroplating system comprises a bath reservoir, a holding device, an anode, a direct current power supply, and a controller. The bath reservoir contains an electrolyte solution. The holding device holds a wafer submerged in the electrolyte solution. The wafer comprises features covered by a cobalt layer. The anode is opposite to the wafer and submerged in the electrolyte solution. The direct current power supply generates a direct current between the holding device and the anode. A combination of forward and reverse pulses is applied between the holding device and the anode to electroplate a copper layer on the cobalt layer of the wafer.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: November 9, 2021
    Assignee: Lam Research Comporation
    Inventors: Jeyavel Velmurugan, Bryan L. Buckalew, Thomas A. Ponnuswamy
  • Patent number: 11171316
    Abstract: The present disclosure provides a display substrate, a method for preparing the same, and a display device. The method includes: providing a base substrate including a display region and at least one inner non-display region located inside the display region, with the inner non-display region including an opening region located in the middle of the inner non-display region and a reserved region located around the opening region; forming a mask pattern in the inner non-display region; forming at least one evaporation material layer on the base substrate, with the evaporation material layer being divided by the mask pattern into a first portion of the evaporation material layer formed on the mask pattern and a second portion of the evaporation material formed on other regions; processing the mask pattern; and forming a thin-film encapsulation layer on the base substrate.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: November 9, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Ziyu Zhang
  • Patent number: 11164867
    Abstract: Structures with altered crystallinity and methods associated with forming such structures. A semiconductor layer has a first region containing polycrystalline semiconductor material, defects, and atoms of an inert gas species. Multiple fins are arranged over the first region of the semiconductor layer. The structure may be formed by implanting the semiconductor layer with inert gas ions to modify a crystal structure of the semiconductor layer in the first region and a second region between the first region and a top surface of the semiconductor layer. An annealing process is used to convert the first region of the semiconductor layer to a polycrystalline state and the second region of the semiconductor layer to a monocrystalline state. The fins are patterned from the second region of the semiconductor layer and another semiconductor layer epitaxially grown over the second region of the semiconductor layer.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: November 2, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Siva P. Adusumilli, Julien Frougier, Ruilong Xie, Anthony K. Stamper
  • Patent number: 11164452
    Abstract: Disclosed are devices, systems and methods for managing parking monitoring and enforcement. In one aspect, a method of determining whether a vehicle is present in a parking space includes monitoring the parking space with a first vehicle detection technique utilizing image processing and monitoring the parking space with a second vehicle detection technique that does not utilize image processing. The parking space can be monitored with a third vehicle detection technique that is different than the first and second vehicle detection techniques. A conclusion that a vehicle has entered or left the parking space can be determined upon a agreement of the multiple techniques employed.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: November 2, 2021
    Assignee: Municipal Parking Services, Inc.
    Inventors: Mark J. Moran, Richard W. Kelley, II, Marcus N. Schmidt
  • Patent number: 11158765
    Abstract: A light-emitting component a first layer stack configured to generate light, at least one additional layer stack configured to generate light, where each of the first layer stack and the at least one additional layer stack are separately drivable from one another and where an auxiliary structure is arranged between the first layer stacks and the at least one additional layer stacks.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: October 26, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Daniel Riedel, Andreas Rausch, Ulrich Niedermeier
  • Patent number: 11158772
    Abstract: A lighting assembly is disclosed which includes a leadframe and at least one light-emitting diode (LED) element arranged on the leadframe. At least a portion of the leadframe is covered with a polyurethane coating arranged to electrically insulate the portion of the leadframe, and at least a portion of the polyurethane covered portion of the leadframe is further covered with a thermally conductive material. A method for manufacturing the lighting assembly is also disclosed.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: October 26, 2021
    Assignee: Lumileds LLC
    Inventors: Nan Chen, Hiu Tung Chu, Dong Pan, Paul Scott Martin, Tomonari Ishikawa