Patents Examined by Moazzam Hossain
  • Patent number: 10446586
    Abstract: Disclosed are a pixel unit, an array substrate and a manufacturing method therefor, a display panel and a display device. At least two step portions adjacent to each other in an upward direction are provided at at least one of a first side of a drain electrode close to a display region and a second side of the drain electrode away from the display region, such that a pixel electrode is lapped onto the drain electrode gently.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: October 15, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Xiao Wang
  • Patent number: 10446648
    Abstract: A method for manufacturing a semiconductor device includes providing a substrate, forming an amorphous layer in the substrate, performing a first etching process on the substrate using the amorphous layer as an etch stop layer to form a plurality of first fins, performing a channel stop ion implantation process into the amorphous layer to form an impurity region, and performing an annealing process to activate implanted dopants in the impurity region, wherein the amorphous layer disappears during the annealing process. The method also includes performing a second etching process on a region of the substrate disposed between the first fins to form second fins from the first fins, and forming an isolation region between adjacent second fins by filling at least a portion of an air gap between the second fins with an insulating material. The method prevents dopants of the channel stop implant from diffusing into the channel.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: October 15, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10444584
    Abstract: Although each drain electrode extension portion which is a connection region between a drain electrode and a pixel electrode does not transmit visible light, making an end side of the drain electrode extension portion coincide with an end side of the pixel electrode can improve an aperture ratio. In addition, making each semiconductor layer with high resistance protrude from the end side of the drain electrode extension portion can restrict an increase in parasitic capacitance and bring the drain electrode extension portion closer to the gate wiring.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: October 15, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Manami Ando, Manabu Tanahara
  • Patent number: 10447004
    Abstract: A laser diode system includes plurality of laser pumps, each of the plurality of laser pumps including a plurality of laser diode drivers and a plurality of laser diode elements, wherein each of the plurality of laser diode drivers is electrically coupled to power at least two of the plurality of laser diode elements. A combiner electrically is coupled to the plurality of laser diode elements to combine an output of each of the plurality of laser pumps to generate a combined output light. A controller identifies a failed laser pump or a failed laser diode element, receives an encoded key to gain access to the controller, and disables the failed laser pump or the failed laser diode element based at least in part on authenticating the encoded key.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: October 15, 2019
    Assignee: NLIGHT, INC.
    Inventor: Robert Joseph Foley
  • Patent number: 10446538
    Abstract: A method is provided for fabricating an electrostatic discharge (ESD) protection structure. The method includes forming a substrate having a first region and a second region, wherein the first region and the second region have a preset distance; forming a well area in the substrate; forming a first fin portion in the substrate in the first region and a second fin portion in the substrate in the second region; forming a supporting gate structure, wherein the supporting gate structure includes a first supporting gate crossing the first fin portion and a second supporting gate crossing the second fin portion; forming a dielectric layer on the well area; and forming a conductive structure in the dielectric layer, wherein the conductive structure includes a first conductive structure connecting to the first fin portion and a second conductive structure connecting to the second fin portion.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: October 15, 2019
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Fei Zhou
  • Patent number: 10446566
    Abstract: Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Justin B. Dorhout, Nancy M. Lomeli
  • Patent number: 10444211
    Abstract: An embodiment of the invention provides a method where an air quality forecast having an air quality turning point is received. A processor identifies an updated air quality turning point based on weather observation information. An air quality forecast at the updated air quality turning point is generated with the weather observation information and human input, which can include human knowledge from a weather expert or an air quality expert. An air quality forecast for a first time period directly prior to the updated air quality turning point is generated with the air quality forecast at the updated air quality turning point and the human input. An air quality forecast for a second time period directly after the updated air quality turning point is generated with the air quality forecast for the first time period, the air quality forecast at the updated air quality turning point, and the human input.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: October 15, 2019
    Assignee: International Business Machines Corporation
    Inventors: Xin X. Bai, Jin Dong, Hui Du, Xiao G. Rui, Xi Xia, Bao G. Xie, Wen Jun Yin, Wei Zhao
  • Patent number: 10446398
    Abstract: A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: October 15, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Cao, Shu-Jen Han, Ning Li, Jianshi Tang
  • Patent number: 10438838
    Abstract: A method and structure for providing a semiconductor-on-insulator (SCOI) wafer having a buried low-K dielectric layer includes forming a device layer on a first semiconductor substrate. In various embodiments, at least a portion of the device layer is separated from the first semiconductor substrate, where the separating forms a cleaved surface on the separated portion of the device layer. In some examples, a patterned low-K dielectric layer is formed on a second semiconductor substrate. Thereafter, and in some embodiments, the separated portion of the device layer is bonded, along the cleaved surface, to the patterned low-K dielectric layer.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: October 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hsiang Tsai, Chung-Chuan Tseng, Li Hsin Chu, Chia-Wei Liu
  • Patent number: 10439021
    Abstract: Devices and methods for forming a device are disclosed. A substrate is provided. The substrate has first and second major surfaces. A capacitor is disposed in the substrate. The capacitor includes a first electrode, a second electrode and an insulator separating the first and second electrodes. The second electrode encloses the first electrode and the insulator.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shunqiang Gong, Juan Boon Tan
  • Patent number: 10439018
    Abstract: According to some embodiments, an integrated circuit device is disclosed. The integrated circuit device include at least one inductor having at least one turn, a magnetic coupling ring positioned adjacent to the at least one inductor, the magnetic coupling ring comprising at least two magnetic coupling turns, the at least two magnetic coupling turns are disposed adjacent to the at least one turn to enable magnetic coupling between the at least two magnetic coupling turns and the at least one turn The integrated circuit device also includes a power electrode and a ground electrode, wherein the power electrode and the ground electrode are coupled to the at least one inductor and the magnetic coupling ring to provide a first current in the at least one inductor having a direction opposite to a second current in the magnetic coupling ring to cancel at least a portion of a magnetic field generated by the at least one inductor.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: October 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao Chieh Li, Hao-chieh Chan
  • Patent number: 10439031
    Abstract: Structures for a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit, and methods of fabricating a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit. A doped semiconductor layer that includes a first region with a first electrode of the vertical electrical fuse and a second region with a first source/drain region of the vertical-transport field effect transistor. A semiconductor fin is formed on the first region of the doped semiconductor layer, and a fuse link is formed on the second region of the doped semiconductor layer. A second source/drain region is formed that is coupled with the fin. A gate structure is arranged vertically between the first source/drain region and the second source/drain region. A second electrode of the vertical fuse is formed such that the fuse link is arranged vertically between the first electrode and the second electrode.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Kangguo Cheng, Tenko Yamashita, Chun-chen Yeh
  • Patent number: 10439041
    Abstract: A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: October 8, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroaki Niimi, Mahalingam Nandakumar
  • Patent number: 10439005
    Abstract: A multicolor light-emitting element that utilizes fluorescence and phosphorescence and is advantageous for practical application is provided. The light-emitting element has a stacked-layer structure of a first light-emitting layer containing a host material and a fluorescent substance and a second light-emitting layer containing two kinds of organic compounds and a substance that can convert triplet excitation energy into luminescence. Note that light emitted from the first light-emitting layer has an emission peak on the shorter wavelength side than light emitted from the second light-emitting layer.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: October 8, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiro Ishisone, Satoshi Seo, Yusuke Nonaka, Nobuharu Ohsawa
  • Patent number: 10431464
    Abstract: A method includes forming a dielectric layer on a substrate and patterning the dielectric layer to form an opening in the dielectric layer. A first layer of metallic material (e.g., non-nitride metal) is deposited to form a liner layer on an upper surface of the dielectric layer and on exposed surfaces within the opening. A second layer of metallic material (e.g., copper) is deposited to fill the opening with metallic material. An overburden portion of the second layer of metallic material is removed by planarizing the second layer of metallic material down an overburden portion of the liner layer on the upper surface of the dielectric layer. A surface treatment process (e.g., plasma nitridation) is performed to convert the overburden portion of the liner layer into a layer of metal nitride material. The layer of metal nitride material is selectively etched away using a wet etch process.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: October 1, 2019
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 10429269
    Abstract: A building safety verification system and a building safety verification method for estimating a degree of damage of a building after an earthquake occurs are provided. The building safety verification system includes: an inter-story displacement measurement unit which obtains, from measurement data of acceleration sensors which measure accelerations of a plurality of stories in a building, an inter-story displacement of each of the stories; a natural period measurement unit which obtains a natural period of microtremor of the building from measurement data of a micro vibration sensor which measures micro vibration of a highest story of the building or a story near the highest story; and a building safety evaluation unit which evaluates soundness of the building from the inter-story displacement obtained by the inter-story displacement measurement unit and the natural period obtained by the natural period measurement unit.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: October 1, 2019
    Assignee: NTT FACILITIES, INC.
    Inventors: Kenichi Yoshida, Shigeto Nagashima, Toshiya Motohi, Kouzou Toyota, Yoshifumi Sugimura, Wataru Gotou, Maki Mochiduki, Hiroyasu Nishii
  • Patent number: 10431731
    Abstract: The present invention comprises: a step of applying a liquid composition for forming a PZT ferroelectric film; a step of drying the film applied with the liquid composition; a step of irradiating UV rays onto the dried film at a temperature of 150 to 200° C. in an oxygen-containing atmosphere; and after the application step, the drying step, and the UV irradiation step once, or more times, a step of firing for crystallizing a precursor film of the UV-irradiated ferroelectric film by raising a temperature with a rate of 0.5° C./second or higher in an oxygen-containing atmosphere or by raising a temperature with a rate of 0.2° C./second or higher in a non-oxygen containing atmosphere, followed by keeping the temperature at 400 to 500° C. An amount of liquid composition is set such that thickness of the ferroelectric film be 150 nm or more for each application and ozone is supplied during UV irradiation.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: October 1, 2019
    Assignees: JAPAN ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, MITSUBISHI MATERIALS CORPORATION
    Inventors: Yuki Tagashira, Reijiro Shimura, Yuzuru Takamura, Jinwang Li, Tatsuya Shimoda, Toshiaki Watanabe, Nobuyuki Soyama
  • Patent number: 10428645
    Abstract: An integrated and rigless method of determining the location and the type of damage in casing or tubing of a wellbore that involves recording a thickness profile of the casing or tubing, a temperature log, and a noise log along the depth of the wellbore, followed by locating the damage from the thickness profile, and determining the type of damage from the temperature log and the noise log.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: October 1, 2019
    Assignee: King Fahd University of Petroleum and Minerals
    Inventors: Ali Musa Al-Hussain, M. Enamul Hossain
  • Patent number: 10429529
    Abstract: A method for adaptively determining one or more faults from geological survey data includes: (a) generating at least one attribute volume comprising a plurality of attributes from said geological survey data; (b) identifying at least one region of interest on a predetermined cross-section of said at least one attribute volume; (c) adding at least one seed to said at least one region of interest; (d) defining at least one representative area in accordance with said region of interest; (e) starting an initial generation of at least one basic geological object by adapting said at least one seed and/or representative area; (f) selectively determining growth confidence levels for any of said at least one basic geological object based on a realistic geological principles, and mapping said at least one basic geological object with colour-coded data of said growth confidence levels; (g) monitoring a visual representation of said at least one basic geological object during said initial generation; (h) selectively stop
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: October 1, 2019
    Assignee: Foster Findlay Associates Limited
    Inventors: Stephen Purves, James Lowell, Dale Norton, Jonathan Henderson, Gaynor Paton, Nicholas McArdle
  • Patent number: 10431684
    Abstract: A method to improve transistor performance uses a wafer (100) of single-crystalline semiconductor with a first zone (102) of field effect transistors (FETs) and circuitry at the wafer surface, and an infrared (IR) laser with a lens for focusing the IR light to a second depth (112) farther from the wafer surface than the first depth of the first zone. The focused laser beam is moved parallel to the surface across the wafer to cause local multi-photon absorption at the second depth for transforming the single-crystalline semiconductor into a second zone (111) of polycrystalline semiconductor with high density of dislocations. The second zone has a height and lateral extensions, and permanently stresses the single-crystalline bulk semiconductor; the stress increases the majority carrier mobility in the channel of the FETs, improving the transistor performance.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: October 1, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Steven Kummerl, Matthew John Sherbin, Saumya Gandhi