Patents Examined by Moazzam Hossain
  • Patent number: 11501928
    Abstract: A method of fabricating and packaging an ohmic micro-electro-mechanical system (MEMS) switch device may comprise constructing the switch device on an insulating substrate. The switch device may have contacts that consist of a platinum-group metal. The method may further comprise forming an oxidized layer of the platinum-group metal on an outer surface of each of the one or more contacts. The method may further comprise bonding an insulating cap to the insulating substrate, to hermetically seal the switch device. The bonding may occur in an atmosphere that has a proportion of oxygen within a range of 0.5% to 30%, such that, after the switch device has been hermetically sealed within the sealed cavity, an atmosphere within the sealed cavity has a proportion of oxygen within the range of 0.5% to 30%. The platinum-group metal may be ruthenium, and the oxidized layer of the platinum-group metal may be ruthenium dioxide.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: November 15, 2022
    Assignee: MENLO MICROSYSTEMS, INC.
    Inventors: Andrew Minnick, Christopher F. Keimel, Xu Zhu
  • Patent number: 11502033
    Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer and a second dielectric layer that are sequentially stacked on the substrate, a contact that penetrates the first dielectric layer and extends toward the substrate, and a conductive line that is provided in the second dielectric layer and electrically connected to the contact, The conductive line extends in a first direction. The contact comprises a lower segment in the first dielectric layer and an upper segment in the second dielectric layer. A width in a second direction of the conductive line decreases with decreasing distance from the substrate. The second direction intersects the first direction. A sidewall of the upper segment of the contact is in contact with the conductive line.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: November 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kiho Yang
  • Patent number: 11494619
    Abstract: A device includes first wires, second wires, resistors, and a processor. Input signals are transmitted from the first wires through the resistors to the second wires. The processor receives a sum value of the input signals from one of the second wires, and shifts the sum value by a nonlinear activation function to generate a shifted sum value. The processor calculates a backpropagation value based on the shifted sum value and a target value, and generates a pulse number based on a corresponding input signal of the input signal and the backpropagation value. Each of a value of the corresponding input signal and the backpropagation value is higher than or equal to a threshold value. The processor applies a voltage pulse to one of the resistors related to the corresponding input signal based on the pulse number.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: November 8, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Tuo-Hung Hou, Chih-Cheng Chang
  • Patent number: 11482564
    Abstract: A method of manufacturing an image sensing apparatus includes: forming a first substrate structure including a first region of a pixel region, the first substrate structure having a first surface and a second surface; forming a second substrate structure including a circuit region for driving the pixel region, the second substrate structure having a third surface and a fourth surface; bonding the first substrate structure to the second substrate structure, such that the first surface is connected to the third surface; forming a second region of the pixel region on the second surface; forming a first connection via, the first connection via extending from the second surface to pass through the first substrate structure; mounting semiconductor chips on the fourth surface, using a conductive bump; and separating a stack structure of the first substrate structure, the second substrate structure, and the semiconductor chips into unit image sensing apparatuses.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: October 25, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Hyun Yoon, Doo Won Kwon, Kwan Sik Kim, In Gyu Baek, Tae Young Song
  • Patent number: 11482670
    Abstract: A method of fabricating a variable resistance memory device includes: forming a bottom electrode on a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer has a first trench that exposes the bottom electrode; forming a variable resistance layer in the first trench; and irradiating the variable resistance layer with a laser, wherein the variable resistance layer is irradiated by the laser for a time of about 1.8 ?s to about 54 ?s.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: October 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jiho Park, Kwangmin Park, Jeonghee Park, Changyup Park, Sukhwan Chung
  • Patent number: 11469348
    Abstract: The invention described herein provides a method and apparatus to realize incorporation of Beryllium followed by activation to realize p-type materials of lower resistivity than is possible with Magnesium. Lower contact resistances and more effective electron confinement results from the higher hole concentrations made possible with this invention. The result is a higher efficiency GaN-based LED with higher current handling capability resulting in a brighter device of the same area.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: October 11, 2022
    Assignee: Odyssey Semiconductor, Inc.
    Inventors: James R. Shealy, Richard J. Brown
  • Patent number: 11469145
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The method includes forming a gate material layer in the trench. The method includes forming a planarization layer over the gate material layer. The planarization layer includes a first material that is different from a second material of the gate material layer and a third material of the dielectric layer. The method includes performing an etching process to remove the planarization layer and a first upper portion of the gate material layer so as to form a gate in the trench.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chai-Wei Chang, Po-Chi Wu, Wen-Han Fang
  • Patent number: 11459227
    Abstract: Disclosed is a hinged MEMS and/or NEMS device with out-of-plane movement including a first portion and a second portion that is hinged so as to be able to rotate with respect to the first portion about an axis of rotation contained in a first mean plane of the device. The device also includes a hinging element that connects the first portion and the second portion and that is stressed flexurally and a sensing element that extends between the first portion and the second portion and that deforms during the movement of the second portion. Finally, the device includes two blades that extend perpendicularly to the mean plane of the hinge device and parallel to the axis of rotation, the blades being placed between the hinging element and the sensing element and connecting the first portion and the second portion and being stressed torsionally during the movement of the second portion.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: October 4, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Loic Joet, Audrey Berthelot
  • Patent number: 11454553
    Abstract: A multi-purpose Micro-Electro-Mechanical Systems (MEMS) thermopile sensor able to use as a thermal conductivity sensor, a Pirani vacuum sensor, a thermal flow sensor and a non-contact infrared temperature sensor, respectively.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: September 27, 2022
    Inventor: Xiang Zheng Tu
  • Patent number: 11450784
    Abstract: A light-emitting thyristor includes a first semiconductor layer of a P type, a second semiconductor layer of an N type arranged adjacent to the first semiconductor layer; a third semiconductor layer of the P type arranged adjacent to the second semiconductor layer; and a fourth semiconductor layer of the N type arranged adjacent to the third semiconductor layer. A part of the first semiconductor layer is an active layer adjacent to the second semiconductor layer. A dopant concentration of the active layer is higher than or equal to a dopant concentration of the third semiconductor layer. A thickness of the third semiconductor layer is thinner than a thickness of the second semiconductor layer. A dopant concentration of the second semiconductor layer is lower than the dopant concentration of the third semiconductor layer.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: September 20, 2022
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hiroto Kawada, Kenichi Tanigawa, Shinya Jyumonji, Takuma Ishikawa, Chihiro Takahashi
  • Patent number: 11450803
    Abstract: A resistance change element includes a first lead electrode, a resistance change layer provided on the first lead electrode, and a second lead electrode provided on the resistance change layer. The surface of the first lead electrode on the resistance change layer side includes a first region in which the resistance change layer is provided, and a second region that is a region other than the first region. In the second region, a second material having a work function that is larger than that of a first material configuring the first lead electrode is unevenly distributed.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: September 20, 2022
    Assignee: TDK Corporation
    Inventor: Naoki Ohta
  • Patent number: 11444240
    Abstract: Methods, systems, and devices are disclosed for enhancement of spin-orbit torque. In one aspect, a magnetic device includes a magnetic tunneling junction (MTJ), including a free magnetic layer, a pinned magnetic layer and a non-magnetic junction layer between the free magnetic layer and the pinned magnetic layer, and a spin Hall effect metal layer that includes one or more insertion metal layers operable to introduce interfacial scattering of electrons flowing in the spin Hall metal layer to increase the spin current that interacts with and changes the magnetization of the free magnetic layer of the MTJ.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: September 13, 2022
    Assignee: Cornell University
    Inventors: Robert A. Buhrman, Lijun Zhu
  • Patent number: 11430824
    Abstract: An integrated circuit (IC) device includes a first substrate and a first structure on a front surface of the first substrate. The first structure includes a first interlayer insulating layer structure including a plurality of first conductive pad layers spaced apart from one another at different levels of the first interlayer insulating layer structure. The IC device includes a second substrate on the first substrate and a second structure on a front surface of the second substrate, which faces the front surface of the first substrate. The second structure includes a second interlayer insulating layer structure bonded to the first interlayer insulating layer structure. A through-silicon via (TSV) structure penetrates the second substrate and the second interlayer insulating layer structure. The TSV structure is in contact with at least two first conductive pad layers of the plurality of first conductive pad layers located at different levels.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: August 30, 2022
    Inventors: Sun-hyun Kim, Sang-il Jung, Byung-jun Park
  • Patent number: 11420866
    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical systems (MEMS) structure including a composite spring. A first substrate underlies a second substrate. A third substrate overlies the second substrate. The first, second, and third substrates at least partially define a cavity. The second substrate comprises a moveable mass in the cavity and between the first and third substrates. The composite spring extends from a peripheral region of the second substrate to the moveable mass. The composite spring is configured to suspend the moveable mass in the cavity. The composite spring includes a first spring layer comprising a first crystal orientation, and a second spring layer comprising a second crystal orientation different than the first crystal orientation.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Sung Chang, Shang-Ying Tsai, Wei-Jhih Mao
  • Patent number: 11424256
    Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Thimmegowda, Andrew R. Bicksler, Roland Awusie
  • Patent number: 11414319
    Abstract: A method for producing a nanocrystalline, gas-sensitive layer structure. The method for producing a nanocrystalline, gas-sensitive layer structure on a substrate comprises the steps: depositing a base layer made of a base material; depositing a doping layer made of a doping material; repeating the preceding steps; and performing a tempering step, whereby a gas-sensitive, nanocrystalline layer structure is produced.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: August 16, 2022
    Assignee: Robert Bosch GmbH
    Inventors: Andreas Krauss, Elisabeth Preiss
  • Patent number: 11411170
    Abstract: A magnetoresistive memory device includes a magnetic tunnel junction including a free layer, at least two tunneling dielectric barrier layers, and at least one metallic quantum well layer. The quantum well layer leads to the resonant electron tunneling through the magnetic tunnel junction in such a way that it strongly enhances the tunneling probability for one of the magnetization states of the free layer, while this tunneling probability remains much smaller in the opposite magnetization state of the free layer. The device can be configured in a spin transfer torque device configuration, a voltage-controlled magnetic anisotropy, a voltage controlled exchange coupling device configuration, or a spin-orbit-torque device configuration.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: August 9, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Alan Kalitsov, Bhagwati Prasad, Derek Stewart
  • Patent number: 11411179
    Abstract: A method of fabricating a variable resistance memory device that includes forming a plurality of memory cells on a substrate. Each of the plurality of memory cells in a switching device and a variable resistance pattern. A capping structure is formed that commonly covers lateral side surfaces of the plurality of memory cells. An insulating gapfill layer is formed that covers the capping structure and fills a region between adjacent memory cells of the plurality of memory cells. The forming of the capping structure includes forming a second capping layer including silicon oxide that covers the lateral side surfaces of the plurality of memory cells. At least a partial portion of the second capping layer is nitrided by performing a first decoupled plasma process to form a third capping layer that includes silicon oxynitride.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: August 9, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaeho Jung, Kwangmin Park, Jonguk Kim, Dongsung Choi
  • Patent number: 11401156
    Abstract: The present invention discloses a micro-electro-mechanical system silicon on insulator (MEMS SOI) pressure sensor and a method for preparing the same. The pressure sensor includes a bulk silicon layer, a buried oxide layer, a substrate, a varistor, a passivation layer, and an electrode layer. The varistor is obtained by means of photolithography and ion implantation on a device layer of an SOI wafer. The passivation layer is SiO2 formed by means of annealing treatment on the SOI wafer. An annealing atmosphere is one of pure O2, a gas mixture of O2/H2O, a gas mixture of O2/NO, a gas mixture of O2/HCl, and a gas mixture of O2/CHF3. By means of the annealing treatment, the damage to a surface of the buried oxide layer as a result of over-etching during formation of the varistor by means of photolithography is eliminated and the unstability of the sensor caused by body and interface defects of the passivation layer and trapped charges thereof is resolved.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: August 2, 2022
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Xiaodong Huang, Zhikang Lan, Pengfei Zhang
  • Patent number: 11393771
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao Chun Liu, Ching-Wen Hsiao, Kuo-Ching Hsu, Mirng-Ji Lii