Patents Examined by Moazzam Hossain
  • Patent number: 10847449
    Abstract: A copper lead frame used in the assembly of a semiconductor device includes a die flag and lead fingers extending away from the die flag. Each lead finger has a proximal end near the die flag and a distal end further away from the die flag. Metal plating is formed on the lead fingers, where first lead fingers have the metal plating on their proximal ends and second lead fingers have the metal plating on their distal ends. The first and second lead fingers are arranged alternately around the die flag.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: November 24, 2020
    Assignee: NXP USA, INC.
    Inventors: Meijiang Song, Allen Marfil Descartin, Mariano Layson Ching, Jr., Lidong Zhang, Jun Li
  • Patent number: 10847418
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a first dielectric layer over a semiconductor substrate and forming a first conductive feature extending into the first dielectric layer. The first conductive feature has a planar top surface. The method also includes forming a second dielectric layer over the first conductive feature. The method further includes forming a hole in the second dielectric layer to expose the planar top surface of the first conductive feature. In addition, the method includes partially removing the first conductive feature from the planar top surface of the first conductive feature to form a curved surface of the first conductive feature. The method further includes forming a second conductive feature to fill the hole after the curved surface of the first conductive feature is formed.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-Yen Peng, Chia-Tien Wu, Jye-Yen Cheng
  • Patent number: 10849207
    Abstract: Disclosed herein is a lighting system configured to obtain an indicator data of a RF spectrum signal generated by a number of receivers at a number of times in an area. At each respective one of the number of times, for each respective one of the receivers, apply one of a plurality of heuristic algorithm coefficients to each indicator data for the respective time, based on results of the applications of the coefficients to indicator data, generate an indicator data metric value for each of the indicator data for the respective time, and process the indicator data metric values to compute an output value. The lighting system is further configured to compare the output value at each of the plurality of times with a threshold to detect one of an occupancy condition or a non-occupancy condition in the area and control the light source in response to the detected one of the occupancy condition or the non-occupancy condition in the area at each of the number of times.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: November 24, 2020
    Assignee: ABL IP HOLDING LLC
    Inventors: Min-Hao Michael Lu, Michael Miu, Eric J. Johnson
  • Patent number: 10840098
    Abstract: A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: November 17, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Yuki Nakano
  • Patent number: 10840417
    Abstract: A method for manufacturing an optoelectronic component and an optoelectronic component are disclosed. In an embodiment, a method includes applying a conversion layer including a luminescence conversion material to a support plate including a glass, arranging at least two optoelectronic semiconductor chips over the conversion layer on a side remote from the support plate and forming an envelope material free from a luminescence conversion material between the optoelectronic semiconductor chips, thereby forming a workpiece.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: November 17, 2020
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Matthias Knoerr
  • Patent number: 10840248
    Abstract: A resistor for dynamic random access memory includes a substrate with a memory cell region and a peripheral region defined thereon, and a resistor formed on a shallow trench isolation of the substrate, wherein the resistor is provided with a winding portion and terminal portions at two ends of the winding portion. The winding portion is electrically connected with an overlying metal layer through contacts, and the terminal portion includes a polysilicon layer and a metal multilayer from the bottom up.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: November 17, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Yukihiro Nagai
  • Patent number: 10840416
    Abstract: The invention relates to an optoelectronic component (100) comprising a semiconductor chip (1) configured for emitting radiation, a conversion element (2) comprising quantum dots (5) and configured for wavelength conversion of radiation, wherein the conversion element (2) comprises a layer structure (7) having a plurality of inorganic barrier layers (31, 32, 33, 34), wherein the inorganic barrier layers (31, 32, 33, 34) are spatially separated from one another at least regionally by a hybrid polymer (4), wherein the hybrid polymer (4) comprises organic and inorganic regions that are covalently bonded to one another, wherein the quantum dots (5) are embedded in the hybrid polymer (4) and/or at least in one of the barrier layers (31, 32, 33, 34).
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: November 17, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: David O'Brien, Georg Dirscherl
  • Patent number: 10825894
    Abstract: Provided are MIM capacitor and method of manufacturing the same. The MIM capacitor includes a first electrode, a second electrode, a third electrode, a first insulating layer, a second insulating layer, and a first spacer. The first electrode and the third electrode are electrically connected to each other. The first insulating layer is between the first electrode and the second electrode. The second insulating layer is between the second electrode and the third electrode. The first spacer is located between a sidewall of the first electrode and the first insulating layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Jiun Wu, Shun-Yi Lee
  • Patent number: 10822330
    Abstract: The present specification relates to a hetero-cyclic compound and an organic light emitting device including the same.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: November 3, 2020
    Assignee: LG Chem, Ltd.
    Inventors: Yongbum Cha, Seongmi Cho, Jungbum Kim, Sung Kil Hong, Jiwon Kwak
  • Patent number: 10825846
    Abstract: An imaging device includes: a semiconductor substrate; a first pixel including: a first photoelectric converter above the semiconductor substrate, including first and second electrodes and a first photoelectric conversion layer between the first and second electrodes, configured to convert incident light into first charge; and a first charge accumulation region in the semiconductor substrate, electrically connected to the second electrode; and a second pixel including a second photoelectric converter above the semiconductor substrate, including third and fourth electrodes and a second photoelectric conversion layer between the third and fourth electrodes, configured to convert incident light into second charge; and a second charge accumulation region in the semiconductor substrate, electrically connected to the fourth electrode.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: November 3, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kyosuke Kobinata, Sanshiro Shishido, Yoshihiro Sato
  • Patent number: 10818772
    Abstract: Fabrication methods and device structures for a heterojunction bipolar transistor. A trench isolation region is formed that surrounds an active region of semiconductor material, a collector is formed in the active region, and a base layer is deposited that includes a first section over the trench isolation region, a second section over the active region, and a third section over the active region that connects the first section and the second section. An emitter is arranged over the second section of the base layer, and an extrinsic base layer is arranged over the first section of the base layer and the third section of the base layer. The extrinsic base layer includes a first section containing polycrystalline semiconductor material and a second section containing single-crystal semiconductor material. The first and second sections of the extrinsic base layer intersect along an interface that extends over the trench isolation region.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Vibhor Jain, Pernell Dongmo, Cameron Luce, James W. Adkisson, Qizhi Liu
  • Patent number: 10818840
    Abstract: OVJP print bars are provided that include multiple print head segments, each of which includes a print head and which can be positioned relative to the substrate independently of each other print head segment. Accordingly, a more consistent head-to-substrate distance can be maintained even for substrates that are not uniformly planar.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: October 27, 2020
    Assignee: Universal Display Corporation
    Inventors: William E. Quinn, Gregory McGraw, Gregg Kottas
  • Patent number: 10811509
    Abstract: A semiconductor device includes a source/drain feature disposed over a substrate. The source/drain feature includes a first nanowire, a second nanowire disposed over the first nanowire, a cladding layer disposed over the first nanowire and the second nanowire and a spacer layer extending from the first nanowire to the second nanowire. The device also includes a conductive feature disposed directly on the source/drain feature such that the conductive feature physically contacts the cladding layer and the spacer layer.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ching-Fang Huang, Carlos H. Diaz, Chih-Hao Wang, Wen-Hsing Hsieh, Ying-Keung Leung
  • Patent number: 10811537
    Abstract: A device includes a semiconductor substrate, an isolation structure, and an epitaxial fin portion. The semiconductor substrate has an implanted region. The implanted region has a bottom fin portion thereon, in which a depth of the implanted region is smaller than a thickness of the semiconductor substrate. The isolation structure surrounds the bottom fin portion. The epitaxial fin portion is disposed over a top surface of the bottom fin portion, in which the implanted region of the semiconductor substrate includes oxygen and has an oxygen concentration lower than about 1·E+19 atoms/cm3.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Yu Lin, Ming-Hua Yu, Tze-Liang Lee, Chan-Lon Yang
  • Patent number: 10811539
    Abstract: Provided herein are devices, systems, and methods of employing the same for the performance of bioinformatics analysis. The apparatuses and methods of the disclosure are directed in part to large scale graphene FET sensors, arrays, and integrated circuits employing the same for analyte measurements. The present GFET sensors, arrays, and integrated circuits may be fabricated using conventional CMOS processing techniques based on improved GFET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense GFET sensor based arrays. Improved fabrication techniques employing graphene as a reaction layer provide for rapid data acquisition from small sensors to large and dense arrays of sensors. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes, including DNA hybridization and/or sequencing reactions.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: October 20, 2020
    Assignee: NANOMEDICAL DIAGNOSTICS, INC.
    Inventors: Pieter van Rooyen, Mitchell Lerner, Paul Hoffman
  • Patent number: 10813225
    Abstract: A method and structure for forming conductive structure such as an electric circuit, or a portion of an electric circuit, can include the use of a thermal print head and a ribbon including a carrier and a metal layer. The thermal print head is used to print a first portion of the metal layer onto a sacrificial print medium. The first portion printed has a first pattern, where a second portion having a second pattern remains on the carrier. The first pattern is a reverse image at least a portion of the electric circuit, while the second pattern includes at least a portion of the electric circuit. The second portion having the second pattern can be transferred to a circuit substrate, then used as an electric circuit.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: October 20, 2020
    Assignee: XEROX CORPORATION
    Inventor: Marc D. Daniels
  • Patent number: 10804354
    Abstract: A radio frequency resistor element comprises a resistive polysilicon trace, an isolation component and a semiconductor substrate. The resistive polysilicon trace is located above the isolation component. The isolation component is laterally at least partially surrounded by a modified semiconductor region located above the semiconductor substrate and having a higher charge carrier recombination rate than the semiconductor substrate.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: October 13, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Hans Taddiken, Martin Bartels, Andrea Cattaneo, Henning Feick, Christian Kuehn, Anton Steltenpohl
  • Patent number: 10804378
    Abstract: A method is performed to a structure that includes a substrate with first and second regions for logic and RF devices respectively, first fin and first gate structure over the first region, second fin and second gate structure over the second region, and gate spacers over sidewalls of the gate structures. The method includes performing a first etching to the first fin to form a first recess; and performing a second etching to the second fin to form a second recess. The first and second etching are tuned to differ in at least one parameter such that the first recess is shallower than the second recess and a first distance between the first recess and the first gate structure along the first fin lengthwise is smaller than a second distance between the second recess and the second gate structure along the second fin lengthwise.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Tsun Tsai, Tong Jun Huang, I-Chih Chen, Chi-Cherng Jeng
  • Patent number: 10796961
    Abstract: A method of singulating a wafer includes providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces. The wafer has first and second opposing major surfaces, a layer of material atop the second major surface, and portions of the layer of material are adapted to remain atop surfaces of the plurality of die after completion of the method of singulating the wafer. The method includes placing the wafer onto a carrier substrate and singulating the wafer through the spaces to form singulation lines, wherein singulating comprises leaving at least a portion of the layer of material under the singulation lines. The method includes separating the layer of material under the singulation lines by applying pressure to the wafer and applying high frequency vibrations to fatigue the layer of material.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: October 6, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 10796943
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned mask layer is formed on a semiconductor substrate. An isolation trench is formed in the semiconductor substrate by removing a part of the semiconductor substrate. A liner layer is conformally formed on an inner sidewall of the isolation trench. An implantation process is performed to the liner layer. The implantation process includes a noble gas implantation process. An isolation structure is at least partially formed in the isolation trench after the implantation process. An etching process is performed to remove the patterned mask layer after forming the isolation structure and expose a top surface of the semiconductor substrate. A part of the liner layer formed on the inner sidewall of the isolation trench is removed by the etching process. The implantation process is configured to modify the etch rate of the liner layer in the etching process.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: October 6, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Shi-You Liu, Shao-Hua Hsu