Abstract: A wafer processing method for processing a wafer which has one side in which a circular recessed portion is formed in a region surrounded by an annular protruding portion is performed by a thermocompression bonding apparatus including a first recessed portion, a second recessed portion, and a holding table that is disposed on the second recessed portion. In the method, the wafer the one side of which is oriented upward is held from a lower side by the holding table, a sheet is sandwiched by the first recessed portion and the second recessed portion, the first recessed portion is depressurized while the second recessed portion is depressurized, pressure inside the first recessed portion is increased, the sheet is caused to come into contact with the one side of the wafer, and the sheet is heated, to thermocompression-bond the sheet to the one side of the wafer.

Abstract: Light-emitting diode (LED) packages, and more particularly to a light collector for light mixing in LED packages to improve the far field emission pattern (FFP) of the LED packages are disclosed. The LED package can include one or more LED chips with different wavelength ranges, and the light collector placed over the LED chips can have a reflective surface, save for a reduced aperture through which the light form the LED chips can be emitted after mixing in the light collector. The LED package can also include a lens to further improve the FFP. In an embodiment the light collector can include diffuser material to facilitate the mixing of the light within the light collector. The LED package with the light collector mixes multiple emission point sources into a single point source, or reduced-area source, that considerably improves the FFP of multi-colored LED chips of the LED package.

Abstract: The disclosed semiconductor structure includes: a substrate and a data line on the substrate, the data line extends along a first direction; the first transistor and the second transistor located on the first transistor's side away from the data line; each of the first transistor and the second transistor includes: a semiconductor column, the semiconductor column is located on a part of the top surface of the data line and extends along the third direction; an isolation structure inside the semiconductor column; along the second direction, the thickness of the isolation structure in different regions in the third direction is different, and the isolation structure runs through the semiconductor columns, and two of the first, the second and the third directions intersect each other. This improves the sensitivity of the second transistor to the change in current in the first transistor while reducing the leakage current in the first transistor.

Abstract: Transistor structures comprising a stack of channel material layers may be fabricated from a material stack comprising an uppermost sacrificial material layer over one or more bilayers. Each bilayer includes a sacrificial material layer and a channel material layer. The uppermost sacrificial material layer may ensure an uppermost channel material layer will have substantially the same structure as an underlying channel material layer. A channel portion of all channel material layers may therefore have substantially the same thickness. End portions of all channel material layers may therefore also be both above and below a first gate spacer with a second gate spacer adjacent to a sidewall of the end portions. A channel portion of an underlying one of the channel material layers may have a lesser thickness than that of its end portions. An uppermost channel material layer may advantageously have substantially the same difference in layer thickness between end portions and channel portion.

Abstract: A semiconductor structure includes a substrate, a vertical stack including nanostructures, and a gate structure wrapping around each of the nanostructures. The nanostructures are suspended and vertically arranged over the substrate. The gate structure includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The semiconductor structure further includes inner spacers and gate spacers. The inner spacers are formed on opposite sides of the gate structure, between the nanostructures, and separating the nanostructures from each other. The gate spacers are formed on the opposite sides of the gate structure and over a topmost one of the nanostructures. The gate dielectric layer includes a first portion formed on the nanostructures and a second portion extending from the first portion. The first portion and the second portion have a first thickness and a second thickness, respectively. The first thickness is greater than the second thickness.

Abstract: A semiconductor device includes a source/drain having a height, a length, and a width. A full wrap-around contact surrounds a partial length of the source/drain, wherein the full wrap-around contact includes a partial front-side wrap-around contact from a front side of a substrate and a partial back-side wrap-around contact from a back side of the substrate.

Abstract: Drive substrates and display panels are provided. In a thin film transistor of the drive substrate, a structure with double-gate and double-active layer is formed by a first active layer, a first gate, a first sub-gate of a second gate, and a part of a second active layer in an area adjacent to an output electrode; and a structure with single active layer and top gate is formed by a second sub-gate of the second gate and a part of the second active layer in an area adjacent to an input electrode. The first gate and the second gate together control a first channel of the first active layer and a first portion of a second channel of the second active layer.

Abstract: A semiconductor device includes: a semiconductor base body of a first conductivity-type; a first well region of a second conductivity-type provided in the semiconductor base body; at least one second well region of the first conductivity-type implementing a part of a high-side circuit provided in the first well region; a buried layer of the second conductivity-type provided at a bottom of the first well region and having a higher impurity concentration than the first well region; a voltage blocking region of the second conductivity-type provided at a circumference of the first well region; and an extraction region of the first conductivity-type provided to have a greater depth than the second well region at least at a part of a circumference of the high-side circuit in the first well region so as to be opposed to the second well region.

Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.

Abstract: A semiconductor device may include a substrate, data storage patterns on the substrate and spaced apart from each other in a first direction and a second direction that intersect each other and are parallel to a top surface of the substrate, first cell conductive lines that extend in the first direction and are spaced apart from each other in the second direction on the data storage patterns, cell via contacts that are spaced apart from each other in the first direction and disposed between a pair of the first cell conductive lines, dummy data storage patterns that are spaced apart from each other in the first direction between the first cell conductive lines and are disposed between the cell via contacts, and upper conductive lines on the cell via contacts and electrically connected to the cell via contacts, respectively.

Abstract: A non-volatile memory device may include a memory cell region and a peripheral circuit region positioned below the memory cell region in the vertical direction. The memory cell region may include a plurality of channel structures extending in a vertical direction, a first metal layer over the plurality of channel structures, a first capping layer over the first metal layer, a first upper insulation layer over the first capping layer, and at least one first dummy contact penetrating through the first capping layer. The first metal layer may include a plurality of bit lines and at least one dummy bit line. The bit lines may be respectively connected to the plurality of channel structures. The at least one first dummy contact may be on the at least one dummy bit line and may provide a migration path for hydrogen ions in the first upper insulation layer.

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

Abstract: A semiconductor structure and a manufacturing method thereof are provided in the present application provides. The semiconductor structure includes a substrate and a heterojunction structure located on the substrate. The heterojunction structure includes a channel layer and a barrier layer located on the channel layer. The channel layer includes at least one n-type doped layer. The manufacturing method of the semiconductor structure includes: providing a substrate; forming a heterojunction structure on the substrate, where forming the heterojunction structure includes: forming a channel layer on the substrate, doping the channel layer to form an n-type doped layer; forming a barrier layer on the channel layer; forming a gate electrode, a source electrode and a drain electrode, the gate electrode is located on the heterojunction structure, and the source electrode and the drain electrode are located on two sides of the grid electrode, separately.

Abstract: A semiconductor device includes a channel region formed on a substrate, a source region formed on the channel region, a drain region formed on the channel region, a gate region formed on the channel region between the source region and the drain region, a source contact region formed on a portion of the source region, and a resistance region formed on another portion of the source region. The source contact region and the resistance region are electrically connected in parallel with a source terminal.

Abstract: A semiconductor device includes: a drift layer of a first conduction type provided in a semiconductor substrate having a first principal plane and a second principal plane opposed to the first principal plane; a first semiconductor layer of a second conduction type provided between the first principal plane of the semiconductor substrate and the drift layer and having impurity concentration higher than impurity concentration of the drift layer; a first buffer layer of a first conduction type provided between the second principal plane of the semiconductor substrate and the drift layer and having hydrogen-induced donors with impurity concentration higher than impurity concentration of the drift layer; and a second semiconductor layer of a first conduction type or a second conduction type provided between the second principal plane of the semiconductor substrate and the first buffer layer and having impurity concentration higher than impurity concentration of the drift layer, wherein the first buffer layer incl

Abstract: N+-type source regions, low-concentration regions, and p++-type contact regions are each selectively provided in surface regions of a semiconductor substrate, at a front surface thereof, and are in contact with a source electrode. The n+-type source regions and the low-concentration regions are in contact with a gate insulating film at sidewalls of a trench and are adjacent to channel portions of a p-type base region, in a depth direction. The p++-type contact regions are disposed apart from the trench. In surface regions of an epitaxial layer constituting the p-type base region, portions left free of the n+-type source regions and the p++-type contact regions configure the low-concentration regions of an n?-type or a p?-type. The low-concentration regions are disposed periodically along the trench, between the trench and the p++-type contact regions. By the described structure, short-circuit withstand capability may be increased without increasing the number of processes.

Abstract: A power semiconductor device includes a semiconductor layer, a well region located inside the semiconductor layer and having a first conductivity type, a source region located on the well region and having a second conductivity type, a gate region in contact with a side surface of the well region and surrounding the well region, a drift region in contact with bottom surfaces of the well region and the gate region and having the second conductivity type, and a contact region located on the well region and having the first conductivity type. The drift region includes a protruding region in contact with another side surface of the well region. The power semiconductor device includes a source electrode in contact with each of the source region, the contact region, and the protruding region.

Abstract: A method for forming a semiconductor device includes forming a front side of the semiconductor device, the front side comprising a metal wire M2, and a plurality of power rails coupled to the M2. Further, the method includes forming a through silicon via (TSV) from a back side of the semiconductor device to the front side, the TSV connecting a first power rail of the front side with a metal wire M1 on the back side. Further, the method includes forming a power delivery network on the back side, the TSV providing power from the power delivery network to the front side.

Abstract: A display device includes a via pattern having a first height in a first area and a second height in a second area, wherein the second height is lower than the first height, a pixel electrode contacting the connection electrode in the second area, and a pixel defining pattern disposed on the pixel electrode and accommodated in the via pattern to overlap the second area.

Abstract: A display panel and an evaporation method for the display panel. The display panel includes: a first electrode, a second electrode and a light emitting structure layer positioned between the first electrode and the second electrode. The light emitting structure layer includes: a light emitting layer; an electron transport layer arranged on a side of the light emitting layer facing away from the first electrode, and including a plurality of doped layers that are stacked; an electron injection layer positioned on a side of the electron transport layer facing away from the light emitting layer. The electron transport layer has a reference plane positioned in the middle of the electron transport layer along the thickness direction of the display panel.