Patents Examined by Mohammad A Rahman
  • Patent number: 11127911
    Abstract: The present application discloses a display panel and method of manufacturing thereof. The display panel of the present application includes a substrate, an active switch, a color photoresist layer, a first electrode layer, a light emitting diode, a second electrode layer, an encapsulation layer and a driver circuit. The light emitting diode includes a red light emitting layer, a green light emitting layer and a blue light emitting layer which includes a silicon-germanium quantum dot material.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: September 21, 2021
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: En-Tsung Cho, Hejing Zhang
  • Patent number: 11121265
    Abstract: The present invention relates to a silicon carbide trench Schottky barrier diode using polysilicon and a method of manufacturing same. The diode has a low turn-on voltage and an improved reverse characteristic. The method includes sequentially forming an epitaxial layer, a polysilicon layer, an oxide film, and a photoresist film on a silicon carbide substrate, patterning the photoresist to form a photoresist pattern, etching the oxide film using the photoresist pattern as an etching mask to form an oxide film pattern, etching the polysilicon layer using the oxide film pattern as an etching mask to form a polysilicon pattern, removing the photoresist pattern, forming an epitaxial pattern by etching the epitaxial layer down to a predetermined depth using the oxide film pattern as an etching mask, and removing the oxide film pattern to produce a trench.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: September 14, 2021
    Inventors: O Gyun Seok, In Ho Kang, Sang Cheol Kim, Hyoung Woo Kim, Moon Kyong Na, Jeong Hyun Moon, Wook Bang
  • Patent number: 11107790
    Abstract: A laser bonding method includes forming a bonding part including an adhesive layer and a conductive particle disposed within the adhesive layer on a substrate; aligning a bonding target by disposing the bonding target on a surface of the bonding part opposite the substrate; disposing a pressing part on a surface of the bonding target that is opposite to the bonding part and pressing the bonding target onto the bonding part through the pressing part; heating the bonding target by irradiating at least the pressing part with a laser and conducting heat from the pressing part to the bonding target and from the bonding target to the bonding part; and bonding together the bonding part and the bonding target by the heat conducted from the bonding target to the bonding part so that the conductive particle electrically connects the substrate and the bonding target. The pressing part may be removed.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: August 31, 2021
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kwang-Seong Choi, Yong Sung Eom, KeonSoo Jang, Seok-Hwan Moon, Hyun-cheol Bae
  • Patent number: 11094800
    Abstract: An integrated circuit device includes: a fin-type active area including a fin top surface on a top portion and an anti-punch-through recess having a lowermost level lower than a level of the fin top surface; a nanosheet stack facing the fin top surface, the nanosheet stack including a plurality of nanosheets having vertical distances different from each other from the fin top surface; a gate structure surrounding each of the plurality of nanosheets; a source/drain region having a side wall facing at least one of the plurality of nanosheets; and an anti-punch-through semiconductor layer including a first portion filling the anti-punch-through recess, and a second portion being in contact with a side wall of a first nanosheet most adjacent to the fin-type active area among the plurality of nanosheets, the anti-punch-through semiconductor layer including a material different from a material of the source/drain region.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: August 17, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nak-jin Son, Dong-il Bae
  • Patent number: 11094640
    Abstract: A package module includes a core structure including a frame having a penetrating portion, an electronic component disposed in the penetrating portion, and an insulating material covering at least a portion of each of the frame and the electronic component and filling at least a portion of the penetrating portion. The core structure further has a recessed portion in which a stopper layer is disposed on a bottom surface of the recessed portion. A semiconductor chip has a connection pad and is disposed in the recessed portion such that an inactive surface faces the stopper layer. An encapsulant covers at least a portion of each of the core structure and the semiconductor chip, and fills at least a portion of the recessed portion. An interconnect structure is disposed on the core structure and an active surface of the semiconductor chip, and includes a redistribution layer.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: August 17, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangkyu Lee, Shanghoon Seo, Jeongho Lee
  • Patent number: 11094845
    Abstract: A method of producing light-emitting diode chips includes A) and C)-F) in order: A) providing a growth substrate, C) producing a structural layer, the structural layer including Alx1Ga1-x1-y1Iny1N, where-in y1?0.5, and a plurality of structural elements with a mean height of at least 50 nm so that a side of the structural layer facing away from the growth substrate is rough, D) producing a cover layer on the structural layer, the cover layer forming the structural layer true to shape and including Alx2Ga1-x2-y2Iny2N, wherein x2?0.6, E) producing a planarization layer on the cover layer, a side of the finished planarization layer is flat and the planarization layer includes Alx3Ga1-x3-y3Iny3N, wherein x3+y3?0.2, and F) growing a functional layer sequence that generates radiation on the planarization layer.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 17, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Massimo Drago, Alexander Frey, Joachim Hertkorn
  • Patent number: 11088146
    Abstract: An embedded dynamic random-access memory cell includes a wordline to supply a gate signal, a selector thin-film transistor (TFT) above the wordline and that includes an active layer and is configured to control transfer of a memory state of the memory cell between a first region and a second region of the active layer in response to the gate signal, a bitline to transfer the memory state and coupled to and above the first region of the active layer, a storage node coupled to and above the second region of the active layer, and a metal-insulator-metal capacitor coupled to and above the storage node and configured to store the memory state. In an embodiment, the wordline is formed in a back end of line process for interconnecting logic devices formed in a front end of line process below the wordline, and the selector TFT is formed in a thin-film process.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: August 10, 2021
    Assignee: Intel Corporation
    Inventor: Yih Wang
  • Patent number: 11075269
    Abstract: A semiconductor device, includes a channel region, and a source/drain region adjacent to the channel region. The source/drain region includes a first epitaxial layer, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and the first epitaxial layer is made of SiAs.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Ting Tsai, Chung-Wei Hung, Jung-Ting Chen, Ying-Hua Lai, Song-Bor Lee, Bor-Zen Tien
  • Patent number: 11069597
    Abstract: Semiconductor chips and methods of manufacturing the same are provided. The semiconductor chip includes a substrate, an interlayer insulation layer including a bottom interlayer insulation layer on an upper surface of the substrate and a top interlayer insulation layer on the bottom interlayer insulation layer, an etch stop layer between the bottom interlayer insulation layer and the top interlayer insulation layer, a landing pad on the interlayer insulation layer, and a through via connected to the landing pad through the substrate, the interlayer insulation layer, and the etch stop layer. The etch stop layer is isolated from direct contact with the landing pad.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-suk Lee, Hak-seung Lee, Dong-chan Lim, Tae-seong Kim, Kwang-jin Moon
  • Patent number: 11059717
    Abstract: A micromechanical pressure sensor, having a sensor core formed in a silicon substrate in a pressure-sensitive region, having a sensor membrane, a first cavity being formed in the silicon substrate on the sensor membrane; a second cavity formed between a rear-side surface of the silicon substrate and the sensor core, access holes that go out from the rear-side surface of the silicon substrate being connected to the second cavity; and at least one anchoring recess going out from the rear-side surface being formed in an anchoring region of the silicon substrate surrounding the pressure-sensitive region, the anchoring recess being formed such that a molding compound can flow into the anchoring recess.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: July 13, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Arne Dannenberg, Tobias Henn
  • Patent number: 11056588
    Abstract: A method for fabricating a vertical transistor device includes forming a plurality of fins on a substrate. The method further includes forming an interlevel dielectric layer on the substrate and sidewalls of each of the fins. The method further includes selectively removing the interlevel dielectric layer between adjacent fins. The method further includes laterally recessing a portion of the substrate between the adjacent fins to form a bottom source/drain cavity exposing a bottom portion of each fin and extending beyond each fin. The method further includes epitaxially growing an epitaxial growth material from the substrate and filling the bottom source/drain cavity.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Heng Wu, Gen Tsutsui, Lan Yu, Ruilong Xie
  • Patent number: 11040870
    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Sung Chang, Chun-Wen Cheng, Fei-Lung Lai, Shing-Chyang Pan, Yuan-Chih Hsieh, Yi-Ren Wang
  • Patent number: 11037931
    Abstract: The instant disclosure discloses method comprising receiving a substrate; disposing a dielectric layer over the substrate; disposing a metallic material on the dielectric layer; disposing a passivation layer on top surface of the metallic material; and performing an alloy layer formation process to dispose a SiGe layer across top surface of the passivation layer.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: June 15, 2021
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Keewoung Choi, Hasung Lee, Sung-Ki Kim
  • Patent number: 11024659
    Abstract: An image sensor and a method of fabricating an image sensor are provided, the image sensor including a plurality of color filters spaced apart from each other on a semiconductor substrate; a protective layer covering sidewalls of the color filters and top surfaces of the color filters; and a low-refractive pattern filling a space between the color filters.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: June 1, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaesung Hur, Youngtak Kim, Hajin Lim
  • Patent number: 11018278
    Abstract: A semiconductor body is disclosed. In an embodiment a semiconductor body includes a p-doped region, an active region, an intermediate layer and a layer stack containing indium, wherein an indium concentration in the layer stack changes along a stacking direction, wherein the layer stack is formed with exactly one nitride compound semiconductor material apart from dopants, wherein the intermediate layer is nominally free of indium, arranged between the layer stack and the active region, and directly adjoins the layer stack, wherein the intermediate layer and/or the layer stack are n-doped at least in places, wherein a dopant concentration of the layer stack is at least 5*1017 1/cm3 and at most 2*1018 1/cm3, and wherein a dopant concentration of the intermediate layer is at least 2*1018 1/cm3 and at most 3*1019 1/cm3.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: May 25, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Joachim Hertkorn, Marcus Eichfelder
  • Patent number: 11018222
    Abstract: Disclosed herein are structures, methods, and assemblies related to metallization in integrated circuit (IC) structures. For example, in some embodiments, an IC structure may include a first nanowire in a metal region and a second nanowire in the metal region. A distance between the first nanowire and the second nanowire may be less than 5 nanometers, and the metal region may include tungsten between the first nanowire and the second nanowire.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Daniel B. O'Brien, Christopher J. Wiegand, Lukas M. Baumgartel, Oleg Golonzka, Dan S. Lavric, Daniel B. Bergstrom, Jeffrey S. Leib, Timothy Michael Duffy, Dax M. Crum
  • Patent number: 11018130
    Abstract: An integrated circuit (IC) die is provided, which includes a die body; electrostatic discharge (ESD) circuitry formed in the die body; contact pads exposed on an active side of the die body; a first conductive tower formed in the die body and electrically coupling a first contact pad to the ESD circuitry. The first conductive tower comprises first, second, third, and fourth segments formed from metal layers of the die body; a first via electrically coupling the first segment to the second segment; a second via electrically coupling the first segment to the third segment; a third via electrically coupling the second segment to the fourth segment; and a fourth via electrically coupling the third segment to the fourth segment, the second segment electrically parallel with the third segment. The IC die further comprises at least a first data line disposed between the first, second, third, and fourth segments.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: May 25, 2021
    Assignee: XILINX, INC.
    Inventor: Mohammed Fakhruddin
  • Patent number: 11011707
    Abstract: The organic EL display device includes at least a transparent electrode, an organic EL layer, and a non-transparent electrode in this order and further includes a black insulating layer, and the non-transparent electrode has a reflectance of 25%±20%.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: May 18, 2021
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Takeshi Arai, Kazuto Miyoshi
  • Patent number: 11011391
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a substrate; forming a silicon layer on the substrate, wherein an edge region of the top surface of the substrate is exposed from the silicon layer; epitaxially growing a GaN-based semiconductor material on the silicon layer and the substrate to form a GaN-based semiconductor layer on the silicon layer and a plurality of GaN-based nodules on the edge region of the top surface of the substrate; and performing a first dry etch step to remove the GaN-based nodules, wherein performing the first dry etch step includes applying a first bias power that is equal to or higher than 1500 W.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: May 18, 2021
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yung-Fong Lin, Yu-Chieh Chou
  • Patent number: 10985155
    Abstract: An embedded NMOS triggered silicon controlled rectification device includes a P-type substrate, at least one rectifying zone, and at least one trigger. The rectifying zone includes a first N-type heavily doped area, an N-type well, and a first P-type heavily doped area. Alternatively, the device includes an N-type substrate, a first P-type well, at least one rectifying zone, and at least one trigger. The rectifying zone includes a second P-type well, a first N-type heavily doped area, and a first P-type heavily doped area. The trigger cooperates with the P-type substrate or the first P-type well to form at least one NMOSFET. The trigger is independent to the rectifying zone. The first P-type heavily doped area is arranged between the trigger and the first N-type heavily doped area.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: April 20, 2021
    Assignee: Amazing Microelectronic Corp.
    Inventors: Kun-Hsien Lin, Zi-Ping Chen, Che-Hao Chuang, Tun-Chih Yang