Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

Abstract: Discussed are a light-emitting device and a light-emitting display device having improved efficiency and increased lifespan. A plurality of stacks is provided between an anode and a cathode for at least a subpixel to emit a predetermined color, and emissive layers in different stacks include the same color-based materials having different luminous properties.

Abstract: The first region (RG1) contains a first organic material and a metal compound (a compound containing a metal element). The second region (RG2) contains the first organic material and the metal compound. The average intensity of the SIMS profile of the metal element in the second region (RG2) can be lower than the average intensity of the SIMS profile of the metal element in the first region (RG1). Specifically, the average intensity of the SIMS profile of the metal element in the second region (RG2) can be lower than 10%, preferably lower than 1.0%, of the average intensity of the SIMS profile of the metal element in the first region (RG1).

Abstract: Some embodiments include apparatuses and methods operating the apparatuses. One of the apparatuses includes a first data line located over a substrate, a second data line located over the first data line, a third data line located over the second data line and electrically separated from the first and second data lines, and a memory cell coupled to the first, second, and third data lines. The memory cell includes a first material between the first and second data lines and electrically coupled to the first and second data lines; a second material located over the first data line and the first material, the second material electrically separated from the first material and electrically coupled to the third data line; and a memory element electrically coupled to the second material and electrically separated from the first material and first and second data lines.

Abstract: Disclosed are a white organic light emitting element, which may uniformize the color coordinates of white regardless of a change in current density by changing the configuration of different kinds of light emitting layers contacting each other, and a display device using the same.

Abstract: Capacitor comprising: a first porous semiconductor having an average pore size of between 20 nm and 200 nm and preferably between 40 nm and 100 nm, at least one second electric conductor, wherein the second electric conductor infiltrates the porous structure, and the materials involved are selected such that a potential barrier is formed between the first porous semiconductor and the second conductor, without applying an external voltage, as a result of the diffusion of charge carriers, which is preferably more than 0.5 V, more preferably more than 0.7 V, more preferably more than 1 V, and more preferably still more than 1.4 V, wherein a dielectric layer having a thickness of 1 nm to 10 nm is preferably arranged between the first porous semiconductor and the second electric conductor.

Abstract: Exemplary deposition methods may include delivering a boron-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the boron-containing precursor and the nitrogen-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either of the boron-containing precursor or the nitrogen-containing precursor may be greater than or about 2:1. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a boron-and-nitrogen material on a substrate disposed within the processing region of the semiconductor processing chamber.

Abstract: Integrated circuit structures having source or drain structures with vertical trenches are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The epitaxial structures of the first and second source or drain structures have a vertical trench centered therein. The first and second source or drain structures include silicon and a Group V dopant impurity.

Abstract: A semiconductor device includes a gate structure on a substrate and a dielectric film stack over the gate structure and the substrate, where the dielectric film stack includes a first inter layer dielectric (ILD) over the substrate and the gate structure, a barrier layer over the first ILD, a second ILD over the barrier layer, and a contact extending through the dielectric film stack. An upper portion of a contact sidewall has a first slope, a lower portion of the contact sidewall has a second slope different from the first slope, and a transition from the first slope to the second slope occurs at a portion of the contact extending through the barrier layer.

Abstract: Organic luminescent material, includes: host material, TADF sensitizer, and fluorescent-luminescent material; wherein absolute value of difference between LUMO level of the host material and LUMO level of the TADF sensitizer is not more than 0.4 eV, and absolute-value of difference between HOMO level of the host material and HOMO level of the TADF sensitizer is not more than 0.4 eV; absolute-value of LUMO level of the fluorescent-luminescent material is not more than absolute-value of the LUMO level of the host material and the LUMO level of the TADF sensitizer, and/or absolute-value of HOMO level of the fluorescent-luminescent material is not less than an absolute-value of the HOMO level of the host material and absolute-value of the HOMO level of the TADF sensitizer; and emission-spectrum of the host material overlaps an absorption-spectrum of the TADF sensitizer, and emission-spectrum of the TADF sensitizer overlaps absorption-spectrum of the fluorescent-luminescent material.

Abstract: A field-effect transistor includes a Ga2O3-based semiconductor layer, a source region and a drain region that are formed inside the Ga2O3-based semiconductor layer, a gate electrode that is formed, via a gate insulating film, on a channel region as the Ga2O3-based semiconductor layer between the source region and the drain region, a source electrode connected to the source region, and a drain electrode connected to the drain region. An interface charge including a negative charge is formed between the gate electrode and the channel region, and a gate threshold voltage is not less than 4.5V.

Abstract: A conductive via layer is deposited on a bottom electrode, then patterned and trimmed to form a sub 20 nm conductive via on the bottom electrode. The conductive via is encapsulated with a first dielectric layer, which is planarized to expose a top surface of the conductive via. A MTJ stack is deposited on the encapsulated conductive via wherein the MTJ stack comprises at least a pinned layer, a barrier layer, and a free layer. A top electrode layer is deposited on the MTJ stack and patterned and trimmed to form a sub 30 nm hard mask. The MTJ stack is etched using the hard mask to form an MTJ device and over etched into the encapsulation layer but not into the bottom electrode wherein metal re-deposition material is formed on sidewalls of the encapsulation layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.

Abstract: A method of forming ferroelectric hafnium oxide (HfO2) in a substrate processing system includes depositing an HfO2 layer on a substrate, depositing a hafnium nitride (HfN) layer on the HfO2 layer; and annealing the HfO2 layer and the HfN layer to form ferroelectric hafnium HfO2.

Abstract: There is included providing a substrate in a process chamber; and forming a film on the substrate in the process chamber by supplying an inert gas from a first supplier, supplying a first processing gas from a second supplier, and supplying an inert gas from a third supplier to the substrate, the third supplier being installed at an opposite side of the first supplier with respect to a straight line that passes through the second supplier and a center of the substrate and is interposed between the first supplier and the third supplier, to the substrate, wherein in the film, a substrate in-plane film thickness distribution of the film is adjusted by controlling a balance between a flow rate of the inert gas supplied from the first supplier and a flow rate of the inert gas supplied from the third supplier.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.

Abstract: A method of forming ferroelectric hafnium oxide (HfO2) in a substrate processing system includes depositing an HfO2 layer on a substrate, depositing a capping layer on the HfO2 layer, annealing the HfO2 layer and the capping layer to form ferroelectric hafnium HfO2, and selectively etching the capping layer to remove the capping layer without removing the HfO2 layer.

Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.

Abstract: Disclosed are a light-emitting device and a display device including the same. An emissive layer is formed so as to have a dual-layer structure, the triplet energy level of a dopant of a first emissive layer adjacent to a hole transport layer is greater than the triplet energy level of a first host in the first emissive layer, and the triplet energy level of the first host is greater than the triplet energy level of a second host of a second emissive layer, whereby triplet excitons generated in the first emissive layer are recycled to the second emissive layer so as to be reused for light emission.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate, wherein the semiconductor fin includes a channel region and a source/drain region; a gate structure disposed over the channel region of the semiconductor fin, wherein the gate structure includes a gate spacer and a gate stack; a source/drain structure disposed over the source/drain region of the semiconductor fin; and a fin top hard mask vertically interposed between the gate spacer and the semiconductor fin, wherein the fin top hard mask includes a dielectric layer, and wherein a sidewall of the fin top hard mask directly contacts the gate stack, and another sidewall of the fin top hard mask directly contacts the source/drain structure.

Abstract: A method includes forming an assembly of layers including an InP cap layer on an InGaAs absorption region layer, wherein the InGaAs layer is on an n-InP layer, and wherein an underlying substrate layer underlies the n-InP layer. The method includes removing a portion of the InP cap and n-InP layer by dry etching.