Patents Examined by Mohammad T. Karimy
-
Patent number: 8330253Abstract: The present invention provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.Type: GrantFiled: April 22, 2008Date of Patent: December 11, 2012Assignee: Renesas Electronics CorporationInventor: Kazuo Tomita
-
Patent number: 8294175Abstract: A light-emitting device includes: a semiconductor layer including a first conductive contact layer, a first conductive cladding layer, an active layer, a second conductive cladding layer, a second conductive contact layer and a resin block layer in this order; a first electrode in contact with the first conductive contact layer; and a second electrode in contact with the second conductive contact layer. The second conductive contact layer includes a first opening at least in a region facing the first electrode. Moreover, the resin block layer includes a plurality of second openings communicated with the first opening, and the first opening has an air gap.Type: GrantFiled: January 5, 2011Date of Patent: October 23, 2012Assignee: Sony CorporationInventor: Kensuke Kojima
-
Patent number: 8294236Abstract: A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved.Type: GrantFiled: November 15, 2010Date of Patent: October 23, 2012Assignee: Renesas Electronics CorporationInventors: Noriyuki Mitsuhira, Takehiko Nakahara, Yasusuke Suzuki, Jun Sumino
-
Patent number: 8284955Abstract: The present invention provides methods and systems for digitally processing audio signals. Some embodiments receive an audio signal and converting it to a digital signal. The gain of the digital signal may be adjusted a first time, using a digital processing device located between a receiver and a driver circuit. The adjusted signal can be filtered with a first low shelf filter. The systems and methods may compress the filtered signal with a first compressor, process the signal with a graphic equalizer, and compress the processed signal with a second compressor. The gain of the compressed signal can be adjusted a second time. These may be done using the digital processing device. The signal may then be output through an amplifier and driver circuit to drive a personal audio listening device. In some embodiments, the systems and methods described herein may be part of the personal audio listening device.Type: GrantFiled: October 31, 2008Date of Patent: October 9, 2012Assignee: Bongiovi Acoustics LLCInventors: Anthony Bonglovi, Phillip Fuller, Glenn Zelniker
-
Patent number: 8264079Abstract: While bumps formed on pads of a semiconductor chip and a board having a sheet-like seal-bonding resin stuck on its surface are set face to face, the bumps and the board are pressed to each other with a tool, thereby forming a semiconductor chip mounted structure in which the seal-bonding resin is filled between the semiconductor chip and the board and in which the pads of the semiconductor chip and the electrodes of the board are connected to each other via the bumps, respectively. Entire side faces at corner portions of the semiconductor chip are covered with the seal-bonding resin. Therefore, loads generated at the corner portions due to board flexures for thermal expansion and contraction differences among the individual members caused by heating and cooling during mounting as well as for mechanical loads after mounting so that internal breakdown of the semiconductor chip can be avoided.Type: GrantFiled: June 26, 2008Date of Patent: September 11, 2012Assignee: Panasonic CorporationInventors: Teppei Iwase, Yoshihiro Tomura, Kazuhiro Nobori, Yuichiro Yamada, Kentaro Kumazawa
-
Patent number: 8252637Abstract: The purpose of the present invention is to provide a reliable semiconductor device comprising TFTs having a large area integrated circuit with low wiring resistance. One of the features of the present invention is that an LDD region including a region which overlaps with a gate electrode and a region which does not overlap with the gate electrode is provided in one TFT. Another feature of the present invention is that gate electrode comprises a first conductive layer and a second conductive layer and portion of the gate wiring has a clad structure comprising the first conductive layer and the second conductive layer with a low resistance layer interposed therebetween.Type: GrantFiled: May 26, 2011Date of Patent: August 28, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama
-
Patent number: 8242601Abstract: The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.Type: GrantFiled: May 13, 2009Date of Patent: August 14, 2012Assignee: Megica CorporationInventors: Chiu-Ming Chou, Chien-Kang Chou, Ching-San Lin, Mou-Shiung Lin
-
Patent number: 8227797Abstract: A transparent display apparatus is provided that is constructed to transmit or block a light of images selectively according to a supply of electric power to a conventional transparent organic light emitting diode. The transparent display apparatus includes a transparent organic light emitting diode having a glass substrate, a transparent anode, a hole transport layer, an emitting layer, an electron transport layer and a transparent cathode. The transparent display apparatus includes an insulating layer stacked on the transparent cathode, and first and second transparent ITOs stacked on the insulating layer to deliver electromotive force onto an entire surface and to transmit or block the light of images according to the on/off state of a power source. The transparent display apparatus also includes an electro chromic layer provided between the first and the second transparent ITOs and including transparent and colorless chemicals.Type: GrantFiled: June 29, 2009Date of Patent: July 24, 2012Assignee: Samsung Electronics Co., LtdInventor: Ho-Seong Seo
-
Patent number: 8227900Abstract: The present invention provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.Type: GrantFiled: April 22, 2008Date of Patent: July 24, 2012Assignee: Renesas Electronics CorporationInventor: Kazuo Tomita
-
Patent number: 8229136Abstract: The present invention provides for methods and systems for digitally processing audio signals by adjusting the gain of a signal a first time, using a digital processing device located between a radio head unit and a speaker. The methods and systems may filter the adjusted signal with a first low shelf filter, compress the filtered signal with a first compressor, process the signal with a graphic equalizer, compress the processed signal with a second compressor and adjust the gain of the compressed signal a second time. The methods and systems may also filter the signal received from the first low shelf filter with a first high shelf filter prior to compressing the filtered signal with the first compressor. The signal may be filtered with a second low shelf filter prior to processing the signal with the graphic equalizer. Some embodiments filter the signal with a second high shelf filter after the signal is filtered with the second low shelf filter.Type: GrantFiled: August 25, 2008Date of Patent: July 24, 2012Inventors: Anthony Bongiovi, Phillip Fuller, Glenn Zelniker
-
Patent number: 8227832Abstract: The present invention provides a multi-finger structure of a SiGe heterojunction bipolar transistor (HBT). It is consisted of plural SiGe HBT single cells. The multi-finger structure is in a form of C/BEBC/BEBC/.../C, wherein, C, B, E respectively stands for collector, base and emitter; CBEBC stands for a SiGe HBT single cell. The collector region is consisted of an n type ion implanted layer inside the active region. The bottom of the implanted layer is connected to two n type pseudo buried layers. The two pseudo buried layers are formed through implantation to the bottom of the shallow trenches that surround the collector active region. Two collectors are picked up by deep trench contact through the field oxide above the two pseudo buried layers. The present invention can reduce junction capacitance, decrease collector electrode output resistance, and improve device frequency characteristics.Type: GrantFiled: December 17, 2010Date of Patent: July 24, 2012Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.Inventors: Tzuyin Chiu, Zhengliang Zhou, Xiongbin Chen
-
Patent number: 8222718Abstract: A semiconductor die package. The semiconductor die package includes a premolded clip structure assembly having a clip structure, a semiconductor die attached to the clip structure, and a first molding material covering at least a portion of the clip structure and the semiconductor die. The semiconductor die package also includes a leadframe structure having a die attach pad, where the leadframe structure is attached to premolded clip structure assembly.Type: GrantFiled: February 5, 2009Date of Patent: July 17, 2012Assignee: Fairchild Semiconductor CorporationInventors: Armand Vincent C. Jereza, Paul Armand Calo, Erwin Victor R. Cruz
-
Patent number: 8223992Abstract: A speaker array apparatus includes a speaker array that emits sounds of a plurality of channels, a beam formation calculating section that performs a calculation for controlling phases of the sounds so that the speaker array emits sound beams in directions set for the respective channels, a sound source localization applying section that performs a calculation for controlling the phases of the sounds emitted from the speaker array so as to form a plurality of virtual point sound sources, and performs a calculation of auditory sensation characteristics at a listening position on a basis of a head-related transfer function, a selecting section that selects one of the beam formation calculating section and the sound source localization applying section, and a phase controlling section that controls the phases of the sounds emitted from the speaker array on a basis of a calculation result of the beam formation calculation section which is selected by the selecting section or applies the auditory sensation charactType: GrantFiled: July 3, 2008Date of Patent: July 17, 2012Assignee: Yamaha CorporationInventors: Koji Suzuki, Yusuke Konagai
-
Patent number: 8217474Abstract: A hermetic microelectromechanical system (MEMS) package includes a CMOS MEMS chip and a second substrate. The CMOS MEMS Chip has a first substrate, a structural dielectric layer, a CMOS circuit and a MEMS structure. The structural dielectric layer is disposed on a first side of the first structural substrate. The structural dielectric layer has an interconnect structure for electrical interconnection and also has a protection structure layer. The first structural substrate has at least a hole. The hole is under the protection structure layer to form at least a chamber. The chamber is exposed to the environment in the second side of the first structural substrate. The chamber also comprises a MEMS structure. The second substrate is adhered to a second side of the first substrate over the chamber to form a hermetic space and the MEMS structure is within the space.Type: GrantFiled: December 28, 2009Date of Patent: July 10, 2012Assignee: Solid State System Co., Ltd.Inventors: Chien-Hsing Lee, Tsung-Min Hsieh, Jhyy-Cheng Liou
-
Patent number: 8217483Abstract: A semiconductor component that includes a photosensitive doped semiconductor layer, in which electrical charge carriers are released during absorption of electromagnetic radiation is disclosed. The photosensitive semiconductor layer has a structured interface and at least one layer which generates an electric field for separating the released charge carriers disposed downstream of the structured interface. The electric field extends over the structured interface. The photosensitive semiconductor component is distinguished by a high efficiency of the charge carrier separation, in particular, for generating an electric current.Type: GrantFiled: November 24, 2009Date of Patent: July 10, 2012Assignee: Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung E. V.Inventors: Kevin Fuechsel, Andreas Tuennermann, Ernst-Bernhard Kley
-
Patent number: 8217443Abstract: A semiconductor device includes a semiconductor layer having a trench; a source region formed in a surface layer portion thereof adjacently to a first side of the trench; a drain region formed in the surface layer portion adjacently to a second side of the trench; a first insulating film formed in the trench; a floating gate stacked on the first insulating film and opposed to the trench, and extending over and covering only partially the source and drain regions; a second insulating film formed on the floating gate; and a control gate at least partially embedded in the trench so that a portion embedded in the trench is opposed to the floating gate through the second insulating film. The first insulating film has a thin portion in contact with the drain region and a thick portion formed by the remainder thereof which covers the entire bottom surface of the trench.Type: GrantFiled: May 21, 2009Date of Patent: July 10, 2012Assignee: Rohm Co., Ltd.Inventor: Naoki Izumi
-
Patent number: 8218791Abstract: A disclosed set top box or other type of multimedia handling device (MHD) is configured to support a toggle volume feature that enables the end user to toggle between two or more substantially different audible volume settings using a single push of a single remote control button or other type of control, e.g., a touch screen control. In some embodiments, the MHD includes a processor, storage media accessible to and readable by the processor, a remote control interface in communication with the processor, a multimedia decoder, and an audio digital-to-analog converter. The remote control interface receives input from a remote control device. The multimedia decoder module receives and processes multimedia streams. The decoder generates a decoder audio output and a decoder video output. The DAC processes the decoder audio output and produces an audio signal having a particular volume level.Type: GrantFiled: June 20, 2008Date of Patent: July 10, 2012Assignee: AT&T Intellectual Property I, L.P.Inventors: Steven M. Wollmershauser, William Averill, William O. Sprague, Jr.
-
Patent number: 8217467Abstract: In some embodiments, a semiconductor memory device includes a substrate that includes a cell array region and a peripheral circuit region. The semiconductor memory device further includes a device isolation pattern on the substrate. The device isolation pattern defines a first active region and a second active region within the cell array region and a third active region in the peripheral circuit region. The semiconductor memory device further includes a first common source region, a plurality of first source/drain regions, and a first drain region in the first active region. The semiconductor memory device further includes a second common source region, a plurality of second source/drain regions, and a second drain region in the second active region. The semiconductor memory device further includes a third source/drain region in the third active region. The semiconductor memory device further includes a common source line contacting the first and second common source regions.Type: GrantFiled: January 5, 2011Date of Patent: July 10, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Sun Sel, Jung-Dal Choi, Choong-Ho Lee, Ju-Hyuck Chung, Hee-Soo Kang, Dong-uk Choi
-
Patent number: 8207561Abstract: The present invention uses an image pickup device comprising a plurality of pixels respectively including a photoelectric conversion unit for converting incoming light into a signal charge, an amplifying unit for amplifying the signal charge generated by the photoelectric conversion unit and a transfer unit for transferring the signal charge from the photoelectric conversion unit to the amplifying unit, in which the photoelectric conversion unit is formed of a first-conductivity-type first semiconductor region and a second-conductivity-type second semiconductor region and a second-conductivity-type third semiconductor region is formed on at least a part of the gap between a photoelectric conversion unit of a first pixel and a photoelectric conversion unit of a second pixel adjacent to the first pixel, a first-conductivity-type fourth semiconductor region having an impurity concentration higher than that of the first semiconductor region is formed between the photoelectric conversion unit and the third semiconType: GrantFiled: March 21, 2011Date of Patent: June 26, 2012Assignee: Canon Kabushiki KaishaInventors: Toru Koizumi, Seiichiro Sakai, Masanori Ogura
-
Patent number: 8204257Abstract: A method for increasing ring tone volume is provided. The method includes steps of: reading an audio file which is set as a current ring tone; determining whether the ring tone is a MP3 audio file or a musical instrument digital interface (MIDI) audio file; adjusting frequencies by using an equalizer technique to increase volume of the ring tone if the ring tone is the MP3 audio file; adjusting a volume level of the ring tone to be the highest volume level, and adjusting timbre of the ring tone to increase the ring tone volume by simulating a musical score of the ring tone by using different instruments if the ring tone is the MIDI audio file. A related system is also provided.Type: GrantFiled: June 27, 2008Date of Patent: June 19, 2012Assignee: Chi Mei Communications Systems, Inc.Inventor: Meng-Chun Chen