Abstract: A blender using different charging modes with wireless charging is disclosed. Exemplary implementations may include a base assembly, a container assembly, an electrical motor, a blending component, a control interface, blending control circuitry, charging control circuitry, and/or other components. The base component may include a rechargeable battery and a wireless charging interface. The charging control circuitry may be configured to make different types of detections related to the availability and/or usage of electrical power and related to the usage and alignment of the wireless charging interface with an external charging structure. The charging control circuitry may conduct electrical power to the rechargeable battery using at least two different charging modes, thus providing different amounts of electrical power to the rechargeable battery in different charging modes.

Abstract: A computer-implemented method and system for determining a wiring network in a multi-core processor. The method includes determining, using a layered-and-progressive determination model, a wiring network including wiring path(s) for operably connecting multiple processor cores in the multi-core processor. The method also includes outputting a layout of the determined wiring network for display. The layered-and-progressive determination model is arranged to model the plurality of processor cores as a mesh of nodes arranged in the form of a rectangular array with n rows and m columns. Nested layer(s) are identified from the rectangular array. Each of the nested layers is formed by respective plurality of nodes connected in respective rectangular paths of the same shape but different sizes. A respective rectangular wiring path for each of the nested layer(s) is determined. The respective rectangular wiring paths are of the same shape but different sizes.

Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kth difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.

Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial of degree k in a sub-function p over a set of values of p, k being an integer greater than or equal to one. The methods include: verifying that an instantiation of the hardware design correctly evaluates the sub-function p; formally verifying that an instantiation of the hardware design implements a function that is polynomial of degree k in p by formally verifying that, for all values of p in the set of values of p, an instantiation of the hardware design has a constant kth difference; and verifying that an instantiation of the hardware design generates an expected output in response to each of at least e different values of p in the set of values of p, wherein e is equal to k when a value of the kth difference is predetermined and e is equal to k+1 when the value of the kth difference is not predetermined.

Abstract: A logic circuit (for providing a multibit flip-flop (MBFF) function) includes: a first inverter to receive a clock signal and generate a corresponding clock_bar signal; a second inverter to receive the clock_bar signal and generate a corresponding clock_bar_bar signal; a third inverter to receive a control signal and generate a corresponding control_bar signal; and a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each including: a NAND circuit to receive data signals; and a 1-bit transmit gate flip-flop (TGFF) circuit to output signals Q and q, and receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar and clock_bar_bar signals, and the control and control_bar signals; and the first transfer TXFF circuit in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.

Abstract: A transmission gate structure includes first and second PMOS transistors positioned in a first active area, first and second NMOS transistors positioned in a second active area parallel to the first active area, and four metal segments parallel to the active areas. A first metal segment overlies the first active area, a fourth metal segment overlies the second active area, and second and third metal segments are a total of two metal segments positioned between the first and fourth metal segments. A first conductive path connects gates of the first PMOS and NMOS transistors, a second conductive path connects gates of the second PMOS and NMOS transistors, a third conductive path connects a source/drain (S/D) terminal of each of the first and second PMOS transistors and first and second NMOS transistors and includes a first conductive segment extending across at least three of the four metal segments.

Abstract: Disclosed herein are battery management systems and methods for activating battery override logic for a battery management system to provide a power path to a battery pack. A method of activating battery override logic for a battery management system may comprise detecting a predetermined key toggle sequence performed in a predetermined amount of time or detecting an override message received from a CAN bus. The method may further comprise determining if the last override turn-on sequence was requested more than a predetermined amount of time ago, confirming that the override is configured for the contactor, and turning on the contactor to provide a power path to the battery pack for a limited predetermined amount of time. An exemplary predetermined toggle sequence may comprise on-off-on-off-on performed within 10 seconds. An exemplary override message from the CAN bus may be initiated by a user having a key, code, or access card.

Abstract: Techniques and a system to facilitate estimation of a quantum phase, and more specifically, to facilitate estimation of an expectation value of a quantum state, by utilizing a hybrid of quantum and classical methods are provided. In one example, a system is provided. The system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can include an encoding component and a learning component. The encoding component can encode an expectation value associated with a quantum state. The learning component can utilize stochastic inference to determine the expectation value based on an uncollapsed eigenvalue pair.

Abstract: A control system is configured to control a power adjustment resource including an energy storage device configured to electrically connect to a power network, and a temperature control device configured to perform temperature control of the energy storage device. The control system includes: a first control device configured to control charging and discharging of the energy storage device; a second control device configured to control the temperature control device; and a third control device. The second control device is configured to select either external power or stored power and drives the temperature control device using the selected power. The third control device is configured to determine whether to permit power supply from the power network to the power adjustment resource based on supply and demand information of the power network, and switch between permission and prohibition of the power supply.

Abstract: Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

Abstract: Methods, systems and media for simulating or analyzing voltage drops in a power distribution network can use an incremental approach to define a portion of a design around a victim to capture a sufficient collection of aggressors that cause appreciable voltage drop on the victim, and then an incremental simulation of just the portion can be performed rather than computing simulated voltage drops across the entire design. This approach can be both computationally efficient and can limit the size of the data used in simulating dynamic voltage drops in the power distribution network. Multiple different portions can be simulated separately in separate processing cores or elements. In one embodiment, a system can provide options of user selected constraints for the simulation to provide better accuracy or use less memory. Better accuracy will normally use a larger set of aggressors for each victim at the expense of using more memory.

Abstract: A method for providing an IC design is disclosed. The method includes receiving and synthesizing a behavioral description of an IC design; generating, based on the synthesized behavioral description, a layout for the IC design; performing at least a timing analysis on the layout; accessing, based on the timing analysis, a first cell library including a plurality of transistor-based cells, each having one or more transistors and associated with a respective first delay value; accessing, based on the timing analysis, a second cell library including a plurality of non-transistor-based cells, each having no transistor and associated with a respective second delay value; and updating the layout by at least one of inserting one or more of the plurality of transistor-based cells or inserting one or more of the plurality of non-transistor-based cells.

Abstract: A method for operating a charging station for vehicles may include suppling the charging station with electric energy via a multiple phase supply system, providing, by the charging station, multiple phase lines for an electric power supply of vehicles, supplying a vehicle a charging current via a phase line, measuring at least one supply system voltage that is present on the phase line that supplies the vehicle with the charging current, comparing the measured at least one supply system voltage and a stored rated voltage range, and adjusting the charging current if the measured at least one supply system voltage is outside the stored rated voltage range.

Abstract: A graph-based timing analysis (GBA) is applied to a circuit design that includes a routed gate-level netlist to produce timing estimates of the circuit design. A machine learning (ML) model is applied to modify these GBA timing estimates of the circuit design to make them more accurate. For example, the ML model may be trained using timing estimates from path-based timing analysis as the ground truth, and using features of the circuit design from the GBA as input to the ML model.

Abstract: In general, embodiments of the present disclosure provide methods, apparatus, systems, computer program products, computing devices, computing entities, and/or the like for altering a design of a hardware intellectual property (IP). In accordance with various embodiments, a representation of the design of the hardware IP is converted to generate a control and data flow graph (CDFG) for the design. An entropy analysis of the CDFG is conducted to identify one or more control paths and/or data paths for removal. Responsive to identifying control path(s) for removal, control logic for the control path(s) is removed from the design and replaced with first reconfigurable logic. Responsive to identifying data path(s) for removal, datapath logic for the data path(s) is removed from the design and replaced with second reconfigurable logic. Logic synthesis is then performed on the design, along with verification to check functional correctness of the design of the hardware.

Abstract: A simulation analysis system for dioxin concentration in furnace of municipal solid waste incineration process includes an area division module, the area division module is connected with a numerical simulation module, the numerical simulation module is connected with a single-factor analysis module, the single-factor analysis module includes an orthogonal test analysis module, and the orthogonal test analysis module is connected with a control module; the area division module is used for dividing areas in the incinerator, the numerical simulation module is used for conducting modeling simulation on the divided areas, the single-factor analysis module is used for conducting single-factor analysis according to the output of the numerical simulation module, and the orthogonal test analysis module is used for conducting orthogonal test analysis according to the output of the numerical simulation module.

Abstract: An inductive charging device for charging a mobile telephone within a public transport vehicle comprises a body section that includes an inductive charging device. A holder is provided for holding the mobile telephone in a fixed charging position relative to the inductive charging device. The holder includes a plurality of rigid arms that are fixed in position relative to the main body, and a plurality of biasing members movable between an extended position and a retracted position. The biasing members are arranged within the holder such that they are moved to the retracted position when the mobile telephone is inserted into the holder and in said retracted position apply an inwardly biasing force to the mobile telephone to hold it in the charging position.

Abstract: In a method for analyzing a static analog integrated circuit layout, corresponding simulation netlists are generated from an integrated circuit layout by parasitic parameter extraction, and device-node hypergraph or graph structures reflecting a circuit topological structure are generated from the simulation netlists. Then, characteristics of RC local networks between ports of individual device groups to be matched are analyzed. An independent source current is provided at i-ports of the RC networks, AC analysis is performed on the RC local networks to acquire impedance values of j-ports at different frequencies, and then a circuit mismatch condition is determined by comparing the impedance values of the individual RC local networks.

Abstract: Various implementations of a smart battery management system are provided. An example method includes identifying sensor data of a cell in a battery system; predicting, based on the sensor data, a failure event of the cell; and preventing the failure event by activating a control circuit connected to the cell.