Abstract: A system and method for creating layout for semiconductor chips are described. In various implementations, an integrated circuit includes at least a first functional block and a second functional block. The first functional block includes circuitry that has a first set of parameters of a first process corner. The second functional block includes circuitry that has a second set of parameters of a second process corner different from the first set of parameters of the first process corner. For a same set of operating conditions, the second functional block has device characteristics different from device characteristics of the first functional block based on the first process corner and the second process corner being different from one another. The integrated circuit is fabricated with a process corner mask that indicates which areas of the die use the first process corner and which areas use the second process corner.

Abstract: A simulation acceleration system is provided. The system includes a simulation accelerator that receives compiled code of a design that includes register transfer level (RTL) components and testbench components. The compiled code includes instructions for simulating behaviors of the design. The simulation accelerator schedules the instructions to be executed by multiple processors based on simulation events occurring at different simulation timesteps. The simulation events are determined according to the executed instructions. The simulation accelerator captures trace data generated by the execution of the scheduled instructions and provides the captured trace data.

Abstract: An electronic device includes a battery device, a capacity measuring unit, and a microprocessor. The battery device outputs its remaining capacity and fully charged capacity. The capacity measuring unit includes a sensing resistor, measures the battery current of the battery device using the sensing resistor, and integrates the battery current to obtain the actual capacity. The microprocessor stores the fully charged capacity. When the battery device is in a specific state, the microprocessor calculates the capacity difference between the remaining capacity and the actual capacity. The microprocessor calibrates the fully charged capacity according to the ratio of the capacity difference to the remaining capacity.

Abstract: Various embodiments provide for adjusting routing capacity of a grid cell of one or more layers of a circuit design based on detected regions, such as notch regions (e.g., corners of macros, blockage corners) and input/output (IO) pin regions. More particularly, various embodiments detect one or more notch regions in a circuit design, detect one or more I/O pin regions in the circuit design, and adjust (e.g., reduce) routing capacity of one or more grid cells of one or more detected regions.

Abstract: A method for analyzing the contact assignment of a contact element of a cell module for a vehicle battery to charge or discharge individual cells. A module charger charges/discharges the cell module and includes a diagnosis function for the contact assignment of the contact element. A method is disclosed for operating a module charger, which allows for charging and discharging cells of different cell modules with different contact assignments and automatically prevents incorrect operation. The method includes connecting a contact element of a diagnosis unit corresponding to the contact element to establish an electrical connection with each contact. A voltage measurement is taken of a contact against all other individual contacts, and the voltage values assigned to the contacts are saved. Then, based on the assigned voltage values, the contact assignment with respect to the individual cells is determined and, finally, the cell module is charged or discharged.

Abstract: A battery array comprising a plurality of batteries. Each battery comprises a plurality of stacked battery cells, wherein the battery cells have varying properties. Each battery cell comprises an anode layer; a cathode layer; an ion conducting membrane positioned between the anode layer and the cathode layer; a top layer; a bottom layer; and circuitry disposed on the top layer, bottom layer, or both. The circuitry comprising one or more first circuits for monitoring or controlling the battery cell. Further, the battery comprises a battery control circuit configured to provide electrical interface connections with the circuitry. The battery array comprises a battery array control circuit configured to provide electrical interface connections with the battery control circuits of each battery.

Abstract: A system may generate an annotation based on an attribute determined in connection with logic. In some implementations, the logic may be between a first function (e.g., a first point of logic, such as an encoder) and a second function (e.g., a second point of logic, such as a decoder) in a first level circuit representation. The attribute may indicate, for example, fault protection using error correction code, parity, or Gray code, or a power level, frequency domain, or clock domain. The system may then identify circuitry in a second level circuit representation corresponding to the annotated logic in the first level circuit representation. The second level circuit representation may be generated based on the first level circuit representation. The system may then mark the identified circuitry in the second level circuit representation having the attribute. In some implementations, the system may determine a fault profile of an integrated circuit design based on the marking.

Abstract: Design metrics from the physical design of an integrated circuit are made available to the front end designer. Physical design metrics are computed for sub-circuits from the physical design of an integrated circuit. Examples of physical design metrics include metrics for timing, congestion, power consumption and other metrics that depend on physical aspects of the circuit. Correspondence between the sub-circuits and register transfer level (RTL) source elements from RTL source code for the integrated circuit are determined. Examples of RTL source elements include individual lines of RTL source code, modules in the RTL source code, and user-defined constructs in the RTL source code. For different RTL source elements, the physical design metrics for the corresponding sub-circuits are aggregated. These aggregated physical design metrics, including the associations to the corresponding RTL source elements, are made available to users, for example front end designers.

Abstract: Provided is a lithium ion rechargeable battery charging system with lithium cell balancing, including a lithium ion rechargeable battery and a battery charging device configured for charging the lithium ion rechargeable battery and wherein cell balancing of the lithium ion rechargeable battery cells of the lithium ion rechargeable battery continues for a predetermine period of time once a cell balancing mode begins.

Abstract: Embodiments included herein are directed towards a method for use in an electronic design. The embodiments may include receiving, using at least one processor, at least a portion of an electronic design. The method may further include automatically prompting a user for a library location indicating where to create an exported die schematic and a netlist generation view based upon, at least in part, the portion of the electronic design. The method may also include automatically generating the exported die schematic and the netlist generation view.

Abstract: A portable power panel includes a case having a first electrical connector extending therefrom. The case includes a first DC to DC convertor that converts a first DC voltage provided by a high voltage battery on the vehicle to a second DC voltage. The case includes a battery that produces the second DC voltage. An inverter inverts the second DC voltage into a third voltage useable as an alternating current. An alternating current plug supplies the third voltage to an accessory plugged into the alternating current plug. The case is configured to be selectively and alternatively moved between a (i) coupled position wherein the first electrical connector is electrically coupled to a complementary second electrical connector provided at a dock in the vehicle, and a (ii) decoupled position wherein the first and second electrical connectors are disconnected and the case is moveable providing portable power away from the vehicle.

Abstract: A method may create RTL for a circuit design utilizing DSP blocks by receiving a software program comprising a multiplication statement to multiply a first number by a second number, the first number having a first data type and a first bit width, the second number having a second data type and a second bit width; determining a number of DSP blocks for implementing the statement based at least on the first bit width, the second bit width, a first DSP bit width corresponding to a bit width of a first operand of the DSP blocks, and a second DSP bit width corresponding to a bit width of a second operand of the DSP blocks, wherein the number of DSP blocks is two or more; and generating RTL for the statement, the RTL comprises a plurality of distinct portions corresponding to each of the two or more DSP blocks.

Abstract: An integrated circuit includes a plurality of standard cells including first and second standard cells arranged adjacent to each other in a first direction, and first, second, and third metal layers sequentially stacked in a vertical direction. At least one power segment is arranged adjacent a region where at least one of the first standard cell and the second standard cell is arranged. The at least one power segment is configured to provide power to the plurality of standard cells and is formed as a pattern of the third metal layer extending in a second direction.

Abstract: An integrated circuit includes a first power rail and a second power rail extending in a first direction, and a first power grid stub connected to the first power rail through a first via-connector. The integrated circuit also includes a first vertical conducting line extending in a second direction in a circuit cell between a first vertical cell boundary and a second vertical cell boundary. The first vertical conducting line and the first power grid stub are in a same metal layer and aligned with each other along the second direction.

Abstract: A method of designing a layout of a semiconductor integrated circuit, including receiving input data defining the semiconductor integrated circuit; determining a first layout of the semiconductor integrated circuit by performing a placement and routing (P&R) procedure based on the input data, wherein the first layout includes a plurality of blocks, a plurality of standard cells, a plurality of power wirings, a plurality of ground wirings, a plurality of clock wirings, and a plurality of signal wirings; selecting a target region of the first layout, wherein the target region is capable of accommodating at least one additional power wiring and at least one additional ground wiring; and determining a second layout of the semiconductor integrated circuit by modifying the first layout to include the at least one additional power wiring and the at least one additional ground wiring in the target region.

Abstract: An electronic device can include a power system including a battery and a processor programmed to: receive synchronized context data from one or more other devices associated with a user of the device, determine, at least in part based on the synchronized context data, one or more battery charging intervals, and operate the power system to charge the battery from the external power source during the identified one or more battery charging intervals. The processor can be programmed to determine the one or more battery charging intervals using a machine learning model. The synchronized context data can provide indication of the user's location. If the synchronized context data indicates that the user is at a different location than the device, the one or more battery charging intervals determined based at least in part on an expected time for the user to return to the location of the device.

Abstract: An inductor and a related apparatus are provided. The inductor includes an upper magnet yoke and a lower magnet yoke that are straight-shaped and are disposed in parallel. A first winding disposed on a first fiber post, and a second winding disposed on a second fiber post. The upper magnet yoke, a first upper fiber post, and a second upper fiber post are integrally molded. The lower magnet yoke, a first lower fiber post, and a second lower fiber post are integrally molded. A clockwise/counterclockwise direction of a current in the first winding is consistent with a clockwise/counterclockwise direction of a current in the second winding.

Abstract: The present disclosure provides a satisfiability modulo theory (SMT) modeling system that includes graphical representation circuitry to generate graphical data representing a circuit design; finite state machine (FSM) discovery circuitry to discover, based on a feedback loop of the circuit design, an FSM contained within the graphical data; SMT assertion generation circuitry to generate an SMT assertion set of the FSM, based on the combinatorial and/or sequential logic elements associated with the FSM; and SMT modeling circuitry to determine a behavior of the FSM by applying one or more logical functions to the SMT assertion set.

Abstract: A method for optimizing a layout of a tensor memory defines at least one hard constraint for allocating a plurality of input/output (I/O) vectors for reading and writing data for a task in the tensor memory. The at least one hard constraint is applied to determine one or more potential conflicts between the plurality of I/O vectors. One or more soft constraints aimed at mitigating the one or more potential conflicts between the I/O vectors may also be generated. The at least one hard constraint is applied in a maximum satisfiability (MaxSAT) solver. The one or more soft constraints may also be applied in the MaxSAT solver. The MaxSAT solver determines locations of the data in the tensor memory. The starting addresses of the input data to be read and of output data to be written by each of the I/O vectors are updated in the tensor memory.

Abstract: A fire fighting vehicle includes an energy storage system coupled to the chassis and a charging assembly configured to interface with a charging plug. The energy storage system includes battery cells. The charging assembly includes a housing, a charging port disposed within the housing and electrically coupled to the battery cells, a retainer positioned proximate the charging port, a first actuator, and a second actuator. The charging port is configured to engage with a charging interface of the charging plug. The retainer is configured to engage with a retaining interface of the charging plug to secure the charging interface within the charging port. The first actuator is positioned to release the retaining interface from engagement with the retainer by repositioning the retaining interface into a release position. The second actuator is positioned to eject the charging plug from the charging assembly when the retaining interface is in the release position.