Patents Examined by Mohammed Alam
  • Patent number: 11023637
    Abstract: A logic simulation electronic design automation (EDA) application, the logic can be configured to receive a circuit design of an integrated circuit (IC) chip, the circuit design comprising an imported module comprising a list of simple immediate assertions (SIAs) for the imported module, wherein the circuit design comprises a first power domain and a second power domain, wherein the first power domain controls a power state of the second power domain and the imported module is assigned to the second power domain. The logic simulation EDA application can be configured to convert, in response to user input, each SIA in the list of SIAs into a respective hybrid deferred assertion (HDA) to form a list of HDAs for the imported module and execute a simulation of the IC chip, and execution of the simulation can include execution of a plurality of time slots for a plurality of simulation cycles.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: June 1, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Kohli, Sulabh Nangalia, Apurva Kalia, Yonghao Chen, Mickey Rodriguez, Abhishek Kanungo
  • Patent number: 11024623
    Abstract: A layout modification method for fabricating a semiconductor device is provided. Uniformity of critical dimensions of a first portion and a second portion in a patterned layer are calculated by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the second portion equals a penumbra size of the exposure manufacturing process, and the penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. Non-uniformity between the first and second portions of the patterned layer is compensated according to the uniformity of critical dimensions to generate a modified layout. The patterned layer includes a plurality of absorbers, and a first width of the absorbers is the first portion is less than a second width of the absorbers in the second portion the second portion.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
  • Patent number: 11018512
    Abstract: In some examples, a controller may determine, from among a plurality of energy storage units, a first energy storage unit having a higher than median charge and a second energy storage unit having a lower than median charge. The controller may connect the first energy storage unit to a resonant circuit to transfer energy from the first energy storage unit to the resonant circuit. The controller may then disconnect the first energy storage unit from the resonant circuit, and connect the second energy storage unit to the resonant circuit to transfer energy from the resonant circuit to the second energy storage unit to at least partially balance a charge difference between the first energy storage unit and the second energy storage unit.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: May 25, 2021
    Assignee: HITACHI AUTOMOTIVE SYSTEMS AMERICAS, INC.
    Inventors: Stephen A. Zavodny, Christopher Luman
  • Patent number: 11017145
    Abstract: Embodiments disclosed are directed to systems and methods for modifying an electronic circuit design. According to embodiments, the method includes generating a circuit element of an electronic circuit layout on a graphical user interface, and generating an array group including a plurality of circuit elements. Each cell of the array group includes the same circuit element, and the array group is generated such that a change in at least one attribute of the array group is applied to each circuit element of the plurality of circuit elements.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: May 25, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ashwani Kumar Sanwal, Vandana Gupta, Devendra Deshpande
  • Patent number: 11010522
    Abstract: In one aspect, a fault injection environment and a formal property verification environment are combined in a single integrated flow that allows the user to go back and forth between the two tasks. A system that unifies formal property verification and fault injection includes user interfaces that support the unified use model. In one approach, the FPV tool is the master and its user interface is the primary interface for the user to set up, run and debug faults as well as checkers. This interface allows the user to interactively select the FPV properties and/or the faults to be used for fault analysis. The user interface may provide a view of the faults, for example by listing faults or summarizing faults by class, type, etc.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: May 18, 2021
    Assignee: Synopsys, Inc.
    Inventors: Xiaolin Chen, Arunava Saha, Sandeep Jana, Pratik Mahajan, Jinnan Huang
  • Patent number: 11010527
    Abstract: Disclosed is a method for optimizing a quantum circuit of an ordered series of quantum gates, applied to an initial layout of qubit values, consisting in inserting a set of local SWAP gates so that all gates of the circuit are local, the method including: for each gate, if it is not local, inserting a set of local SWAP gates; determining the set of permutations, each consisting of a succession of swaps of qubit values along shortest paths between positions of qubits associated with the gate; and choosing, from the permutations, a permutation that minimizes a cost representing the number of swaps necessary to make the gates of a sequence within the series, of substantially smaller size, local; re-establishing the initial layout by establishing a tree covering a graph representative of the layout of the qubits of the circuit, and by swapping qubit values along paths of the tree.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: May 18, 2021
    Assignee: BULL SAS
    Inventors: Simon Martiel, Elise Rubat Ciagnus
  • Patent number: 11003828
    Abstract: Systems and methods for layout analysis using unit cell properties. A method includes receiving a layout design and analyzing the layout design to identify unit cells in the layout design. The method includes designating points of interest each corresponding to a respective one of the unit cells and classifying the unit cells into a plurality of classifications using the points of interest and the corresponding properties. The method includes identifying unique patterns of the unit cells, and producing a reduced layout including the unique patterns of unit cells. The method includes performing layout processing on the reduced layout and propagating the process results from each of the unique patterns of unit cells in the reduced layout to other unit cells of the layout design having the same classification.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: May 11, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Sherif Hany Riad Mohammed Mousa, Jea Woo Park, Michael White
  • Patent number: 10997353
    Abstract: An IC design method is provided that includes steps outlined below. A clock tree structure is retrieved from an IC design file. A branch level number of a branch that each of clock units in the clock tree structure locates is determined. A common branch level number of a common branch that closest to each two of the flip-flops is determined. A scan chain structure is retrieved from the IC design file. A wire distance and a clock skew of each two of the flip-flops are determined. A cost is calculated according to the common branch number, the wire distance and the clock skew. An initial point and a terminal point of the flip-flops in the scan chain structure are determined to further calculate a path having a minimum cost. The order of the scan chain structure of the IC design file is updated.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: May 4, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: I-Ching Tsai, Li-Yi Lin, Yun-Chih Chang, Shu-Yi Kao
  • Patent number: 10994629
    Abstract: An electric vehicle reservation charging system is provided. The system includes a communication controller that receives charging and discharging reservation setting information and power rate information. A vehicle controller determines a preset charging profile based on an entry of a preset minimum cost charging mode using the charging and discharging reservation setting information and the power rate information. A charging state control is performed based on an optimal charging state profile and an optimal charging power profile that are preset based on the charging profile. A charger then perform a power control for charging or discharging to correspond to a target charging discharging power command determined by the charging state control.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: May 4, 2021
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Hyun-Sup Kim, In-Seok Park
  • Patent number: 10990743
    Abstract: A computer implemented method for routing a multitude of conductors through a first routing area on a planar surface is presented. The method includes receiving data representing the first routing area bounded by two opposite longitudinal sides each having a different number of a multitude of first vertices. The first routing area includes one or more blockages. The method further includes determining one or more locations on at least one of the two opposite longitudinal sides for adding one or more second vertices, and decomposing the first routing area into a multitude of second routing areas each not including any of the one or more blockages. The method further includes performing a gateway model routing (GMR) of the multitude of conductors in each of the multitude of second routing areas using the multitude of first vertices and the added one or more second vertices.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: April 27, 2021
    Assignee: Synopsys, Inc.
    Inventors: Song Yuan, Chao-Min Wang, Hsin-Po Wang
  • Patent number: 10990732
    Abstract: Introduced herein is an improved technique of recovering system frequency margin via distributed CPMs. The introduced technique creates and distributes multiple sets of always sensitized critical path replicas across a chip and monitors them for timing failure. The introduced technique takes feedback from these critical path replicas and dynamically boosts the clock frequency of the chip to remove the margin. The introduced technique provides more accurate and more comprehensive coverage of a chip performance.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: April 27, 2021
    Assignee: Nvidia Corporation
    Inventors: Tezaswi Raja, Siddharth Saxena, Ben Faulkner, Sachin Idgunji, Vinayak Bhargav Srinath, Wen Yueh, Chad Plummer, Kartik Joshi
  • Patent number: 10990003
    Abstract: A method to determine a mask pattern for a patterning device. The method includes obtaining a target pattern to be printed on a substrate, an initial continuous tone image corresponding to the target pattern, a binarization function (e.g., a sigmoid, an arctan, a step function, etc.) configured to transform the initial continuous tone image, and a process model configured to predict a pattern on the substrate from an output of the binarization function; and generating a binarized image having a mask pattern corresponding to the initial continuous tone image by iteratively updating the initial continuous tone image based on a cost function such that the cost function is reduced. The cost function (e.g., EPE) determines a difference between a predicted pattern determined by the process model and the target pattern.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: April 27, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Duan-Fu Stephen Hsu, Jingjing Liu, Rafael C. Howell, Xingyue Peng
  • Patent number: 10977410
    Abstract: A switch box approach to routing interconnects during the design of an integrated circuit (IC). Processing circuitry (e.g., via an automation tool) may determine a manner in which to interconnect functional blocks of the IC. The signal routes that interconnect the functional blocks can become complicated to comply with design rules for latency, crosstalk, etc. The processing circuitry may divide channels between functional blocks into multiple interconnection blocks, called channel blocks. In this way, the channel blocks may be considered as another block type (e.g., interconnection block) that the processing circuitry can leverage for routing signals between functional blocks.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: April 13, 2021
    Assignee: Fungible, Inc.
    Inventors: Vijaykumar I. Patel, Bharat K. Bisen
  • Patent number: 10963608
    Abstract: A computer implemented method of passive verification of an electronic design, includes the steps of receiving a first electronic design file of a first electronic design comprised at least in part of a mixed signal or analog system, the first electronic design file including at least one first system and first subsystem, collecting first input data from at least one first system input and first subsystem input, analyzing a first parameter of the first input data, receiving a second electronic design file of a second electronic design comprised at least in part of a mixed signal or analog system, the second electronic design file including at least one second system and second subsystem that are comparable in function to the at least one first system and first subsystem of the first electronic design file, collecting second input data from at least one second system input and second subsystem input of the second design file, analyzing the first parameter of the second input data, comparing the analysis of the
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: March 30, 2021
    Assignee: ZIPALOG, INC.
    Inventors: Felicia James, Michael Krasnicki
  • Patent number: 10962886
    Abstract: Provided is a process of selecting a measurement location, the process including: obtaining pattern data describing a pattern to be applied to substrates in a patterning process; obtaining a process characteristic measured during or following processing of a substrate, the process characteristic characterizing the processing of the substrate; determining a simulated result of the patterning process based on the pattern data and the process characteristic; and selecting a measurement location for the substrate based on the simulated result.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: March 30, 2021
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Hans Van Der Laan, Wim Tjibbo Tel, Marinus Jochemsen, Stefan Hunsche
  • Patent number: 10956641
    Abstract: The purpose of the present invention is to facilitate evaluating the precision of a pipe network model without using flow information. An analysis device according to an embodiment of the present invention comprises a transfer characteristic derivation unit which derives a transfer characteristic which represents a relation between a voltage in a plurality of nodes which are included in an electrical circuit which is a model of a pipe network through which a fluid flows and a voltage in an interior node which is a different node of the electrical circuit from the plurality of nodes, and a computation unit which, on the basis of the transfer characteristic and the pressure of the fluid at positions within the pipe network which correspond to the plurality of nodes, computes the pressure of the fluid at a position within the pipe network which corresponds to the interior node.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: March 23, 2021
    Assignee: NEC CORPORATION
    Inventor: Manabu Kusumoto
  • Patent number: 10949594
    Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: March 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sudhakar Surendran
  • Patent number: 10936773
    Abstract: Systems and methods to perform integrated circuit development include identifying one or more multi-sink nets in a design of the integrated circuit. Each of the one or more multi-sink nets includes a source that supplies signals to two or more sinks. A method includes determining a wire tag for each of the two or more sinks of each of the one or more multi-sink nets. Each wire tag defines characteristics of a wire connecting the source to the sink, and the characteristics include a wire width and a range of metal layers within the integrated circuit for traversal of the wire. The method also includes providing the design and the wire tags for fabrication of the integrated circuit.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lukas Daellenbach, Sven Peyer
  • Patent number: 10929590
    Abstract: Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: February 23, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Ruping Cao, John G. Ferguson, John D. Cayo, Alexandre Arriordaz
  • Patent number: 10922468
    Abstract: Systems and methods for systems and methods for generating the complete set of IC design layout clips, or any part of the complete set, satisfying usefulness criteria and of a prespecified size. A method includes generating an initial set of integrated circuit (IC) design layout clips as a current set of IC design layout clips. The method includes removing any of IC design layout clips from the current set of IC design layout clips that do not meet the one or more usefulness criteria. The method includes, while a size of the IC design layout clips is less than a desired clip size, generating a new set of IC design layout clips from the current set of IC design layout clips according to every combination of pairs of the design layout clips in the current set of IC design layout clips, and repeating the removing process.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: February 16, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Mohamed-Nabil Sabry, Kareem Madkour, Sherif Ahmed Abdel-Wahab Hammouda