Abstract: A target wire is separated into one set of segments based on effective spaces of crossing wires at one target-wire side, and another set of segments based on effective spaces of crossing wires at another target-wire side. Effective widths of crossing wires at the one and other target-wire sides are accumulated. One effective length factor for crossing wires at the one target-wire side is determined, and another effective length factor for crossing wires at the other target-wire side is determined. One or more capacitance values are ascertained for the one and other target-wire sides with reference to a data structure of capacitance per-unit-length for identified configurations. A total capacitance is determined using the effective length factors, and the ascertained capacitance values. An impact of the determined total capacitance on circuit performance is assessed, and based on the assessing, the wiring pattern of the integrated circuit is modified.

Abstract: A method may include generating a residual curvature map for a substrate, the residual curvature map being based upon a measurement of a surface of the substrate. The method may include generating a dose map based upon the residual curvature map, the dose map being for processing the substrate using a patterning energy source; and applying the dose map to process the substrate using the patterning energy source.

Abstract: Timing analysis of a digital integrated circuit using intent based timing constraints includes defining a plurality of intent groups for an integrated circuit design. Each intent group is associated with a different clock type of the integrated circuit design. A different timing phase of a plurality of timing phases of one or more clock signals of the integrated circuit design is associated with each intent group. One or more timing constraints is associated with each of the intent groups. A timing result is computed based on propagating the timing phases of each of the intent groups and applying the associated timing constraints from an input to a timing point of the integrated circuit design.

Abstract: In some aspects, timing metrics for timing paths of a circuit design are accessed. These timing metrics were evaluated at a first temperature. The circuit design includes multiple components. Location-dependent temperature information for the components and a thermal derate schedule are also accessed. The thermal derate schedule specifies adjustments to timing metrics as a function of temperature. A processing device adjusts the timing metrics based on the thermal derate schedule and based on differences between the first temperature and the location-dependent temperature information for the respective components of the circuit design.

Abstract: An optical proximity correction (OPC) method using a Jacobian matrix, which may minimize an edge placement error (EPE) of an arbitrary pattern, and a method of manufacturing a mask by using the OPC method. The OPC method may include obtaining training data for calculating a differentiation Jacobian matrix of a mask segment of an EPE, obtaining a neural Jacobian matrix model through artificial neural network (ANN) training using the training data, and applying a prediction value based on the neural Jacobian matrix model to mask optimization (MO) to minimize the EPE.

Abstract: Automatic verification of a hardware cryptographic implementation includes receiving a reference implementation of a cryptographic algorithm, receiving test case data associated with the cryptographic algorithm, generating a stimulus based upon the test case data, applying the stimulus to the reference implementation using a simulation model to generate a first intermediate state result, applying the stimulus to a hardware implementation of the cryptographic algorithm using the simulation model to generate a second intermediate state result, and generating a verification result based upon a comparison of the first intermediate state result and the second intermediate state result.

Abstract: A system and method for implementing and generating a network-on-chip (NoC) topology based on area and timing assessment. A topology of the NoC is defined, approximations of area and timing of the topology without optimization are performed; and an exact, complete register transfer level (RTL) description of the topology is generated if the approximated area and timing satisfy constraints.

Abstract: A system may provide a placeholder for a component in a block of a first-level integrated circuit design without wiring at least one port of the component. The system may determine a mapping to a provider interface in the block. The system may invoke an integrated circuit generator to generate a second-level integrated circuit design based on the first-level integrated circuit design. The generator when executed replaces the provider interface with the component including wiring ports of the component, including the at least one port, in the second-level integrated circuit design according to the mapping. In some implementations, an application program interface may enable a provider to communicate with the generator. The provider can utilize the API to instantiate the provider interface and determine the mapping.

Abstract: Optimizing ML models for resource constraints in electronic design automation (EDA) computer aided design (CAD) flows, including computing a set of bin thresholds based on slope changes in an ordered set of discrete probabilistic classification scores, assigning the discrete probabilistic classification scores to the bins based on the values of the discrete probabilistic classification scores and the bin thresholds, and selecting processes associated with the discrete probabilistic classification scores of one or more of the bins based on costs of the respective processes and a global budget.

Abstract: Provided are a wireless charging base and a charging system of automatic snow sweeping equipment. The wireless charging base comprises a mounting component and a charging component, an upper end face of the mounting component and a support surface of the wireless charging base are oppositely arranged at a preset included angle, or, the upper end face of mounting component has a first side and a second side, and the distance between the upper end face and the support surface gradually increases from the first side to the second side, so as to be suitable for automatic snow sweeping equipment to move from the first side to the second side.

Abstract: Methods for implementing or synthesizing functions in hardware and fixed-function hardware include generating a look-up table, LUT, representing the function and then applying a transform to the LUT to transform the LUT into a plurality of derived LUTs. The transform may be applied recursively. A hardware design implementing each of the derived LUTs in fixed-function hardware logic, along with a logic unit that performs the inverse transform, is then created.

Abstract: An electronic device manufacturing system configured to identify, by a processor, a first machine-learning model trained to generate predictive data for a first process chamber and obtain metrology data associated with a substrate produced by a second process chamber. The manufacturing system is further configured to train a second machine-learning model based on the first machine-learning model and the metrology data, wherein the second machine-learning model is trained to generate predictive data associated with the second process chamber.

Abstract: Methods and systems are provided for performing power shut-off in a high-level synthesis flow. The methods and systems access a high level synthesis flow (HLS) file representing a circuit design. The methods and systems process the HLS file to identify a portion of the circuit design that is associated with power shut-off indicating that the portion of the circuit design is enabled for shut down. The methods and systems, based on identifying the portion of the circuit design that is associated with power shut-off, synthesize the HLS file into a register-transfer level (RTL) design of the circuit design in which one or more logic elements that implement the portion of the circuit design are enabled for shut down. In addition to the generation of the RTL design, a Power Intent File is generated to communicate a list of retention and non-retention registers to the downstream EDA flow.

Abstract: Disclosed are a method for obtaining a quantum circuit performed by a computer device, relating to the field of quantum technologies. The method includes: obtaining a combination of identity matrices and Pauli Z matrices as a diagonal matrix basis; determining a dynamical evolution relationship of imaginary time diagonal control based on the diagonal matrix basis and a dynamical evolution relationship of quantum imaginary time control; determining a first quantum circuit of imaginary time diagonal control based on the dynamical evolution relationship of imaginary time diagonal control; determining a second quantum circuit based on a variational quantum approximation algorithm; and cyclically alternating the first quantum circuit and the second quantum circuit to obtain a quantum circuit.

Abstract: A battery system for a vehicle includes: a first positive terminal, a second positive terminal, and a negative terminal; switches; at least two battery modules each including at least three strings of battery cells that are configured to, at different times be: connected in series and to the first positive terminal via first ones of the switches; connected in parallel and to the second positive terminal via second ones of the switches; and disconnected from both of the first and second positive terminals; and a switch control module configured to, based on a derated state of the vehicle, adjust at least one of an upper limit for charging of the battery strings and a lower limit for discharging of the battery strings.

Abstract: Provided is a semiconductor device simulation system and method. The simulation system includes; a device structure file input module configured to receive a plurality of device structure files for a plurality of sub-devices obtained by dividing a semiconductor device to be simulated; a connection relationship extraction module configured to extract connection relationships between the device structure files for the sub-devices; an interface condition application module configured to apply interface conditions to interface points of the device structure files according to the extracted connection relationships; and a simulation module configured to simulate an operation of the semiconductor device using the device structure files for the sub-devices and the interface conditions at interface points of adjacent sub-devices. The simulation system can simulate the semiconductor device using a plurality of device structure files for the sub-devices.

Abstract: A computer system is provided for protecting a circuit design for an application specific integrated circuit. The computer system includes a logic circuit replacement tool for identifying a module of logic circuitry for replacement in at least a portion of the circuit design. The logic circuit replacement tool generates a transformed circuit design for the application specific integrated circuit by replacing the logic circuitry in the module with a configurable circuit that performs a logic function of the logic circuitry when a bitstream stored in storage circuits in the configurable circuit configures the configurable circuit. The transformed circuit design includes the configurable circuit in the module.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for methods and apparatus to generate I/O timing constraint predictions for system-on-chips using machine learning. An apparatus is disclosed herein comprising at least one memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to extract delay features from a first system-on-chip design and a second system-on-chip design, apply a machine learning model to the extracted delay features to determine an estimated delay for the first system-on-chip design, compare the estimated delay for the first system-on-chip design to the second system-on-chip design to determine an error of the first system-on-chip design, and update the second system-on-chip design based on the error determined for the first system-on-chip design.

Abstract: Embodiments included herein are directed towards a method for use in an electronic design. The method may include receiving, at a graphical user interface, a first indication to integrate a first fabric associated with the electronic design. The method may further include, in response to receiving the first indication, receiving first data associated with the first fabric. The method may also include launching, based at least in part on the first data, a first distributed electronic design application session corresponding to the first fabric. The method may additionally include determining, based at least in part on the first data, a first top level layout of the first fabric. Furthermore, the method may include generating a first plurality of technology independent elements corresponding to the first fabric.

Abstract: A pattern generation device includes a memory and a processor coupled to the memory. The processor is configured to generate pattern data corresponding to a pattern of a metal layer based on a generation condition, determine whether the generated pattern data satisfies a predetermined condition, return to generate the pattern data when the predetermined condition is not satisfied, calculate a characteristic of the pattern or an element or circuit having the pattern when a high-frequency signal is inputted to a first portion and a high-frequency signal is outputted from a second portion by performing an electromagnetic field analysis based on the pattern data when the predetermined condition is satisfied, determine whether the calculated characteristic is within a target range, change the generation condition when the calculated characteristic is not within the target range, and return to generate the pattern data after changing the generation condition.