Abstract: A battery system for a vehicle includes: a first positive terminal, a second positive terminal, and a negative terminal; switches; at least two battery modules each including at least three strings of battery cells that are configured to, at different times be: connected in series and to the first positive terminal via first ones of the switches; connected in parallel and to the second positive terminal via second ones of the switches; and disconnected from both of the first and second positive terminals; and a switch control module configured to, based on a derated state of the vehicle, adjust at least one of an upper limit for charging of the battery strings and a lower limit for discharging of the battery strings.

Abstract: Provided is a semiconductor device simulation system and method. The simulation system includes; a device structure file input module configured to receive a plurality of device structure files for a plurality of sub-devices obtained by dividing a semiconductor device to be simulated; a connection relationship extraction module configured to extract connection relationships between the device structure files for the sub-devices; an interface condition application module configured to apply interface conditions to interface points of the device structure files according to the extracted connection relationships; and a simulation module configured to simulate an operation of the semiconductor device using the device structure files for the sub-devices and the interface conditions at interface points of adjacent sub-devices. The simulation system can simulate the semiconductor device using a plurality of device structure files for the sub-devices.

Abstract: A computer system is provided for protecting a circuit design for an application specific integrated circuit. The computer system includes a logic circuit replacement tool for identifying a module of logic circuitry for replacement in at least a portion of the circuit design. The logic circuit replacement tool generates a transformed circuit design for the application specific integrated circuit by replacing the logic circuitry in the module with a configurable circuit that performs a logic function of the logic circuitry when a bitstream stored in storage circuits in the configurable circuit configures the configurable circuit. The transformed circuit design includes the configurable circuit in the module.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for methods and apparatus to generate I/O timing constraint predictions for system-on-chips using machine learning. An apparatus is disclosed herein comprising at least one memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to extract delay features from a first system-on-chip design and a second system-on-chip design, apply a machine learning model to the extracted delay features to determine an estimated delay for the first system-on-chip design, compare the estimated delay for the first system-on-chip design to the second system-on-chip design to determine an error of the first system-on-chip design, and update the second system-on-chip design based on the error determined for the first system-on-chip design.

Abstract: Embodiments included herein are directed towards a method for use in an electronic design. The method may include receiving, at a graphical user interface, a first indication to integrate a first fabric associated with the electronic design. The method may further include, in response to receiving the first indication, receiving first data associated with the first fabric. The method may also include launching, based at least in part on the first data, a first distributed electronic design application session corresponding to the first fabric. The method may additionally include determining, based at least in part on the first data, a first top level layout of the first fabric. Furthermore, the method may include generating a first plurality of technology independent elements corresponding to the first fabric.

Abstract: A pattern generation device includes a memory and a processor coupled to the memory. The processor is configured to generate pattern data corresponding to a pattern of a metal layer based on a generation condition, determine whether the generated pattern data satisfies a predetermined condition, return to generate the pattern data when the predetermined condition is not satisfied, calculate a characteristic of the pattern or an element or circuit having the pattern when a high-frequency signal is inputted to a first portion and a high-frequency signal is outputted from a second portion by performing an electromagnetic field analysis based on the pattern data when the predetermined condition is satisfied, determine whether the calculated characteristic is within a target range, change the generation condition when the calculated characteristic is not within the target range, and return to generate the pattern data after changing the generation condition.

Abstract: Embodiments of the present disclosure provide a power display method and apparatus, and an electronic device. The method includes: determining, in a case that a target condition is satisfied, a target charging power in each of N pieces of preset duration, to obtain N target charging power, where N is a positive integer; determining a target consumed power in each of the N pieces of preset duration, to obtain N target consumed power; and generating a target charging curve according to a current remaining power, N target charging power, and N target consumed power of the electronic device, where the target condition is that the electronic device is in a charging state, or the electronic device is in a simulated charging state.

Abstract: Disclosed are a process design kit (PDK) product and also a design system and a design method that employ the PDK product to layout IC designs including 3D IC designs. The PDK product includes a storage medium and a PDK, including a library of cells, stored thereon. The cells can include parameterized cells (pcells) representing various IC components. The pcells are parameter-customizable and one or more of the pcells are also layout configuration-customizable. Each parameter and layout configuration-customizable pcell includes customization script, which is executable by a processor in response to inputs specific to that pcell and which can cause the processor to place an instance of that pcell with customized parameters in a 3D IC layout according to a selected layout configuration option (e.g., a single-chip layout configuration option or a multi-chip layout configuration option).

Abstract: Implementations of a method of generating a product system model may include, using a first interface, receiving from a user a selection of a product type; selecting a product SPICE model associated with the product type from a database of product SPICE models; and using a second interface, receiving from the user a selection of a process condition. The method may include, using a third interface, receiving from the user one or more system characteristics and one or more operating characteristics; using a fourth interface, receiving from the user one or more circuit characteristics; using a SPICE model simulation module, generating a SPICE model output with the product SPICE model, and, using a formatting module, formatting the SPICE model output into a product system model file, the product system model file including one of a structured text file, a plain text file, or a delimited text file.

Abstract: A quantum circuit includes a plurality of first optical waveguides and a plurality of second optical waveguides formed on a substrate and each of which includes a single-photon source; a first multiplexer formed on the substrate and configured to condense first photons propagated through the plurality of first optical waveguides; a second multiplexer formed on the substrate and configured to condense second photons propagated through the plurality of second optical waveguides; a branching element configured to introduce the first photons condensed by the first multiplexer and the second photons condensed by the second multiplexer and branch the first photons and the second photons in a first direction and a second direction; a first detector configured to detect the first photons and the second photons branched in the first direction; and a second detector configured to detect the first photons and the second photons branched in the second direction.

Abstract: An example mobile computing device includes at least one processor, a battery, and a device enclosure. The device enclosure at least partially encloses the mobile computing device. At least one portion of the device enclosure comprises at least one first element, a region that is at least partially formed in and at least partially surrounded by the at least one first element, at least one insulative element formed in the region, wherein the at least one insulative element includes at least one electrically insulative material, and a wireless charging module included in the region. The wireless charging module is configured to wirelessly communicate with an external charging device to induce a current in the wireless charging unit, and wherein the current is used to charge the battery of the mobile computing device.

Abstract: A power integration system with motor drive and battery charging and discharging function includes a motor, a power integration circuit, and a battery. The motor includes multi-phase paths, and each path has an inductor. The power integration circuit includes an inverter and a charger. The inverter includes multi-phase bridge arms, each bridge arm has an upper switch and a lower switch, and each bridge is correspondingly coupled to each inductor of the motor. The charger a switch, the upper switch and the lower switch of at least one bridge arm of the shared inverter, and the inductor of the shared motor. The switch is coupled between any two bridge arms. The power integration circuit receives a DC power provided by a DC power apparatus, and the charger converts the DC power to charge the battery, and the battery provides power required to drive the motor through the inverter.

Abstract: A system and method of designing an integrated circuit for calculating an approximation of a target function over a predetermined interval may include employing an approximation algorithm, to calculate a first approximation function, which approximates the target function. Embodiments may construct an objective function based on the first approximation function. Based on the objective function, embodiments may calculate a first set of outcome coefficient values, which define an outcome approximation function, and generate, based on the outcome approximation function, an approximation schematic. The approximation schematic may represent an electrical approximation circuit, adapted to (i) receive an input value within the predetermined interval, and (ii) produce an estimation of the mathematical function at the input value, according to the outcome approximation function.

Abstract: A system and method for creating layout for semiconductor chips are described. In various implementations, an integrated circuit includes at least a first functional block and a second functional block. The first functional block includes circuitry that has a first set of parameters of a first process corner. The second functional block includes circuitry that has a second set of parameters of a second process corner different from the first set of parameters of the first process corner. For a same set of operating conditions, the second functional block has device characteristics different from device characteristics of the first functional block based on the first process corner and the second process corner being different from one another. The integrated circuit is fabricated with a process corner mask that indicates which areas of the die use the first process corner and which areas use the second process corner.

Abstract: A simulation acceleration system is provided. The system includes a simulation accelerator that receives compiled code of a design that includes register transfer level (RTL) components and testbench components. The compiled code includes instructions for simulating behaviors of the design. The simulation accelerator schedules the instructions to be executed by multiple processors based on simulation events occurring at different simulation timesteps. The simulation events are determined according to the executed instructions. The simulation accelerator captures trace data generated by the execution of the scheduled instructions and provides the captured trace data.

Abstract: An electronic device includes a battery device, a capacity measuring unit, and a microprocessor. The battery device outputs its remaining capacity and fully charged capacity. The capacity measuring unit includes a sensing resistor, measures the battery current of the battery device using the sensing resistor, and integrates the battery current to obtain the actual capacity. The microprocessor stores the fully charged capacity. When the battery device is in a specific state, the microprocessor calculates the capacity difference between the remaining capacity and the actual capacity. The microprocessor calibrates the fully charged capacity according to the ratio of the capacity difference to the remaining capacity.

Abstract: Various embodiments provide for adjusting routing capacity of a grid cell of one or more layers of a circuit design based on detected regions, such as notch regions (e.g., corners of macros, blockage corners) and input/output (IO) pin regions. More particularly, various embodiments detect one or more notch regions in a circuit design, detect one or more I/O pin regions in the circuit design, and adjust (e.g., reduce) routing capacity of one or more grid cells of one or more detected regions.

Abstract: A method for analyzing the contact assignment of a contact element of a cell module for a vehicle battery to charge or discharge individual cells. A module charger charges/discharges the cell module and includes a diagnosis function for the contact assignment of the contact element. A method is disclosed for operating a module charger, which allows for charging and discharging cells of different cell modules with different contact assignments and automatically prevents incorrect operation. The method includes connecting a contact element of a diagnosis unit corresponding to the contact element to establish an electrical connection with each contact. A voltage measurement is taken of a contact against all other individual contacts, and the voltage values assigned to the contacts are saved. Then, based on the assigned voltage values, the contact assignment with respect to the individual cells is determined and, finally, the cell module is charged or discharged.

Abstract: A battery array comprising a plurality of batteries. Each battery comprises a plurality of stacked battery cells, wherein the battery cells have varying properties. Each battery cell comprises an anode layer; a cathode layer; an ion conducting membrane positioned between the anode layer and the cathode layer; a top layer; a bottom layer; and circuitry disposed on the top layer, bottom layer, or both. The circuitry comprising one or more first circuits for monitoring or controlling the battery cell. Further, the battery comprises a battery control circuit configured to provide electrical interface connections with the circuitry. The battery array comprises a battery array control circuit configured to provide electrical interface connections with the battery control circuits of each battery.

Abstract: A system may generate an annotation based on an attribute determined in connection with logic. In some implementations, the logic may be between a first function (e.g., a first point of logic, such as an encoder) and a second function (e.g., a second point of logic, such as a decoder) in a first level circuit representation. The attribute may indicate, for example, fault protection using error correction code, parity, or Gray code, or a power level, frequency domain, or clock domain. The system may then identify circuitry in a second level circuit representation corresponding to the annotated logic in the first level circuit representation. The second level circuit representation may be generated based on the first level circuit representation. The system may then mark the identified circuitry in the second level circuit representation having the attribute. In some implementations, the system may determine a fault profile of an integrated circuit design based on the marking.