Patents Examined by Mohammed Bashar
  • Memory system and method of controlling non-volatile memory
    Patent number: 11551774
    Abstract: According to one embodiment, a memory system includes a non-volatile memory provided with a plurality of memory cells, and a memory controller. The memory controller reads data subjected to error-mitigation encoding from the non-volatile memory, the data including determination information indicating whether or not a value is changed by the error-mitigation encoding, executes error-mitigation decoding on the read data, re-executes the error-mitigation encoding on a decoding result obtained by the error-mitigation decoding, and compares the determination information included in the read data with determination information included in data obtained by re-executing the error-mitigation encoding and outputs a comparison result.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: January 10, 2023
    Assignee: Kioxia Corporation
    Inventors: Itaru Hida, Tokumasa Hara
  • Systems and methods for writing, reading, and controlling data stored in a polymer
    Patent number: 11549140
    Abstract: The disclosure provides a novel system of storing information using a charged polymer, e.g., DNA, the monomers of which correspond to a machine-readable code, e.g., a binary code, and which can be synthesized and/or read using a novel nanochip device comprising nanopores; novel methods and devices for synthesizing oligonucleotides in a nanochip format; novel methods for synthesizing DNA in the 3? to 5? direction using topoisomerase; novel methods and devices for reading the sequence of a charged polymer, e.g., DNA, by measuring capacitive or impedance variance, e.g., via a change in a resonant frequency response, as the polymer passes through the nanopore; and further provides compounds, compositions, methods and devices useful therein.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: January 10, 2023
    Assignee: IRIDIA, INC.
    Inventors: Paul F. Predki, Maja Cassidy
  • Auto-power on mode for biased testing of a power management integrated circuit (PMIC)
    Patent number: 11538545
    Abstract: Methods, systems, and devices supporting an auto-power on mode for biased testing of a power management integrated circuit (PMIC) are described. A system may program a PMIC of a memory system to a specific mode. The mode may cause the PMIC to apply a bias to a memory device of the memory system upon receiving power and independent of a command to apply the bias to the memory device. The system may transmit power to the memory system while controlling one or more operating conditions (e.g., temperature, humidity) for a threshold time. The PMIC may apply a bias to the memory device during the threshold time based on the PMIC being programmed to the mode and the transmitted power. The system may identify a capability or defect of the memory device resulting from transmitting the power to the memory system while controlling the operating conditions for the threshold time.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventor: William Anthony Lendvay
  • Latch circuit and memory device including the same
    Patent number: 11532375
    Abstract: A memory device includes a latch circuit suitable for storing an input address as a first latch address in response to a first latch signal, and storing an address, selected between the input address and the first latch address, as a second latch address in response to a second latch signal, a test determining circuit suitable for determining whether a memory cell fail occurs, based on test data, and generating a detection signal corresponding to the determination result, in response to a test mode signal, and a control signal generation circuit suitable for comparing the input address to the first and second latch addresses in response to the detection signal, and selectively enabling the first and second latch signals according to the comparison result.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: December 20, 2022
    Assignee: SK hynix Inc.
    Inventor: Woo Hyun Paik
  • Memory with automatic background precondition upon powerup
    Patent number: 11532358
    Abstract: Memory devices and systems with automatic background precondition upon powerup, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a plurality of memory cells and a fuse array configured to store precondition data. The precondition data can identify a portion of the memory array, specify a predetermined precondition state, or a combination thereof. When the memory device powers on, the memory device can be configured to automatically retrieve the precondition data from the fuse array and/or to write memory cells in the portion of the memory array to the predetermined precondition state before executing an access command.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: December 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Anthony D. Veches, Debra M. Bell, James S. Rehmeyer, Robert Bunnell, Nathaniel J. Meier
  • Method for reading and writing and memory device
    Patent number: 11527301
    Abstract: The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; storing the address information pointed to by the read command into a memory bit of a preset memory space if an error occurs in the data to be read out, wherein the preset memory space is provided with a plurality of the memory bits, each of the plurality of memory bits being associated with a spare memory cell; and backing up the address information stored in the preset memory space into a non-volatile memory cell according to a preset rule.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: December 13, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Shuliang Ning, Jun He, Zhan Ying, Jie Liu
  • Automated method and associated device for the non-volatile storage, retrieval and management of message/label associations and vice versa, with maximum likelihood
    Patent number: 11526741
    Abstract: An associative-memory-storage unit, and to an associative-memory-storage method are provided. The associative-memory-storage unit includes a first subset of at least memory sub-units over w bits, and a second memory sub-unit over v bits. The associative-memory-storage sub-unit may be used to associate messages with labels, and vice versa.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 13, 2022
    Assignee: ANOTHER BRAIN
    Inventor: Patrick Pirim
  • Level dependent error correction code protection in multi-level non-volatile memory
    Patent number: 11527300
    Abstract: A method, apparatus, and system for level dependent error correction code protection in multi-level non-volatile memory. A write command to write data to a non-volatile memory array may be received. At least one multi-level page of multi-level storage cells may be determined for the write data. A coding rate for the write data of the at least one multi-level page may be determined based on an attribute of the at least one multi-level page. An ECC codeword may be generated that satisfies the coding rate and includes the write data. The ECC codeword may then be stored on the at least one multi-level page.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: December 13, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Nian Yang, Sahil Sharma, Harish Singidi
  • Adjusting a reliability scan threshold in a memory sub-system
    Patent number: 11521699
    Abstract: A first scan operation of a set of memory pages of a data block is performed using a first reliability threshold level to identify a set of scan results. A workload type associated with the data block is determined based on the set of scan results. The first reliability threshold level is adjusted to a second reliability threshold level based on the workload type. A second scan operation of the set of memory pages of the data block is performed using the second reliability threshold level.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: December 6, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Ashutosh Malshe, Gianni S. Alsasua, Harish R. Singidi
  • Semiconductor memory device, method of driving the same and method of fabricating the same
    Patent number: 11508728
    Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged along a common semiconductor layer. Each of the plurality of memory cell transistors comprises a first source/drain region and a second source/drain region formed in the common semiconductor layer; a gate stack formed on a portion of the common semiconductor layer between the first source/drain region and the second source/drain region; and an electrical floating portion in the portion of the common semiconductor layer, a charge state of the electrical floating portion being adapted to adjust a threshold voltage and a channel conductance of the memory cell transistor. The plurality of memory cell transistors connected in series with each other along the common semiconductor layer provide a memory string.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: November 22, 2022
    Assignees: SK hynix Inc., Duality Inc.
    Inventor: Jin Hong Ahn
  • Methods of synthesizing DNA
    Patent number: 11505825
    Abstract: The disclosure provides methods of synthesizing DNA using topoisomerase-mediated ligation, by adding single nucleotides or oligomers to a DNA strand in the 3? to 5? direction.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: November 22, 2022
    Assignee: IRIDIA, INC.
    Inventor: Paul F. Predki
  • Memory repair using optimized redundancy utilization
    Patent number: 11495314
    Abstract: A semiconductor device is provided, which contains a memory bank including M primary word lines and R replacement word lines, a row/column decoder, and an array of redundancy fuse elements. A sorted primary failed bit count list is generated in a descending order for the bit fail counts per word line. A sorted replacement failed bit count list is generated in an ascending order of the M primary word lines in an ascending order. The primary word lines are replaced with the replacement word lines from top to bottom on the lists until a primary failed bit count equals a replacement failed bit count or until all of the replacement word lines are used up. Optionally, the sorted primary failed bit count list may be re-sorted in an ascending or descending order of the word line address prior to the replacement process.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Hao Huang, Cheng-Yi Wu, Katherine H. Chiang, Chung-Te Lin
  • Leakage compensation for memory arrays
    Patent number: 11482268
    Abstract: Apparatuses and techniques for compensating for noise, such as a leakage current, in a memory array are described. Leakage currents may, for example, be introduced onto a digit line from unselected memory cells. In some cases, a compensation component may be coupled with the digit line during a first phase of a read operation, before the target memory cell has been coupled with the digit line. The compensation component may sample a current on the digit line and store a representation of the sampled current. During a second phase of the read operation, the target memory cell may be coupled with the digit line. During the second phase, the compensation component may compensate for leakage or other parasitic effects by outputting a current on the digit line during the read operation based on the stored representation of the sampled current.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: October 25, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Memory device virtual blocks using half good blocks
    Patent number: 11475974
    Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sri Rama Namala, Jung Sheng Hoei, Jianmin Huang, Ashutosh Malshe, Xiangang Luo
  • Memory component provided with a test interface
    Patent number: 11462288
    Abstract: A memory component comprises a memory unit including an array of memory cells, a controller of the memory unit, and a JTAG test interface including a plurality of contact pads adapted to connect the memory component with a host device and/or a test machine, wherein the test interface further comprises a plurality of test registers, which are configured to store the operating instructions for performing the test of the memory component, and wherein those test registers are organized in a matrix configuration, each row of the matrix being associated with a specific address. A related System-On-Chip device and a related method are further disclosed.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: October 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Antonino Mondello, Alberto Troia
  • Memory and operation method of memory
    Patent number: 11462286
    Abstract: A method for operating a memory includes: activating a first row, and sensing and amplifying, by a first bit line sense amplifier array, data of memory cells of the first row; transferring data of first columns of the first row from the first bit line sense amplifier array to global input/output lines through first input/output sense amplifiers; storing data of the global input/output lines in the first columns of a dummy bit line sense amplifier array through dummy write drivers; transferring data of second columns of the first row from the first bit line sense amplifier array to the global input/output lines through the first input/output sense amplifiers; and storing the data of the global input/output lines in the second columns of the dummy bit line sense amplifier array through the dummy write drivers.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: October 4, 2022
    Assignee: SK hynix Inc.
    Inventors: Munseon Jang, Hoiju Chung
  • Semiconductor memory device, method of driving the same and method of fabricating the same
    Patent number: 11456297
    Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged along a common semiconductor layer. Each of the plurality of memory cell transistors comprises a first source/drain region and a second source/drain region formed in the common semiconductor layer; a gate stack formed on a portion of the common semiconductor layer between the first source/drain region and the second source/drain region; and an electrical floating portion in the portion of the common semiconductor layer, a charge state of the electrical floating portion being adapted to adjust a threshold voltage and a channel conductance of the memory cell transistor. The plurality of memory cell transistors connected in series with each other along the common semiconductor layer provide a memory string.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: September 27, 2022
    Assignees: SK hynix Inc., Duality Inc.
    Inventor: Jin Hong Ahn
  • Memory device including redundancy mats
    Patent number: 11450404
    Abstract: A memory device includes an at least one first normal mat and an at least one second normal mat, a first redundancy mat configured to provide one or more first redundancy column lines for repairing one or more column lines disposed in the at least one first normal mat, a second redundancy mat configured to provide one or more second redundancy column lines for repairing one or more column lines disposed in the at least one second normal mat, and a redundancy segmented input/output (I/O) line coupled to both of the first redundancy mat and the second redundancy mat.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: September 20, 2022
    Assignee: SK hynix Inc.
    Inventors: Soo Hwan Kim, Mi Hyun Hwang
  • Flexible memory system with a controller and a stack of memory
    Patent number: 11450354
    Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: September 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Joe M. Jeddeloh, Brent Keeth
  • Memory system
    Patent number: 11450397
    Abstract: A memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller is configured to schedule plural types of reliability countermeasure processes to be executed for the nonvolatile semiconductor memory. The plural types of reliability countermeasure processes includes at least a first reliability countermeasure process. The memory controller is configured to skip the first reliability countermeasure process to be executed when the first reliability countermeasure process is not necessary to be executed by executing an access process other than the first reliability countermeasure process to the nonvolatile semiconductor memory.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: September 20, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Prashob Ramachandran Nair