Abstract: A display apparatus includes a buffer layer provided on a substrate and having a plurality of concave portions and a black matrix disposed at each of the plurality of concave portions, whereby loss of the black matrix may be prevented and a filling material may be uniformly filled when a transistor substrate and a color filter substrate are bonded.

Abstract: A photodetector includes a light receiving part having a plurality of light receiving elements, and a signal processing part that adds outputs from the light receiving elements and outputs the result. A plurality of measurements are performed while combination of effective light receiving elements among the light receiving elements in the light receiving part is changed. The results of the measurements are subjected to a compressive sensing process to determine an output signal of for each light receiving element or for each group of light receiving elements.

Abstract: Disclosed are a semiconductor nanocrystal particle including indium (In), zinc (Zn), and phosphorus (P), wherein a mole ratio of the zinc relative to the indium is greater than or equal to about 25:1, and the semiconductor nanocrystal particle includes a core including a first semiconductor material including indium, zinc, and phosphorus and a shell disposed on the core and including a second semiconductor material including zinc and sulfur, a method of producing the same, and an electronic device including the same. The semiconductor nanocrystal particle emits blue light having a maximum peak emission at a wavelength of less than or equal to about 470 nanometers.

Abstract: A solid-state imaging device includes: a plurality of pixels each including a first electrode, an organic photoelectric conversion film, and a second electrode in this order on a substrate, the organic photoelectric conversion film including a first inclined surface on a side wall; and a first sealing film formed, on the plurality of pixels, to cover the side wall of the organic photoelectric conversion film and the second electrode.

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

Abstract: Embodiments of the invention provide a semiconductor memory device. In some embodiments, the device includes a bottom electrode extending in a y-direction relative to top surface of a substrate and a top electrode extending in an x-direction relative to the top surface of the substrate. An active area is located at the cross-section between the bottom electrode and the top electrode and is located on vertical side walls extending in a z-direction of the semiconductor memory device with respect to the top surface of the substrate. An insulating layer is located in the active area in between the top electrode and the bottom electrode.

Abstract: To increase emission efficiency of a fluorescent light-emitting element by efficiently utilizing a triplet exciton generated in a light-emitting layer. The light-emitting layer of the light-emitting element includes at least a host material and a guest material. The triplet exciton generated from the host material in the light-emitting layer is changed to a singlet exciton by triplet-triplet annihilation (TTA). The guest material (fluorescent dopant) is made to emit light by energy transfer from the singlet exciton. Thus, the emission efficiency of the light-emitting element is improved.

Abstract: A device includes a fuse-array mat including a plurality of fuse-array elements. Each fuse-array element includes a fuse comprising a fuse line having less than or equal to 50% of a dimension of the fuse line disposed over an active area of the fuse-array element, wherein the fuse is configured to be activated to indicate a fuse state of the fuse of two possible fuse states of the fuse. Additionally, each fuse-array element includes an access device comprising a gate line having more than 50% of a dimension of the gate line disposed over the active area of the fuse-array element.

Abstract: A method of fabricating a semiconductor structure is described. The method comprises forming at least one mandrel on a substrate, the at least one mandrel comprising a diamond-like carbon and having a top and two opposing sidewalls, the diamond-like carbon comprising at least 40% sp3 hybridized carbon atoms. The mandrel may be used in Self-Aligned Multiple Patterning (SAMP) processes.

Abstract: A semiconductor device includes a body region of a second conductivity type, a body contact region of the second conductivity type formed in the body region and having a higher average doping concentration than the body region, a source region of a first conductivity type opposite the second conductivity type formed in the body region adjacent the body contact region, a drift zone of the first conductivity type spaced apart from the source region by a section of the body region which forms a channel region of the semiconductor device, and a gate electrode configured to control the channel region. The body contact region extends under a majority of the source region in a direction towards the channel region and has a doping concentration of at least 1e18 cm?3 under the majority of the source region. Additional semiconductor device embodiments and methods of manufacture are described.

Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

Abstract: A semiconductor device includes a base substrate including an NMOS region and a PMOS region. The PMOS region includes a first P-type region and a second P-type region. The semiconductor device also includes an interlayer dielectric layer, a gate structure formed through the interlayer dielectric layer and including an N-type region gate structure formed in the NMOS region, a first gate structure formed in the first P-type region and connected to the N-type region gate structure, and a second gate structure formed in the second P-type region and connected to the first gate structure. The direction from the N-type region gate structure to the second gate structure is an extending direction of the gate structure, and along a direction perpendicular to the extending direction of the gate structure, the width of the first gate structure is larger than the width of the second gate structure.

Abstract: Systems, methods and apparatus are disclosed for interfacing process controllers in a process automation system with one or more intelligent electrical devices (IEDs) of an electrical automation system to use process and electrical control space information to perform actions and make decisions regarding actions in a connected enterprise system to facilitate energy management goals as well as process control goals in view of electrical control space information and process control space information.

Abstract: A bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes and a diode triggered clamp device in some embodiment. In other embodiments, a bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes with a clamp device merged with a steering diode in each set. The TVS circuit is constructed to realize low capacitance at the protected nodes and improved clamping voltage for robust protection against surge evens. In some embodiments, the TVS circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range. In this manner, the TVS circuit does not present undesirable parasitic capacitance to the data pins being protected, especially when the data pins are applied in high speed applications.

Abstract: According to embodiments of the present invention, a circuit is provided. The circuit includes forming a first electrical device having a first region of a first conductivity type, forming a second electrical device having a second region of a second conductivity type, and electrically coupling the first region and the second region to each other, wherein one of the first and second regions is arranged to at least substantially surround the other of the first and second regions. According to further embodiments of the present invention, a method of forming a circuit is also provided.

Abstract: In a case of a multilayer wiring structure in which an insulating layer provided between wires is made of a material having high transmittance of light in a visible range containing ultraviolet rays, wires in the upper layer and those in a lower layer may be recognized together when defects of an upper layer are visually inspected. In this case, the lower layer may be noise for the inspection of the wires in the upper layer, lowering inspection accuracy. This lowered inspection accuracy has inhibited improvement in manufacturing yields and reliability. In order to solve this issue, a multilayer wiring substrate of the disclosure includes: a substrate; and a first wire and a second wire that are provided on the substrate with an insulating layer having a light transmitting property in between, and one or both of which are subjected to a surface treatment.

Abstract: A three-dimensional memory device includes a substrate, conductive layers and insulating layers, a storage layer, a first channel, a second channel and a first conductive plug. The conductive layers and insulating layers are alternately stacked over the substrate to form a multi-layer stacked structure. The storage layer penetrates through the multi-layer stacked structure, and has a first string portion and a second string portion that are spaced from each other. The first channel is located on a lateral side of the first string portion. The second channel is located on a lateral side of the second string portion. The first channel and the second channel have an upper channel portion and a lower channel portion. The first conductive plug is interconnected between the upper channel portion and the lower channel portion.

Abstract: A display device includes: a substrate on which a plurality of sub-pixels are arranged; a light-emitting device including a light-emitting layer in each of the plurality of sub-pixels; a thin film encapsulation layer covering the light-emitting layer in each of the plurality of sub-pixels; a black matrix around the plurality of sub-pixels; and an optical sensor on the substrate, the optical sensor including a sensing portion for sensing light emitted from a light source, wherein the black matrix has a plurality of openings, through which light emitted from the light source passes, in a path through which the light is received by the sensing portion via an input object which is in contact with the substrate.

Abstract: Systems and methods are described to improve efficiency in the manufacturing of a product for a manufacturer. The system includes a manufacturing route. The manufacturing route specifies at least two dimensions, where a first dimension of the at least two dimensions is a client machine and a second dimension of the at least two dimensions is a process associated with the client machine. A data stream is responsive to the plurality of dimensions. A database is configured to receive the data stream. A processor is configured to provide data from the data stream that indicate a symptom of a problem which can occur within the manufacturing route.

Abstract: A display device includes a substrate that includes a display area and a pad area, and a plurality of data pads that are provided on the pad area of the substrate and arranged along a first direction and a second direction, where the plurality of data pads includes a first data pad, a second data pad that is disposed adjacent to the first data pad along the first direction, a third data pad that is disposed adjacent to the first data pad along the second direction, and a fourth data pad that is disposed adjacent to the second data pad along the second direction, and the first data pad and the second connection wire are respectively disposed in different layers.