Patents Examined by Mohammed Shamsuzzaman
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Patent number: 11189599Abstract: A package includes a first device die, and a second device die bonded to the first device die through hybrid bonding. The second device die is larger than the first device die. A first isolation region encapsulates the first device die therein. The first device die, the second device die, and the first isolation region form parts of a first package. A third device die is bonded to the first package through hybrid bonding. The third device die is larger than the first package. A second isolation region encapsulates the first package therein. The first package, the third device die, and the second isolation region form parts of a second package.Type: GrantFiled: October 1, 2019Date of Patent: November 30, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen
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Patent number: 11189579Abstract: A semiconductor module internally includes semiconductor elements and multilayer substrates on which the semiconductor elements are arranged. The semiconductor module further includes, in a case, fastening portions for fastening a cooler such as conductive radiating fins or water-cooling jackets, for example. In the semiconductor module, side faces of heat radiating plates formed on the rear surface sides of the multilayer substrates are electrically connected to the fastening portions in the case by conductive connectors.Type: GrantFiled: October 1, 2019Date of Patent: November 30, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Satoshi Kaneko, Naoyuki Kanai
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Patent number: 11189611Abstract: An ESD protection semiconductor device includes a substrate. A gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins having a first conductivity type are disposed in the substrate respectively at two sides of the gate set. A first doped fin is disposed in the substrate and positioned in between the source fins and spaced apart from the source fins. The first doped fin comprises a second conductivity type that is complementary to the first conductivity type. A second doped fin is formed in one of the drain fins and isolated from the one of the drain fins by an isolation structure. The second doped fin is electrically connected to the first doped fin.Type: GrantFiled: April 9, 2020Date of Patent: November 30, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Yu Huang, Kuan-Cheng Su, Tien-Hao Tang, Ping-Jui Chen, Po-Ya Lai
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Patent number: 11183508Abstract: Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. The semiconductor device includes a string of transistors stacked in a vertical direction over a substrate of the semiconductor device having a channel structure extending in the vertical direction. The string of transistors includes first, second, and third substrings of transistors that are arranged along first, second, and third portions of the channel structure, respectively. Gate structures of transistors in the first, second, and third substring are separated by respective first, second, and third insulating layers and the second insulating layers have a higher etch rate than that of the third insulating layers.Type: GrantFiled: November 20, 2019Date of Patent: November 23, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Qiguang Wang, Gonglian Wu
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Patent number: 11183579Abstract: Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the method for fabricating semiconductor device may include forming a trench in a substrate; forming a gate dielectric layer over the trench, embedding a first dipole inducing portion in the gate dielectric layer on a lower side of the trench, filling a lower gate over the first dipole inducing portion, embedding a second dipole inducing portion in the gate dielectric layer on an upper side of the trench and forming an upper gate over the lower gate.Type: GrantFiled: November 21, 2019Date of Patent: November 23, 2021Assignee: SK hynix Inc.Inventor: Dong-Soo Kim
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Patent number: 11183555Abstract: A display device including a display area and a non-display area, the display device including a plurality of data wires disposed in the display area and in the non-display area, a plurality of connecting wires disposed in the display area and connected to the data wires, a plurality of dummy patterns disposed in the display area in the same layer as the connecting wires, and shielding patterns disposed on the connecting wires. First gaps are defined between the connecting wires and the dummy patterns, and the shielding patterns overlap with the first gaps.Type: GrantFiled: December 29, 2019Date of Patent: November 23, 2021Inventors: Min Seong Yi, Seung Hwan Cho, Tae Hyun Kim, Jong Hyun Choi
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Patent number: 11177146Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a system for processing a substrate includes a process chamber comprising a first processing volume and a second processing volume; a first heating device configured to heat a substrate to a first temperature; a carrier configured to support the substrate while the substrate is being heated using the first heating device to the first temperature and transfer the substrate to and from each of the first processing volume and the second processing volume; a second heating device configured to maintain the substrate at or near the first temperature; and a chuck configured to receive the substrate from the carrier, and comprising an outer zone and an inner zone having independent variable pressure control to apply a chucking force at the outer zone that is different from a chucking force provided at the inner zone.Type: GrantFiled: October 31, 2019Date of Patent: November 16, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Qi Jie Peng, Chin Wei Tan, Jun-Liang Su, Fang Jie Lim, Sriskantharajah Thirunavukarasu, Arvind Sundarrajan, Puay Han Tan
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Patent number: 11177171Abstract: Integrated chips and methods of forming the same include forming a lower conductive line over an underlying layer. An upper conductive via is formed over the lower conducting lines. An encapsulating layer is formed on the lower conductive line and the upper conductive via using a treatment process that converts an outermost layer of the lower conductive line and the upper conductive via into the encapsulating layer.Type: GrantFiled: October 1, 2019Date of Patent: November 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Oscar van der Straten, Kenneth C. K. Cheng, Joseph F. Maniscalco, Koichi Motoyama
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Patent number: 11171202Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, an active cell field in the body, and a plurality of first and second cells in the active cell field. Each cell is electrically connected to the first load terminal structure and to a drift region. Each first cell includes a mesa having a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each second cell includes a mesa having a port region of the opposite conductivity type electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and has a total extension of less than 100 nm in the direction.Type: GrantFiled: May 13, 2019Date of Patent: November 9, 2021Assignee: Infineon Technologies AGInventors: Anton Mauder, Franz-Josef Niedernostheide, Christian Philipp Sandow
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Patent number: 11171014Abstract: There is provided a substrate processing method, including: forming a silicon nitride film laminated on an etching target film by supplying a film forming gas to a substrate; oxidizing a surface of the silicon nitride film to form an oxide layer by supplying an oxidizing gas to the substrate; and etching the etching target film by supplying an etching gas containing halogen to the substrate, in a state in which the etching target film and the oxide layer are exposed on a surface of the substrate.Type: GrantFiled: June 7, 2018Date of Patent: November 9, 2021Assignee: TOKYO ELECTRON LIMITEDInventors: Hideomi Hane, Kentaro Oshimo, Shimon Otsuki, Jun Ogawa, Noriaki Fukiage, Hiroaki Ikegawa, Yasuo Kobayashi, Takeshi Oyama
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Patent number: 11171117Abstract: Representative techniques and devices including process steps may be employed to form a common interconnection of a multi-die or multi-wafer stack. Each device of the stack includes a conductive pad disposed at a predetermined relative position on a surface of the device. The devices are stacked to vertically align the conductive pads. A through-silicon via is formed that electrically couples the conductive pads of each device of the stack.Type: GrantFiled: June 12, 2019Date of Patent: November 9, 2021Assignee: Invensas Bonding Technologies, Inc.Inventors: Guilian Gao, Belgacem Haba
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Patent number: 11171197Abstract: A display device includes a substrate including a first area, a second area, and a bending area. A plurality of first wires are positioned in the first area. A plurality of second wires are positioned in the second area. An insulating layer is positioned in the bending area. A plurality of connecting wires are disposed on the insulating layer. Each of the connecting wires is connected with at least one of the first wires and at least one of the second wires. Each of the connecting wires includes a first portion and a second portion alternatingly arranged along an extending direction of the connecting wires. A width of the first portion is wider than a width of the second portion in a direction perpendicular to the extending direction each of the connecting wires.Type: GrantFiled: December 3, 2019Date of Patent: November 9, 2021Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Jin-Suk Lee, Seong Ryong Lee
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Patent number: 11164744Abstract: There is provided a method of manufacturing a semiconductor device, comprising forming a film on a substrate in a process chamber by performing a cycle a predetermined number of times. The cycle includes alternately performing supplying a halogen-based first process gas to the substrate in the process chamber, and supplying a non-halogen-based second process gas to the substrate in the process chamber. Further, an internal pressure of the process chamber in the act of supplying the first process gas is set to be higher than an internal pressure of the process chamber in the act of supplying the second process gas.Type: GrantFiled: February 25, 2019Date of Patent: November 2, 2021Assignee: KOKUSAI ELECTRIC CORPORATIONInventors: Yugo Orihashi, Atsushi Moriya
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Patent number: 11158372Abstract: A semiconductor memory device includes a substrate, a controller, a semiconductor memory component, first and second capacitors, and a jumper element. The substrate has a conductor pattern. The conductor pattern includes a first conductor portion and a second conductor portion. The first conductor portion overlaps at least a part of the first capacitor in a thickness direction of the substrate and is electrically connected to the first capacitor. The second conductor portion overlaps at least a part of the second capacitor in the thickness direction of the substrate and is electrically connected to the second capacitor. The first conductor portion and the second conductor portion are separated from each other, and are electrically connected to each other by the jumper element.Type: GrantFiled: March 16, 2020Date of Patent: October 26, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takashi Yamasaki, Shinichi Kikuchi
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Patent number: 11152351Abstract: A bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating optimized collector-base junction realizing avalanche mode breakdown. In some embodiments, the bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating individually optimized collector-base and emitter-base junctions with the optimized junctions being spatially distributed. The optimized collector-base and emitter-base junctions both realize avalanche mode breakdown to improve the breakdown voltage of the transistor. Alternately, a unidirectional transient voltage suppressor is constructed as an NPN bipolar transistor with a PN junction diode connected in parallel in the reverse bias direction to the protected node and incorporating individually optimized collector-base junction of the bipolar transistor and p-n junction of the diode.Type: GrantFiled: June 10, 2020Date of Patent: October 19, 2021Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.Inventor: Shekar Mallikarjunaswamy
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Patent number: 11145626Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.Type: GrantFiled: October 1, 2019Date of Patent: October 12, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Ji Hwan Hwang, Ji Hoon Kim, Ji Seok Hong, Tae Hun Kim, Hyuek Jae Lee
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Patent number: 11139243Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.Type: GrantFiled: June 19, 2019Date of Patent: October 5, 2021Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Chien-Cheng Tsai, Feng-Ming Huang
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Patent number: 11139383Abstract: A process for depositing titanium aluminum or tantalum aluminum thin films comprising nitrogen on a substrate in a reaction space can include at least one deposition cycle. The deposition cycle can include alternately and sequentially contacting the substrate with a vapor phase Ti or Ta precursor and a vapor phase Al precursor. At least one of the vapor phase Ti or Ta precursor and the vapor phase Al precursor may contact the substrate in the presence of a vapor phase nitrogen precursor.Type: GrantFiled: April 15, 2020Date of Patent: October 5, 2021Assignee: ASM IP HOLDING B.V.Inventors: Suvi Haukka, Michael Givens, Eric Shero, Jerry Winkler, Petri Räisänen, Timo Asikainen, Chiyu Zhu, Jaakko Anttila
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Patent number: 11133302Abstract: A microelectronic module that includes a semiconductor carrier including a FET that comprises a serpentine gate electrode having an elongated gate width and gate width-to-gate length ratio in access of 100 wherein resistive, capacitive, and inductive elements are embedded within the structure of the serpentine gate electrode.Type: GrantFiled: November 18, 2019Date of Patent: September 28, 2021Inventor: L. Pierre de Rochemont
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Patent number: 11133418Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.Type: GrantFiled: May 15, 2019Date of Patent: September 28, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yen-Chen Chen, Xiao Wu, Hai Tao Liu, Ming Hua Du, Shouguo Zhang, Yao-Hung Liu, Chin-Fu Lin, Chun-Yuan Wu
