Patents Examined by Mohammed Shamsuzzaman
  • Semiconductor device convex source/drain region
    Patent number: 11127637
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device is provided. The method generally includes forming a recess in a fin, the fin being on a substrate. The recess is proximate a gate structure over the fin. The method includes epitaxially growing a source/drain region in the recess using a remote plasma chemical vapor deposition (RPCVD) process. The RPCVD process includes using a silicon source precursor and a hydrogen carrier gas.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ching Lin, Chii-Horng Li, Chien-I Kuo, Li-Li Su
  • Formation of carbon nanotube-containing devices
    Patent number: 11127903
    Abstract: A method of fabricating a carbon nanotube based device, including forming a trench having a bottom surface and sidewalls on a substrate, selectively depositing a bi-functional compound having two reactive moieties in the trench, wherein a first of the two reactive moieties selectively binds to the bottom surface, converting a second of the two reactive moieties to a diazonium salt; and reacting the diazonium salt with a dispersion of carbon nanotubes to form a carbon nanotube layer bound to the bottom surface of the trench.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: September 21, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Bharat Kumar, George S. Tulevski
  • Method for forming an interconnection structure
    Patent number: 11127627
    Abstract: A method for forming an interconnection structure for a semiconductor device is provided.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: September 21, 2021
    Assignee: IMEC VZW
    Inventors: Frederic Lazzarino, Guillaume Bouche, Juergen Boemmels
  • Metal gate scheme for device and methods of forming
    Patent number: 11127836
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a metal-containing compound over the work function tuning layer, and a metal over the metal-containing compound, wherein the metal-containing compound comprises the metal as an element of the compound.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Chia-Ching Lee, Da-Yuan Lee, Hsueh Wen Tsau
  • FinFET device comprising a single diffusion break with an upper surface that is substantially coplanar with an upper surface of a fin
    Patent number: 11121023
    Abstract: A finFET device is disclosed including a fin defined in a semiconductor substrate, the fin having an upper surface and a first diffusion break positioned in the fin, wherein the first diffusion break comprises an upper surface that is substantially coplanar with the upper surface of the fin.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: September 14, 2021
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Jiehui Shu, Hong Yu, Jinping Liu, Hui Zang
  • High-electron-mobility transistor having a buried field plate
    Patent number: 11114554
    Abstract: A high-electron-mobility semiconductor device includes: a buffer region having first, second and third cross-sections forming a stepped lateral profile, the first cross-section being thicker than the third cross-section and comprising a first buried field plate disposed therein, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections; and a barrier region of substantially uniform thickness extending along the stepped lateral profile of the buffer region, the barrier region being separated from the first buried field plate by a portion of the buffer region. The buffer region is formed by a first semiconductor material and the barrier region is formed by a second semiconductor material.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: September 7, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Clemens Ostermaier, Oliver Häberlen
  • Display device, manufacturing method of display device, and exposure device
    Patent number: 11114522
    Abstract: A display device includes a plurality of picture elements, wherein a first electrode is formed in each of the plurality of picture elements, a cover layer is formed such that an opening of the first electrode is formed, a spacer in a layer identical to the cover layer is provided between two of the first electrodes, the spacer is formed with a height greater than a height of the cover layer, and an outer edge portion of the spacer is spaced from an outer edge portion of the cover layer.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 7, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shinji Ichikawa, Hiroki Taniyama, Shinsuke Saida, Ryosuke Gunji, Tohru Okabe, Yoshihiro Nakada, Hiroharu Jinmura, Akira Inoue
  • Display device
    Patent number: 11114516
    Abstract: Disclosed is a display device possessing: a substrate having a display region and a peripheral region surrounding the display region; a pixel over the display region; a passivation film over the pixel; a resin layer over the passivation film; a first dam over the peripheral region and surrounding the display region; and a second dam surrounding the first dam. The passivation film includes; a first layer containing an inorganic compound; a second layer over the first layer, the second layer containing an organic compound; and a third layer over the second layer, the third layer containing an inorganic compound. The second layer is selectively arranged in a region surrounded by the first dam. The resin layer is selectively arranged in a region surrounded by the second dam.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: September 7, 2021
    Assignee: Japan Display Inc.
    Inventor: Jun Hanari
  • Organic light emitting display device
    Patent number: 11107865
    Abstract: An organic light emitting display device includes a first substrate, a second substrate opposite from the first substrate, a plurality of organic light emitting elements on the first substrate, and a color filter on the organic light emitting elements, wherein a transmission wavelength band of the color filter has an upper limit value for transmitting a light wavelength corresponding to a first intensity of a light emitted from the organic light emitting elements at a viewing angle of about 0°, and has a lower limit value for transmitting a light wavelength corresponding to a second intensity that is less than the first intensity.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: August 31, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jinsook Bang, Sanghoon Yim, Donghoon Kim
  • Solid-state imaging device and method for manufacturing solid-state imaging device, and electronic device
    Patent number: 11088187
    Abstract: A solid-state imaging device includes a first-conductivity-type semiconductor well region, a plurality of pixels each of which is formed on the semiconductor well region and is composed of a photoelectric conversion portion and a pixel transistor, an element isolation region provided between the pixels and in the pixels, and an element isolation region being free from an insulation film and being provided between desired pixel transistors.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: August 10, 2021
    Inventors: Keiji Tatani, Fumihiko Koga, Takashi Nagano
  • Semiconductor devices and fabrication methods thereof
    Patent number: 11081549
    Abstract: A method for fabricating a semiconductor device includes providing a semiconductor structure including a semiconductor substrate, a plurality of semiconductor fin structures, and a trench insulation layer formed on the semiconductor substrate and surrounding each semiconductor fin structure. The semiconductor fin structures include a plurality of first semiconductor fin structures and a plurality of second semiconductor fin structures. The top surface of the trench insulation layer is leveled with the top surface of the semiconductor fin structures.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: August 3, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Semiconductor device including a conductive feature over an active region
    Patent number: 11075164
    Abstract: A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Heng Hsieh, Ting-Wei Chiang, Chung-Te Lin, Hui-Zhong Zhuang, Li-Chun Tien, Sheng-Hsiung Wang
  • Light-emitting device
    Patent number: 11075355
    Abstract: A light-emitting unit (140) is formed over a first surface (102) of a substrate (100). A first terminal (112) and a second terminal (132) are formed on the first surface (102) of the substrate (100), and are electrically connected to the light-emitting unit (140). A sealing layer (200) is formed over the first surface (102) of the substrate (100), and seals the light-emitting unit (140). In addition, the sealing layer (200) does not cover the first terminal (112) and the second terminal (132). A cover layer (210) is formed over the sealing layer (200), and is formed of a material different from that of the cover layer (210). In at least a portion of a region located next to the first terminal (112) and a region located next to the second terminal (132), a portion of an end of the cover layer (210) protrudes from the sealing layer (200).
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: July 27, 2021
    Assignees: PIONEER CORPORATION, TOHOKU PIONEER CORPORATION
    Inventors: Hirotsugi Hatakeyama, Shinsuke Tanaka, Shinji Nakajima
  • Glass substrate for display and method for producing same
    Patent number: 11069716
    Abstract: Provided are: a glass substrate that achieves a high strain point while having a low devitrification temperature; and a method for producing said glass substrate. This glass substrate for a display is made of a glass comprising SiO2 and Al2O3, comprising 0% or more to less than 3% B2O3 and from 5 to 14% BaO in mass %, and substantially devoiding Sb2O3, wherein the devitrification temperature is 1235° C. or lower and the strain point is 720° C. or higher. Alternatively, this glass substrate for a display is made of a glass comprising SiO2 and Al2O3, comprising 0% or more to less than 3% B2O3, 1.8% or more MgO, and from 5 to 14% BaO in mass %, and substantially devoiding Sb2O3, wherein (SiO2+MgO+CaO)—(Al2O3+SrO+BaO) is less than 42%, the devitrification temperature is 1260° C. or lower, and the strain point is 720° C. or higher.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: July 20, 2021
    Assignee: AvanStrate Inc.
    Inventor: Manabu Ichikawa
  • Maintenance assistance system and maintenance assistance method for railroad ground equipment
    Patent number: 11066087
    Abstract: An object is to improve the accuracy of prediction of deterioration of railroad ground equipment.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: July 20, 2021
    Assignee: HITACHI, LTD.
    Inventors: Kojin Yano, Tomohito Takai, Toshihiro Eguchi
  • Chip-on-film package, display panel, and display device
    Patent number: 11056027
    Abstract: A chip-on-film package includes a base substrate on which a first pad region, a second pad region, and a third region located between the first pad region and the second pad region are defined, a dummy pad disposed on the first pad region, input pads disposed on the first pad region, output pads disposed on the second region, a first detection line disposed on the base substrate, and a second detection line disposed on the base substrate. The first detection line is connected to a first input pad and a second input pad via the second pad region to form a first loop between the first input pad and the second input pad, and the second detection line is connected to the dummy pad and the first detection line via the third region to form a second loop between the dummy pad and the first input pad.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: July 6, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hee-Kwon Lee, Seungkyun Hong
  • Floating base silicon controlled rectifier
    Patent number: 11056481
    Abstract: A floating base silicon controlled rectifier is provided, which at least comprises a first conductivity type layer; a second conductivity type well formed in the first conductivity type layer; a first conductivity type heavily doped region coupled to a first node and formed in the second conductivity type well; and a second conductivity type heavily doped region coupled to a second node and formed in the first conductivity type layer. The first conductivity type and the second conductivity type are opposite. When the first conductivity type is N type, the second conductivity type is P type. Alternatively, when the first conductivity type is P type, the second conductivity type is N type. By employing the proposed present invention, the floating base silicon controlled rectifier acts as a forward diode, and an input capacitance can be greatly reduced.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: July 6, 2021
    Assignee: AMAZING MICROELECTRONIC CORP.
    Inventors: Chih-Ting Yeh, Che-Hao Chuang
  • SiC freestanding film structure
    Patent number: 11049747
    Abstract: A SiC Freestanding Film Structure capable of preventing a functional surface of a SiC Freestanding Film Structure from being affected by a film thickness and improving strength by increasing the film thickness, the SiC Freestanding Film Structure is formed by depositing a SiC layer through a vapor deposition type film formation method. The SiC layer is deposited with respect to a first SiC layer serving as a functional surface in the SiC Freestanding Film Structure. Focusing on the functional surface and a non-functional surface positioned on front and back sides of any particular portion, the functional surface has smoothness higher than that of the non-functional surface.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: June 29, 2021
    Assignee: ADMAP INC.
    Inventor: Satoshi Kawamoto
  • Route based manufacturing system analysis, apparatuses, systems, and methods
    Patent number: 11036212
    Abstract: Systems and methods are described to improve efficiency in the manufacturing of a product for a manufacturer. The system includes a manufacturing route. The manufacturing route specifies at least two dimensions, where a first dimension of the at least two dimensions is a client machine and a second dimension of the at least two dimensions is a process associated with the client machine. A data stream is responsive to the plurality of dimensions. A database is configured to receive the data stream. A processor is configured to provide data from the data stream that indicates a symptom of a problem which can occur within the manufacturing route.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: June 15, 2021
    Assignee: SCHEMAPORT, LLC
    Inventor: Steven Clair Hugh
  • Semiconductor device
    Patent number: 11037988
    Abstract: A semiconductor device includes a first memory cell, a second memory cell, a first capping film, and a second capping film. The first memory cell includes a first ovonic threshold switch (OTS) on a first phase change memory. The second memory cell includes a second OTS on a second phase change memory. The first capping film is on side surfaces of the first and second memory cells. The second capping film is on the first capping film and fills a space between the first and second memory cells.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Uk Kim, Jeong Hee Park, Seong Geon Park, Soon Oh Park, Jung Moo Lee