Patents Examined by Mohsen Ahmadi
  • Patent number: 10388846
    Abstract: A method for forming a densified solid object corresponding to a thermoelectric element from a mixture of uncompressed, powdered constituent materials. A powdered precursor material may be selected to cause a shrinkage of at least twenty percent in at least two mutually orthogonal linear dimensions of a densified solid object compared to corresponding dimensions of a mold cavity. In some embodiments, a precursor material is selected to produce a thermoelectric material having electrical and mechanical properties suitable for a thermoelectric module. In some embodiments, at least two thermoelectric elements are electrically connected to conductive plates to form a thermoelectric module.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: August 20, 2019
    Assignee: MATRIX INDUSTRIES, INC.
    Inventors: Andrew C. Miner, Kathryn E. Alexander
  • Patent number: 10388781
    Abstract: A bi-directional switch device includes two inter-digitated back-to-back vertical metal oxide semiconductor field effect transistors (MOSFETs) formed on a substrate with their drains connected together, but otherwise isolated from each other.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: August 20, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Madhur Bobde, Sik Lui, Ji Pan
  • Patent number: 10381259
    Abstract: A method of fabricating a semiconductor structure includes forming an isolation feature in a substrate, removing a portion of the isolation feature and a portion of the substrate underneath the removed portion of the isolation feature to form a trench in the substrate, and forming a trapping feature around a bottom portion of the trench. A first sidewall and a second sidewall of the trench are in direct contact with the isolation feature, and a bottom surface of the trench is below a bottom surface of the isolation feature.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: August 13, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Alex Kalnitsky, Chih-Wen Yao, Jun Cai, Ruey-Hsin Liu, Hsiao-Chin Tuan
  • Patent number: 10374060
    Abstract: Techniques for forming VFET bottom source and drain epitaxy with anchors are provided. In one aspect, a method of forming a VFET device includes: patterning at least one fin in a substrate; forming anchors on opposite ends of the at least one fin; laterally etching a base of the at least one fin, wherein the anchors prevent the lateral etching from being performed on the ends of the at least one fin; forming bottom source and drains at the base of the at least one fin between the anchors; removing the anchors; forming bottom spacers on the bottom source and drains; forming gates above the bottom spacers alongside the at least one fin; forming top spacers above the gates; and forming top source and drains above the top spacers at a top of the at least one fin. VFET devices are also provided.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Tenko Yamashita
  • Patent number: 10361248
    Abstract: A pixel of a light emitting diode module, display panel or other device, may comprise different colored sub-pixels, where one of the sub-pixels comprises a wavelength converting material, such as phosphor, to convert light emitted from an associated light emitting diode of that sub-pixel into a color other than the main color of light emitted from that sub-pixel. The wavelength converting material may have an amount selected to tune the color coordinates of the pixel. The amount of wavelength converting material may be determined in response to measuring the intensity of the spectrum of light emitted by the light emitting diode of the sub-pixel, or similarly manufactured sub-pixels, on which the wavelength converting material is to be formed. Methods of manufacturing the same are also disclosed.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: July 23, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin Sub Lee, Han Kyu Seong, Yong Il Kim, Jung Sub Kim, Seul Gee Lee
  • Patent number: 10361219
    Abstract: A silicon-on-insulator substrate which includes a semiconductor substrate, a buried oxide layer, and a semiconductor layer is provided. A hard mask layer is formed over a first region of the silicon-on-insulator substrate. A first silicon-germanium layer is epitaxially grown on the semiconductor layer within a second region of the silicon-on-insulator substrate. The second region is at least a portion of the semiconductor layer not covered by the hard mask layer. A thermal annealing process is performed, such that germanium atoms from the first silicon-germanium layer are migrated to the portion of the semiconductor layer to form a second silicon-germanium layer. The hard mask layer is removed. A layer of semiconductor material is epitaxially grown on top of the semiconductor layer and the second silicon-germanium layer, where the layer of semiconductor material composed of the same material as semiconductor layer.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Leland Chang, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 10361188
    Abstract: An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: July 23, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Jean Jimenez
  • Patent number: 10347669
    Abstract: A flexible display device and a method for manufacturing the same are provided. The method includes providing a rigid sheet having cutting streets, forming a protective pattern on the rigid sheet, the protective pattern covering the cutting streets, and forming a flexible substrate including a reserved region and an unreserved region on the rigid sheet provided with the protective pattern, where the flexible substrate covers the protective pattern, and boundaries between the reserved region and the unreserved region are within regions occupied by the cutting streets. The method further includes fabricating a display component on the flexible substrate in the reserved region, and cutting the flexible substrate along the cutting streets, removing the unreserved region of the flexible substrate and reserving the reserved region of the flexible substrate, incisions caused by cutting being within a region of the protective pattern, and separating the cut flexible substrate from the rigid sheet.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: July 9, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chunyan Xie, Mingche Hsieh
  • Patent number: 10347795
    Abstract: A light emitting diode package structure including a base, a light emitting diode and an encapsulant is provided. The light emitting diode is disposed on a surface of the base and is adapted to generate and emit a light. The encapsulant is disposed on the base and encapsulates the light emitting diode. The encapsulant has a surface parallel to the surface of the base and a plurality of surfaces perpendicular to the surface of the base. The light, after passing through the surface of the encapsulant parallel to the surface of the base, has a first light intensity. The light, after passing through the surfaces of the encapsulant perpendicular to the surface of the base, has a second light intensity. The first light intensity is greater than the second light intensity. In addition, a manufacturing method of a light emitting diode package structure is also provided.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: July 9, 2019
    Assignee: Everlight Electronics Co., Ltd.
    Inventors: Yu-Hsuan Chen, Ming-Kuei Wu
  • Patent number: 10347508
    Abstract: A method includes applying a die attach material to a die pad of an integrated circuit. The die attach material is employed as a bonding material to the die pad. The method includes mounting an integrated circuit die to the die pad of the integrated circuit via the die attach material. The method includes printing an adhesion deposition material on the die attach material appearing at the interface of the integrated circuit die and the die pad of the integrated circuit to mitigate delamination between the integrated circuit die and the die pad.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: July 9, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yong Lin, Rongwei Zhang, Benjamin Stassen Cook, Abram Castro
  • Patent number: 10340379
    Abstract: A semiconductor device according to an embodiment is provided with a plurality of active barrier sections each of which is enclosed by a plurality of element isolation sections each of which is configured of a closed pattern. Namely, the plurality of active barrier sections are electrically isolated from each other.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: July 2, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Keiichi Furuya
  • Patent number: 10340455
    Abstract: The present disclosure provides a method for manufacturing a mask plate assembly, which includes providing a mask plate and a frame and securing the mask plate to the frame. The secured mask plate comprises a redundant portion extending out of the frame. The method further comprises removing at least a part of the redundant portion, and dispensing glue in a predetermined area of a surface of the mask plate, and curing the glue to form a colloid, wherein the colloid is higher than any other area on the surface of the mask plate where the colloid is not formed. The present disclosure further provides a mask plate assembly comprising a frame, and a mask plate secured to the frame, wherein a colloid is formed in a predetermined area of a surface of the mask plate, and the colloid is higher than any other area on the surface of the mask plate where the colloid is not formed. The present disclosure further provides an evaporation device and a method for manufacturing the display substrate.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: July 2, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Can Zhang, Yinan Liang
  • Patent number: 10340193
    Abstract: A fin field-effect transistor is provided. The fin field-effect transistor includes a substrate, a fin structure, a gate-stacked structure, and an isolation structure. The fin structure is disposed on the substrate, and the gate-stacked structure covers the fin structure. The isolation structure disposed on the substrate to isolate the gate-stacked structure from the substrate has different thicknesses in different portions.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: July 2, 2019
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Ta-Hsun Yeh, Cheng-Wei Luo, Hsiao-Tsung Yen, Yuh-Sheng Jean
  • Patent number: 10332825
    Abstract: In one implementation, a semiconductor package includes an integrated circuit (IC) flip chip mounted on a first patterned conductive carrier, a second patterned conductive carrier situated over the IC, and a magnetic material situated over the second patterned conductive carrier. The semiconductor package also includes a third patterned conductive carrier situated over the magnetic material. The second patterned conductive carrier and the third patterned conductive carrier are electrically coupled so as to form windings of an integrated inductor in the semiconductor package.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: June 25, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Parviz Parto
  • Patent number: 10333008
    Abstract: Embodiments of the present disclosure provide for methods of making substrates having an antireflective layer, substrates having an antireflective layer, devices including a substrate having an antireflective layer, and the like.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: June 25, 2019
    Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC.
    Inventors: Peng Jiang, Khalid Askar, Jiamin Wang, Christopher Kim
  • Patent number: 10332964
    Abstract: A single poly electrical erasable programmable read only memory (EEPROM) includes a source, a drain, a dielectric layer and an electrode layer. The source and the drain are located in a substrate, wherein the source and the drain have a first conductive type. The dielectric layer is disposed on the substrate and between the source and the drain, wherein the dielectric layer includes a first dielectric layer having two tunnel dielectric parts separating from each other, and thicknesses of the two tunnel dielectric parts are thinner than thicknesses of the other parts of the first dielectric layer. The electrode layer is disposed on the dielectric layer, wherein the electrode layer includes a first electrode disposed on the first dielectric layer, thereby the first electrode being a floating gate.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: June 25, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Haw Lee, Tzu-Ping Chen
  • Patent number: 10325858
    Abstract: A semiconductor device chip includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a semiconductor device disposed on the first surface of the semiconductor substrate, an interconnect pattern having an end connected to the semiconductor device and another end exposed on a surface of a function layer disposed on the first surface of the semiconductor substrate, plurality of external connection electrodes mounted on the surface of the function layer and electrically connected to the other end of the interconnect pattern, an electromagnetic wave shield film for shielding electromagnetic waves, which is disposed on the second surface of the semiconductor substrate and side surfaces of the function layer, and a ground interconnect electrically connected to the electromagnetic shield film and disposed on the function layer.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: June 18, 2019
    Assignee: DISCO CORPORATION
    Inventor: Katsuhiko Suzuki
  • Patent number: 10326098
    Abstract: An organic light-emitting diode is disclosed. In an embodiment, the diode includes a first light-emitting segment and at least a second light-emitting segment, wherein the first and second light-emitting segments include a common first electrode and a common second electrode, and are configured to emit radiation with different brightnesses, wherein the first electrode includes at least one separating line that does not completely cut through the first electrode, wherein an electric conductivity of the first electrode is reduced in a region of the separating line, wherein the separating line separates the first light-emitting segment from the second light-emitting segment, and wherein the second light-emitting segment has a lower brightness during operation than the first light-emitting segment.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: June 18, 2019
    Assignee: OSRAM OLED GMBH
    Inventors: Karsten Diekmann, Andrew Ingle, Jörg Farrnbacher
  • Patent number: 10319940
    Abstract: An organic EL display device includes a rectangular first substrate, an organic EL diode unit formed on the first substrate, a rectangular second substrate formed on the organic EL diode unit, a frame-shaped adhesive section configured to attach the first substrate to the second substrate to surround the organic EL diode unit, an extraction interconnection group constituted by a plurality of extraction interconnections extracted from the organic EL diode unit, and a dummy interconnection group formed at an adhesive region at which the adhesive section of the first substrate is attached and constituted by a plurality of dummy interconnections that are separated from each other, wherein the extraction interconnection and the dummy interconnection cross the adhesive section in the same direction.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: June 11, 2019
    Assignee: FUTABA CORPORATION
    Inventors: Shinji Ide, Ikuo Ohmori, Nobuko Hayakawa
  • Patent number: 10319678
    Abstract: A three dimensional or stacked circuit device includes a conductive channel cap on a conductor channel. The channel cap can be created via selective deposition or other process to prevent polishing down the conductive material to isolate the contacts. The conductor channel extends through a deck of multiple tiers of circuit elements that are activated via a gate. The gate is activated by electrical potential in the conductor channel. The conductive cap on the conductor channel can electrically connect the conductor channel to a bitline or other signal line, and/or to another deck of multiple circuit elements.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Hongqi Li, Gowrisankar Damarla, Roger Lindsay, Zailong Bian, Jin Lu, Shyam Ramalingam, Prasanna Srinivasan