Patents Examined by Molly Reida
  • Patent number: 10475759
    Abstract: An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface. The first die is attached to the first surface of the substrate by first electrical connectors. The second die is attached to the first surface of the substrate by second electrical connectors. A size of one of the second electrical connectors is smaller than a size of one of the first electrical connectors.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Chen-Hua Yu, Jing-Cheng Lin
  • Patent number: 10367001
    Abstract: Provided herein a semiconductor device including a stack including conductive layers and insulating layers that are alternately stacked, and a slit insulating layer passing through the stack in a stacking direction, the slit insulating layer including a first main pattern extending in a first direction, and a first protruding pattern protruding in a second direction crossing the first direction at an end of the first main pattern.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: July 30, 2019
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seok Min Jeon
  • Patent number: 10269834
    Abstract: A pixel structure for use in a display panel includes a switching element and a storage capacitor. The switching element has a drain electrode and a source electrode disposed on a high-k dielectric layer with k being equal to or higher than 8. The storage capacitor has a first capacitor electrode, a second capacitor electrode and a third capacitor electrode, wherein a passivation layer is disposed between the second an third capacitor electrodes and the high-k dielectric layer is also disposed between the first and second capacitor electrodes. The pixel structure also has a common line connected to the first capacitor electrode, a source line, and a gate line arranged such that the source line, the gate line and the common line may cross over each other over a low-k dielectric layer at a cross-over area where k is equal to or lower than 5.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: April 23, 2019
    Assignee: A.U. Vista, Inc.
    Inventors: Fang-Chen Luo, Willem Den Boer, Hsiang-Lin Lin
  • Patent number: 10186585
    Abstract: A semiconductor device which can reduce power consumption and a method for manufacturing the same are provided. A semiconductor device comprises an Si (silicon) substrate, an SiC (silicon carbide) layer formed on the surface of the Si substrate, an AlN (aluminum nitride) layer formed on the surface of the SiC layer, an n-type GaN (gallium nitride) layer formed on the surface of the AlN layer, a first electrode formed at the surface side of the GaN layer, and a second electrode formed at the reverse face side of the Si substrate 1. The magnitude of electrical current which flows between the first electrode and the second electrode depends on electrical voltage between the first electrode and the second electrode.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: January 22, 2019
    Assignee: Air Water Inc.
    Inventors: Akira Fukazawa, Sumito Ouchi
  • Patent number: 10163630
    Abstract: The present disclosure generally relates to methods for removing contaminants and native oxides from substrate surfaces. The method includes exposing a surface of the substrate to first hydrogen radical species, wherein the substrate is silicon germanium having a concentration of germanium above about 30%, then exposing the surface of the substrate to a plasma formed from a fluorine-containing precursor and a hydrogen-containing precursor, and then exposing the surface of the substrate to second hydrogen radical species.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: December 25, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bo Zheng, Avgerinos V. Gelatos, Anshul Vyas, Raymond Hoiman Hung
  • Patent number: 10158039
    Abstract: A semiconductor device is formed using an n-type layer of Zinc Oxide, a p-type layer formed of a narrow bandgap material. The narrow bandgap material uses a group 3A element and a group 5A element. A junction is formed between the n-type layer and the p-type layer, the junction being operable as a heterojunction diode having a rectifying property at a temperature range, the temperature range having a high limit at room temperature.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: December 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel P. De Souza, Yun Seog Lee, Ning Li, Devendra Sadana, Yao Yao
  • Patent number: 10157798
    Abstract: A method for forming a semiconductor device includes forming a semiconductor fin over a surface of a substrate and forming sacrificial spacers on first and second sides of the semiconductor fin. The first side opposes the second side. The method includes recessing the surface to expose second and third surfaces, recessing the second surface to form a first cavity between the sacrificial spacers and the substrate on the first side, and recessing the third surface to form a second cavity between the sacrificial spacers and the substrate on the second side. The method includes forming a first bottom spacer in the first cavity and forming a second bottom spacer in the second cavity. A thickness of the first bottom spacer in a direction between the sacrificial spacers and the substrate is substantially equal to a thickness of the second bottom spacer in the same direction.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: December 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng Chi, Min Gyu Sung, Ruilong Xie, Tenko Yamashita
  • Patent number: 10157736
    Abstract: Methods and apparatuses suitable for depositing low hydrogen content, hermetic, thin encapsulation layers at temperatures less than about 300° C. are provided herein. Methods involve pulsing plasma while exposing a substrate to deposition reactants, and post-treating deposited encapsulation films to densify and reduce hydrogen content. Post-treatment methods include periodic exposure to inert plasma without reactants and exposure to ultraviolet radiation at a substrate temperature less than about 300° C.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: December 18, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Bart J. van Schravendijk, Akhil Singhal, Joseph Hung-chi Wei, Bhadri N. Varadarajan, Kevin M. McLaughlin, Casey Holder, Ananda K. Banerji
  • Patent number: 10153220
    Abstract: A packaged electronic system comprises a slab (210) of low-grade silicon (l-g-Si) configured as ridges (114) framing a depression of depth (112) including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals (209b) connected to attachment pads in the central area; and semiconductor chips (120, 130) having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: December 11, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Thomas Eugene Grebs, Simon John Molloy
  • Patent number: 10153411
    Abstract: A light emitting device includes a package having a recess which includes a bottom surface and an inner peripheral surface around a periphery of the bottom surface. The package includes a first lead to define a first part of the bottom surface, a second lead to define a second part of the bottom surface, and a resin body to provide the inner peripheral surface and a remaining part of the bottom surface. The bottom surface includes a light emitting element mounting region in the first part and a groove surrounding the light emitting element mounting region. A light emitting element is mounted on the light emitting element mounting region. A light-transmissive resin is provided in the recess to be in at least a part of a groove surface. A light reflecting resin is provided between the inner peripheral surface of the recess and the light-transmissive resin.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: December 11, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Ryoji Naka, Atsushi Bando, Tomohide Miki, Kimihiro Miyamoto
  • Patent number: 10141229
    Abstract: In fully depleted SOI transistors, specifically designed semiconductor materials may be provided for different types of transistors, thereby, for instance, enabling a reduction of hot carrier injection in transistors that are required to be operated at a moderately high operating voltage. To this end, well-controllable epitaxial growth techniques may be applied selectively for one type of transistor, while not unduly affecting the adjustment of material characteristics of a different type of transistor.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 27, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jürgen Faul, Thorsten Kammler
  • Patent number: 10134828
    Abstract: A display device according to an embodiment of the present invention includes: a base material including a display region, and a peripheral region which is located outside the display region, at least a part of the peripheral region being a bending region; an insulating layer that is disposed on the base material, extends from the display region to a part of the peripheral region, and is located apart from an edge of the base material; at least one level difference moderating layer that is disposed under the insulating layer and extends from an edge of the insulating layer toward a side of the bending region; and at least one wiring disposed on the insulating layer and the at least one level difference moderating layer.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: November 20, 2018
    Assignee: Japan Display Inc.
    Inventor: Masumi Nishimura
  • Patent number: 10134919
    Abstract: A vertical flash memory includes a plurality of vertical memory cells, wherein each of the vertical memory cells includes a selective gate, a main gate, a dielectric interlayer and a vertical channel layer. The selective gate is disposed on a substrate. The main gate is stacked on the selective gate. The dielectric interlayer isolates the main gate from the selective gate. The vertical channel layer is disposed on sidewalls of the selective gate and the main gate. The present invention also provides a method of forming said vertical flash memory.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: November 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Tsung-Lin Wu
  • Patent number: 10128292
    Abstract: A method can be used to manufacture a charge storage cell with a first trench and a second trench in a substrate material. The first trench is filled with a doped material. The second trench is filled with a second trench material. The method includes causing the dopant to diffuse from the first trench to thereby provide a doped region adjacent to the first trench. The material from the first and second trenches is removed and at least one of the trenches is filled with a capacitive deep trench isolation material to provide capacitive deep trench isolation.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: November 13, 2018
    Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventor: Laurence Stark
  • Patent number: 10128148
    Abstract: Methods for fabricating semiconductor devices may provide enhanced performance and reliability by recovering quality of a low-k insulating film damaged by a plasma process. A method may include forming a first interlayer insulating film having a trench therein on a substrate, filling at least a portion of the trench with a metal wiring region, exposing a surface of the metal wiring region and a surface of the first interlayer insulating film to a plasma in a first surface treatment process, then exposing the surface of the first interlayer insulating film to a recovery gas containing a methyl group (—CH3) in a second surface treatment process, and then forming an etch stop layer on the metal wiring region and the first interlayer insulating film.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: November 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Viet Ha Nguyen, Nae In Lee, Thomas Oszinda, Byung Hee Kim, Jong Min Baek, Tae Jin Yim
  • Patent number: 10128192
    Abstract: A semiconductor package structure including a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto is provided. The RDL structure includes an inter-metal dielectric (IMD) layer and a first conductive layer disposed at a first layer-level of the IMD layer. A molding compound covers the first surface of the RDL structure. A first semiconductor die is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: November 13, 2018
    Assignee: MEDIATEK INC.
    Inventors: Min-Chen Lin, Che-Ya Chou, Nan-Cheng Chen
  • Patent number: 10128308
    Abstract: The present invention relates to a puzzle-type micro light emitting diode (LED) display device which is capable of implementing a display having various sizes, the micro LED display device including: a micro LED panel in which a plurality of micro LED pixels is arranged in rows and columns; and a micro LED driving substrate (backplane) configured to include an active matrix (AM) circuit unit including a plurality of CMOS cells corresponding to the plurality of micro LED pixels, and a control circuit unit disposed in an outer region of the AM circuit unit, in which the control circuit unit is disposed to be adjacent to two sides among four sides of the micro LED panel.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: November 13, 2018
    Assignee: LUMENS CO., LTD.
    Inventors: Eun Sung Shin, Dong Hee Cho, Yong Pil Kim, Myung Ji Moon, Han Beet Chang, Jae Soon Park
  • Patent number: 10128345
    Abstract: A semiconductor device including a semiconductor element, an upper-surface electrode provided on an upper surface of the semiconductor element, a plated layer provided on an upper surface of the upper-surface electrode, one or more gate runners penetrating the plated layer and provided to extend in a predetermined direction on the upper surface of the semiconductor element, and a metal connecting plate that is arranged above the plated layer and is electrically connected to the upper-surface electrode, wherein the metal connecting plate has a joint portion parallel to the upper surface of the semiconductor element and has a rising portion that is connected to a first end of the joint portion and extends in a direction away from the upper surface of the semiconductor element, and in a plane parallel to the upper surface of the semiconductor element, the rising portion and the gate runner do not overlap with each other.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: November 13, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Hiromichi Gohara, Takafumi Yamada, Kohei Yamauchi, Tatsuhiko Asai, Yoshitaka Nishimura, Akio Kitamura, Hajime Masubuchi, Souichi Yoshida
  • Patent number: 10121716
    Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: November 6, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Tom Grebs, Simon John Molloy
  • Patent number: 10115875
    Abstract: A method of manufacturing a light emitting device that includes a plurality of light emitting parts is provided. The method includes providing a base member having a plurality of recesses; mounting at least one light-emitting element in each of the plurality of recesses; disposing a light-transmissive layer continuously covering the plurality of recesses; and removing portions of the light-transmissive layer on the lateral wall between adjacent recesses to expose corresponding portions of the lateral wall, to obtain a plurality of light-transmissive members.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: October 30, 2018
    Assignee: NICHIA CORPORATION
    Inventor: Takeo Kurimoto