Abstract: A semiconductor memory structure includes a substrate including a memory cell region and a cell edge region adjacent to the memory cell region. Active regions are formed in the substrate and in the memory cell region and the cell edge region. At least a dummy bit line is formed on the active regions in the cell edge region. The dummy bit line extends along a first direction and overlaps at least two active regions along a second direction. The dummy bit line further includes a first inner line portion and an outer line portion. The first inner line portion and the outer line portion extend along the first direction and a width of the first inner line portion is different from a width of the outer line portion.

Abstract: In one embodiment the organic light-emitting diode includes a substrate having a substrate upper side, an electrically conductive grid structure for a current distribution and an electrically conductive particle layer, which are located at the substrate upper side. The grid structure may be embedded in the particle layer. An organic layer sequence for generating the radiation is located directly on the particle layer. A covering electrode is attached to the organic layer sequence. The particle layer comprises scattering particles having a first average diameter and electrically conductive particles having a smaller second average diameter. The scattering particles are densely packed together with the conductive particles. The particle layer forms, together with the grid structure, a substrate electrode for the organic layer sequence.

Abstract: An LED light-emission device includes a substrate, an LED chip, a phosphor-containing resin containing a phosphor and covering the LED chip, and a diffusing agent-containing resin containing a diffusing agent that diffuses light emitted from the phosphor-containing resin and sealing the phosphor-containing resin. The LED chip, the phosphor-containing resin, and the diffusing agent-containing resin are placed on a same flat face of the substrate.

Abstract: A method of manufacturing a nitride semiconductor substrate includes providing a silicon substrate having a first surface and a second surface opposing each other, growing a nitride template on the first surface of the silicon substrate in a first growth chamber, in which a silicon compound layer is formed on the second surface of the silicon substrate in a growth process of the nitride template, removing the silicon compound layer from the second surface of the silicon substrate, growing a group III nitride single crystal on the nitride template in a second growth chamber, and removing the silicon substrate from the second growth chamber.

Abstract: A method of manufacturing an OLED display is disclosed. In one aspect, the method includes providing a donor substrate including a material formed on one surface thereof and heating the material so as to form a barrier thin-film on the donor substrate. The method also includes providing an acceptor substrate and a substrate attached to the acceptor substrate, forming an OLED unit over the substrate, bonding the OLED unit and the barrier thin-film together, and irradiating a laser beam on the barrier thin-film so as to delaminate the donor substrate from the barrier thin-film.

Abstract: A method, in one embodiment, can include forming a core trench and a termination trench in a substrate. The termination trench is wider than the core trench. In addition, a first oxide can be deposited that fills the core trench and lines the sidewalls and bottom of the termination trench. A first polysilicon can be deposited into the termination trench. A second oxide can be deposited above the first polysilicon. A mask can be deposited above the second oxide and the termination trench. The first oxide can be removed from the core trench. A third oxide can be deposited that lines the sidewalls and bottom of the core trench. The first oxide within the termination trench is thicker than the third oxide within the core trench.

Abstract: The present disclosure relates to a method for manufacturing a self-assembled nano-scale LED electrode assembly and more particularly, to a method for manufacturing a self-assembled nano-scale LED electrode assembly in which a nano-scale LED device can be self-aligned on two different electrodes without being chemically and physically damaged and the number of nano-scale LED devices to be mounted can be remarkably increased, and alignment and electrical connection of the LED devices can be further improved.

Abstract: A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (RRAM) elements. The first electrode and the two second electrodes are disposed in a horizontal plane. The first electrode is disposed between the two second electrodes. The first electrode and the two second electrodes are disposed in parallel. The first electrode is coupled to a source region of the transistor. One of the two RRAM elements is disposed between the first electrode and one of the two second electrodes. The other one of the two RRAM elements is disposed between the first electrode and the other one of the two second electrodes.

Abstract: The present invention relates to a method for manufacturing a light extraction substrate for an organic light emitting element, a light extraction substrate for an organic light emitting element, and an organic light emitting element that includes the same and, more specifically, to a method for manufacturing a light extraction substrate for an organic light emitting element, a light extraction substrate for an organic light emitting element, and an organic light emitting element that includes the same, which can enhance the light extraction efficiency of an organic light emitting element and, in particular, can reduce the process cost.

Abstract: According to one embodiment, a method is disclosed for manufacturing an integrated circuit device, the method can include forming a mask member on a first film, the mask member having a pattern, performing a first etching on the first film using the mask member as a mask to form a recessed section in the first film, forming a second film covering an inner side surface of the recessed section. The second film has a film thickness of preventing blockage of the recessed section, and performing a second etching on the second film and the first film via the recessed section. The performing of the second etching includes performing a third etching in a condition of an etching rate at a place smaller in curvature radius in the recessed section being lower than an etching rate at a place larger in curvature radius in the recessed section.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first semiconductor layer, an insulating layer, and a second semiconductor layer; forming an active device on the substrate; forming an interlayer dielectric (ILD) layer on the substrate and the active device; forming a mask layer on the ILD layer; removing part of the mask layer, part of the ILD layer, and part of the insulating layer to form a first contact hole; forming a patterned mask on the mask layer and into the first contact hole; and removing part of the mask layer and part of the ILD layer to form a second contact hole exposing part of the active device.

Abstract: A thin film transistor including a gate electrode, a semiconductor layer, a gate insulating layer, a source electrode, a drain electrode and a graphene pattern. The semiconductor layer overlaps with the gate electrode. The gate insulating layer is disposed between the gate electrode and the semiconductor layer. The source electrode overlaps with the semiconductor layer. The drain electrode overlaps with the semiconductor layer. The drain electrode is spaced apart from the source electrode. The graphene pattern is disposed between the semiconductor layer and at least one of the source electrode and the drain electrode.

Abstract: A power electronic substrate includes a metallic baseplate having a first and second surface opposing each other. An electrically insulative layer also has first and second surfaces opposing each other, its first surface coupled to the second surface of the metallic baseplate. A plurality of metallic traces each include first and second surfaces opposing each other, their first surfaces coupled to the second surface of the electrically insulative layer. At least one of the metallic traces has a thickness measured along a direction perpendicular to the second surface of the metallic baseplate that is greater than a thickness of another one of the metallic traces also measured along a direction perpendicular to the second surface of the metallic baseplate. In implementations the electrically insulative layer is an epoxy or a ceramic material. In implementations the metallic traces are copper and are plated with a nickel layer at their second surfaces.

Abstract: The present invention provides a method for manufacturing a TFT substrate, in which after induced crystallization is conducted by implanting ions into an amorphous silicon layer, there is no need to completely remove the ion induction layer formed on the surface of a poly-silicon layer so obtained and instead, a half-tone mask based operation is applied to remove only a portion of the ion induction layer corresponding to a channel zone and there is no need for re-conducting ion implantation subsequently for source/drain contact zones, thereby saving the mask necessary for re-conducting ion implantation. Further, the source/drain electrodes are also formed with the half-tone mask based operation so as to save the mask necessary for making the source/drain electrodes. Further, the source/drain electrodes are formed first so that the formation of an interlayer insulation layer can be omitted thereby saving the mask necessary for forming the interlayer insulation layer.

Abstract: A semiconductor device may include a semiconductor substrate in which a semiconductor element is provided, and an insulation film provided on the semiconductor substrate, in which the semiconductor substrate may include a first portion and a second portion which has a thickness thinner than a thickness of the first portion, an upper surface of the second portion may be positioned lower than an upper surface of the first portion, a recess extending in a thickness direction of the semiconductor substrate may be provided on the upper surface of the second portion located at a position where the first portion and the second portion adjoin to each other, and the insulation film may extend over from the first portion to the second portion, and fill the recess.

Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.

Abstract: Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer.

Abstract: A semiconductor memory structure includes a substrate including a memory cell region, a peripheral circuit region and a cell edge region defined thereon, and the cell edge region is defined in between the memory cell region and the peripheral circuit region. The semiconductor memory structure includes a plurality of active regions formed in the memory cell region, the cell edge region and the peripheral circuit region, and at least a dummy bit line formed on the active regions in the cell edge region. The dummy bit line is extended along a first direction and overlaps at least two active regions in a second direction. And the first direction and the second direction are perpendicular to each other. The dummy bit line includes a first inner line portion and an outer line portion, and the first inner line portion and the outer line portion include different widths and different spacers.

Abstract: Provided is an LED production method that can produce a great number of high-quality LEDs at low production cost. A binder-rich layer is formed on LEDs to increase the adhesiveness between the LEDs and a substrate; a phosphor layer or phosphor-rich layer is formed over the layer with a mask put on the layer; and the phosphor or a mixture of the phosphor and binder on the mask is recovered and reused.

Abstract: A light emitting device includes a package, at least one light emitting element, a light-transmissive resin, and a light reflecting resin. The package has a recess which includes a bottom surface and an inner peripheral surface. The bottom surface includes a light emitting element mounting region and a groove. The groove has an inner peripheral edge and an outer peripheral edge on the bottom surface to define the groove between the inner peripheral edge and the outer peripheral edge. The at least one light emitting element is mounted on the light emitting element mounting region. The light-transmissive resin is provided in the recess to cover the at least one light emitting element and to be in contact with the groove. The light reflecting resin is provided between the inner peripheral surface of the recess and the light-transmissive resin to reach the outer peripheral edge of the groove.