Abstract: A Semiconductor device and method for fabricating the same are provided. The method includes forming a trench in a substrate, forming a lower gate metal using a first gas, the lower gate metal burying at least a portion of the trench, forming a barrier metal on the lower gate metal, on the barrier metal, forming an upper gate metal using a second gas different from the first gas and forming a capping film on the gate metal, the capping film filling the trench.

Abstract: Provided herein a semiconductor device including a stack including conductive layers and insulating layers that are alternately stacked, and a slit insulating layer passing through the stack in a stacking direction, the slit insulating layer including a first main pattern extending in a first direction, and a first protruding pattern protruding in a second direction crossing the first direction at an end of the first main pattern.

Abstract: A semiconductor device includes: a semiconductor module and a heat dissipation sheet attached to a bottom surface of the semiconductor module, the heat dissipation sheet including: a sheet-shaped first conduction part that has a first main surface bonded to the bottom surface of the circuit substrate, a thermal conductivity of the first conduction part in directions along the first main surface being higher than a thermal conductivity of the first conduction part in a thickness direction; and a sheet-shaped second conduction part that is provided next to the first conduction part at an end of the first conduction part and that has a second main surface continuing from the first main surface, a thermal conductivity of the second conduction part in a thickness direction being higher than a thermal conductivity of the second conduction part in directions along the second main surface.

Abstract: The cap wafer for a MEMS device includes multiple electrically isolated electrodes that can be bonded and electrically connected to separate electrical contacts on a MEMS device wafer. The electrically isolated electrodes can be used for any of a variety of functions, such as for apply a force to a movable MEMS structure on the MEMS device wafer (e.g., for driving resonance of the movable MEMS structure or for adjusting a resonance or sense mode of the movable MEMS structure) or for sensing motion of a movable MEMS structure on the MEMS device wafer. Since the electrodes are electrically isolated, different electrodes may be used for different functions.

Abstract: A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (RRAM) elements. The first electrode and the two second electrodes are disposed in a horizontal plane. The first electrode is disposed between the two second electrodes. The first electrode and the two second electrodes are disposed in parallel. The first electrode is coupled to a source region of the transistor. One of the two RRAM elements is disposed between the first electrode and one of the two second electrodes. The other one of the two RRAM elements is disposed between the first electrode and the other one of the two second electrodes.

Abstract: A method of forming low-energy x-ray absorbers. Sensors may be formed on a semiconductor, e.g., silicon, wafer. A seed metal layer, e.g., gold, is deposited on the wafer and patterned into stem pads for electroplating. Stems, e.g., gold, are electroplated from the stem seed pads through a stem mask. An absorber layer, e.g., gold, is deposited on the wafer, preferably e-beam evaporated. After patterning the absorbers, absorber and stem mask material is removed, e.g., in a solvent bath and critical point drying.

Abstract: An interlayer dielectric material includes a planar surface that exhibits planarity due to raster-patterned decomposition products due to use of a confocal light beam. The planar surface encompasses a filled via that is in electrical and physical contact with a bond pad that is also on the planar surface.

Abstract: A light-emitting diode (LED) chip includes a substrate, a light-emitting component, an electrical static discharge (ESD) protection component, and a conductive layer. The light-emitting component is disposed on the substrate and includes a first semiconductor layer, a first quantum well layer, and a second semiconductor layer, in which the first quantum well layer is disposed between the first and second semiconductor layers. The ESD protection component is disposed on the substrate and includes a third semiconductor layer, a second quantum well layer, and a fourth semiconductor layer, in which the second quantum well layer is disposed between the third and the fourth semiconductor layers. The first and the fourth semiconductor layers are electrically connected with each other through the conductive layer, and the second and the third semiconductor layers are electrically isolated from each other before packaging the LED chip.

Abstract: Embodiments of the invention include a light emitting diode (UVLED), the UVLED including a semiconductor structure with an active layer disposed between an n-type region and a p-type region. The active layer emits UV radiation. The UVLED is disposed on a mount. A transparent encapsulant is disposed over the UVLED. The transparent encapsulant has an angled sidewall.

Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.

Abstract: Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer.

Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer.

Abstract: A semiconductor package includes a first package and a second package stacked on the first package. The first package includes a redistribution substrate, a first semiconductor chip on the redistribution substrate, a connection substrate provided on the redistribution substrate to surround the first semiconductor chip as viewed in plan, and an inductor structure provided within a first region of the connection substrate and electrically connected to the first semiconductor chip through the redistribution substrate. The second package includes at least one outer terminal electrically connected to the first package. The outer terminal is provided on a second region of the connection substrate, and when viewed in plan, the first region and the second region are spaced apart from each other.

Abstract: On a first epitaxial layer of a first conductivity type or a second conductivity type provided on a front surface of a silicon carbide substrate, a mark indicating a crystal axis direction of the silicon carbide substrate within a margin of error of one degree is provided. The mark is created on the silicon carbide substrate by forming the first epitaxial layer of the first conductivity type or the second conductivity type on the front surface of the silicon carbide substrate, detecting a stacking fault from the first epitaxial layer, and confirming the crystal axis direction of the silicon carbide substrate from the detected stacking fault.

Abstract: A side surface type optical semiconductor device includes a substrate made of an insulating material and having a main surface and a back surface, which face opposite sides to each other in a thickness direction. The substrate includes a first concave portion recessed in the thickness direction and a second concave portion recessed further toward the back surface than the first concave portion, a semiconductor optical element is disposed across the first concave portion and the second concave portion, a hollow portion is formed between the semiconductor optical element and the second concave portion, and the hollow portion is used as a light guide path of the semiconductor optical element.

Abstract: Provided is a method for testing a plurality of transistors of a semiconductor device. The method includes forming a plurality of elements or a plurality of logic using a Front End Of Line (FEOL) process, forming a selection logic using at least one of the plurality of elements or the plurality of logic cells, connecting the selection logic and the plurality of transistors, forming a pad for connecting an input terminal of the selection logic and drain or source terminals of the plurality of transistors, and sequentially selecting the plurality of transistors using the selection logic and measuring an electrical characteristic of selected transistors among the plurality of transistors.

Abstract: A display device includes a substrate, one line on the substrate, the one line extending from a peripheral region through a display region, pixels on the display region, the pixels being connected to the one line, an outer line on the peripheral region, the outer line being connected to the one line during a short circuit test process that detects a position of a short circuit defect, an electrostatic protection resistor on the peripheral region, the electrostatic protection resistor being connected to the outer line, a pad on the peripheral region, the pad being connected to the outer line through the electrostatic protection resistor, a short circuit test signal being applied to the pad during the short circuit test process, and a bypass line connecting a node between the pad and the electrostatic protection resistor to the outer line.

Abstract: A vertical flash memory includes a plurality of vertical memory cells, wherein each of the vertical memory cells includes a selective gate, a main gate, a dielectric interlayer and a vertical channel layer. The selective gate is disposed on a substrate. The main gate is stacked on the selective gate. The dielectric interlayer isolates the main gate from the selective gate. The vertical channel layer is disposed on sidewalls of the selective gate and the main gate. The present invention also provides a method of forming said vertical flash memory.

Abstract: A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY.

Abstract: Disclosed is a method. The method includes forming a metal layer on a first surface of a semiconductor body; irradiating the metal layer with particles to move metal atoms from the metal layer into the semiconductor body and form a metal atom containing region in the semiconductor body; and annealing the semiconductor body. The annealing includes heating at least the metal atom containing region to a temperature of less than 500° C.