Patents Examined by Mounir S Amer
  • Patent number: 11984388
    Abstract: Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: May 14, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Stephen St. Germain, Jay A. Yoder, Dennis Lee Conner, Frank Robert Cervantes, Andrew Celaya
  • Patent number: 11978750
    Abstract: A photoelectric conversion device having a light-receiving pixel region and a light-shielded pixel region, the photoelectric conversion device comprising: a semiconductor layer; a first layered structure which is arranged on a first surface of the semiconductor layer in the light-receiving pixel region and in which at least an insulating layer and a metal oxide layer arranged between the semiconductor layer and the insulating layer are stacked; and a second layered structure which is arranged on the first surface of the semiconductor layer in the light-shielded pixel region and in which at least a light-shielding layer, a metal oxide layer arranged between the semiconductor layer and the light-shielding layer, a first insulating layer arranged between the metal oxide layer and the light-shielding layer, and a second insulating layer arranged between the first insulating layer and the light-shielding layer and including hydrogen are stacked.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: May 7, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideaki Ishino
  • Patent number: 11978679
    Abstract: A device used for semiconductor metrology includes a substrate and a plurality of pieces from one or more semiconductor wafers. Each piece of the plurality of pieces is bonded to the substrate at a respective position on the substrate. Each piece of the plurality of pieces includes a respective instance of a measurement test structure and an alignment mark. Each piece of the plurality of pieces has a known location from the one or more semiconductor wafers.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: May 7, 2024
    Assignee: KLA Corporation
    Inventor: Chen Dror
  • Patent number: 11978836
    Abstract: A display module is provided that includes a substrate and a molding part. The substrate includes a first surface disposed with a plurality of LEDs, and a second surface, opposite of the first surface, that is disposed with a plurality of chips connected to the plurality of LEDs and further disposed with a coupling body. The molding part covers the first surface and the plurality of LEDs, and has a shape corresponding to a shape of the plurality of LEDs.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: May 7, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taehyeun Ha, Jaehoo Park
  • Patent number: 11980111
    Abstract: A phase change memory bridge cell comprising a dielectric layer located on top of a at least one electrode, wherein a trench is located in the dielectric layer. A first liner located at the bottom of the trench in the dielectric layer and the first liner is located on the sidewalls of the dielectric layer that forms the sidewalls of the trench. A phase change memory material located on top of the first liner, wherein a top surface of the phase change memory material is aligned with a top surface of the dielectric layer, wherein the dielectric layer is located adjacent to and surrounding the vertical sidewalls of the phase change memory material, wherein a top surface of the phase change memory material is flush with a top surface of the dielectric layer.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: May 7, 2024
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Andrew Herbert Simon, Kevin W. Brew, Muthumanickam Sankarapandian, Steven Michael McDermott, Nicole Saulnier
  • Patent number: 11980109
    Abstract: Provided are a selection element which does not need an intermediate electrode and thus has improved integration, a phase-change memory device having the selection element, and a phase-change memory implemented so that the phase-change memory device has a highly integrated three-dimensional architecture.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: May 7, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun Heub Song, Jae Kyeong Jeong
  • Patent number: 11980108
    Abstract: Techniques are described to form a liner to protect a material, such as a storage element material, from damage during subsequent operations or phases of a manufacturing process. The liner may be bonded to the material (e.g., a chalcogenide material) using a strong bond or a weak bond. In some cases, a sealant material may be deposited during an etching phase of the manufacturing process to prevent subsequent etching operations from damaging a material that has just been etched.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: May 7, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Farrell M. Good, Robert K. Grubbs, Gurpreet S. Lugani
  • Patent number: 11973129
    Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device includes forming nanowire structures stacked over a substrate and spaced apart from one another, and forming a dielectric material surrounding the nanowire structures. The dielectric material has a first nitrogen concentration. The method also includes treating the dielectric material to form a treated portion. The treated portion of the dielectric material has a second nitrogen concentration that is greater than the first nitrogen concentration. The method also includes removing the treating portion of the dielectric material, thereby remaining an untreated portion of the dielectric material as inner spacer layers; and forming the gate stack surrounding nanowire structures and between the inner spacer layers.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Yu Lin, Chansyun David Yang, Fang-Wei Lee, Tze-Chung Lin, Li-Te Lin, Pinyen Lin
  • Patent number: 11967539
    Abstract: A heat dissipation sheet includes a first sheet composed of a plurality of first carbon nanotubes, and a second sheet composed of a plurality of second carbon nanotubes, wherein the first sheet and the second sheet are coupled in a stacked state, and the first carbon nanotubes and the second carbon nanotubes are different in an amount of deformation when pressure is applied.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: April 23, 2024
    Assignee: FUJITSU LIMITED
    Inventors: Shinichi Hirose, Daiyu Kondo
  • Patent number: 11961838
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: April 16, 2024
    Assignee: Intel Corporation
    Inventors: Byron Ho, Chun-Kuo Huang, Erica Thompson, Jeanne Luce, Michael L. Hattendorf, Christopher P. Auth, Ebony L. Mays
  • Patent number: 11957068
    Abstract: Methods, systems, and devices for techniques for memory cells with sidewall and bulk regions in vertical structures are described. A memory cell may include a first electrode, a second electrode, and a self-selecting storage element between the first electrode and the second electrode. The bulk region may extend between the first electrode and the sidewall region. The bulk region may include a chalcogenide material having a first composition, and the sidewall region may include the chalcogenide material having a second composition that is different than the first composition. Also, the sidewall region may separate the bulk region from the second electrode.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: April 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Lorenzo Fratin, Enrico Varesi, Paolo Fantini
  • Patent number: 11950522
    Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: April 2, 2024
    Assignee: SK hynix Inc.
    Inventors: Myoung Sub Kim, Tae Hoon Kim, Beom Seok Lee, Seung Yun Lee, Hwan Jun Zang, Byung Jick Cho, Ji Sun Han
  • Patent number: 11950434
    Abstract: The present disclosure relates to an integrated chip including a first word line and a second word line adjacent to the first word line. The first word line and the second word line both extend along a first direction. A first memory cell is over the first word line and a second memory cell is over the second word line. A first bit line extends over the first memory cell, over the second memory cell, and along a second direction transverse to the first direction. A first dielectric layer is arranged between the first memory cell and the second memory cell. The first dielectric layer extends in a first closed loop to form and enclose a first void within the first dielectric layer. The first void laterally separates the first memory cell from the second memory cell.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yuan-Tai Tseng
  • Patent number: 11950517
    Abstract: A three-dimensional semiconductor memory device may include a first conductive line extending in a first direction, a second conductive line extending in a second direction crossing the first direction, a cell stack at an intersection of the first and second conductive lines, and a gapfill insulating pattern covering a side surface of the cell stack. The cell stack may include first, second, and third electrodes sequentially stacked, a switching pattern between the first and second electrodes, and a variable resistance pattern between the second and third electrodes. A top surface of the gapfill insulating pattern may be located between top and bottom surfaces of the third electrode.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: April 2, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ilmok Park, Kyusul Park, Daehwan Kang
  • Patent number: 11942469
    Abstract: An integrated circuit includes a first-type active-region structure, a second-type active-region structure on a substrate, and a plurality of gate-conductors. The integrated circuit also includes a backside horizontal conducting line in a backside first conducting layer below the substrate, a backside vertical conducting line in a backside second conducting layer below the backside first conducting layer, and a pin-connector for a circuit cell. The pin-connector is directly connected between the backside horizontal conducting line and the backside vertical conducting line. The backside horizontal conducting line extends across a vertical boundary of the circuit cell.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-An Lai, Shih-Wei Peng, Te-Hsin Chiu, Jiann-Tyng Tzeng, Chung-Hsing Wang
  • Patent number: 11944019
    Abstract: A memory device includes a substrate, a transistor disposed over the substrate, an interconnect structure disposed over and electrically connected to the transistor, and a memory stack disposed between two adjacent metallization layers of the interconnect structure. The memory stack includes a bottom electrode disposed over the substrate and electrically connected to a bit line, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer and electrically connected to a word line. Besides, at least one moisture-resistant layer is provided adjacent to and in physical contact with the selector layer, and the at least one moisture-resistant layer includes an amorphous material.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Feng Hsu, Chien-Min Lee, Tung-Ying Lee, Cheng-Hsien Wu, Hengyuan Lee, Xinyu Bao
  • Patent number: 11935750
    Abstract: A method for producing a semiconductor device includes forming, on a substrate, a film to be processed. The method further includes forming, on the film to be processed, a first film containing a metallic element and a second film containing at least one of carbon or boron. The method further includes forming an insulating film on the first and second films. The method further includes processing the film to be processed using the first film, the second film, and the insulating film, as a mask.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: March 19, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Kei Watanabe, Toshiyuki Sasaki, Soichi Yamazaki, Shunsuke Ochiai, Yuya Matsubara
  • Patent number: 11930646
    Abstract: A resistive memory device includes a plurality of first conductive lines in a first area and a second area on a substrate, a plurality of second conductive lines in the first area and the second area, the plurality of second conductive lines being apart from the plurality of first conductive lines in a vertical direction, and a plurality of memory cells connected to the first and second conductive lines at a plurality of intersections between the plurality of first and second conductive lines in the first area and the second area. The plurality of memory cells include an active memory cell in the first area and a dummy memory cell in the second area. The active memory cell including a first resistive memory pattern having a first width and the dummy memory cell including a second resistive memory pattern having a second width greater than the first width.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: March 12, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeonghee Park, Jonguk Kim, Byeongju Bae
  • Patent number: 11930724
    Abstract: A phase change memory (PCM) cell includes an electrode, a heater electrically connected to the electrode, a PCM material electrically connected to the heater, a second electrode electrically connected to the PCM material, an electrical insulator surrounding the PCM material, and a shield positioned between the PCM material and the electrical insulator, the shield comprising a reactive-ion-etching-resistant material.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: March 12, 2024
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Nicole Saulnier, Muthumanickam Sankarapandian, Andrew Herbert Simon, Steven Michael McDermott, Iqbal Rashid Saraf
  • Patent number: 11923369
    Abstract: An integrated circuit includes a set of power rails on a back-side of a substrate, a first flip-flop, a second flip-flop and a third flip-flop. The set of power rails extend in a first direction. The first flip-flop includes a first set of conductive structures extending in the first direction. The second flip-flop abuts the first flip-flop at a first boundary, and includes a second set of conductive structures extending in the first direction. The third flip-flop abuts the second flip-flop at a second boundary, and includes a third set of conductive structures extending in the first direction. The first, second and third flip-flop are on a first metal layer and are on a front-side of the substrate opposite from the back-side. The second set of conductive structures are offset from the first boundary and the second boundary in a second direction.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Hsin Chiu, Wei-Cheng Lin, Wei-An Lai, Jiann-Tyng Tzeng