Patents Examined by Mounir S Amer
  • Patent number: 10811252
    Abstract: A pattern-forming method includes forming a first film above a material to be processed, processing the first film into a pattern to be formed in the material to be processed, providing a second film on the first film and the material to be processed, supplying a precursor containing at least one of a metal material or a semiconductor material to the second film, removing the first film, and processing the material to be processed using the second film impregnated with at least one of the metal material and the semiconductor material, as a mask.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: October 20, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ryosuke Yamamoto, Ryuichi Saito, Seiji Morita, Ryoichi Suzuki, Takeharu Motokawa, Shinichi Ito, Soichi Inoue
  • Patent number: 10804077
    Abstract: A microwave plasma source for generating a microwave plasma inside a chamber by radiating a microwave into the chamber, includes: a microwave oscillator for oscillating the microwave and vary an oscillation frequency thereof; a waveguide through which the microwave propagates; an antenna part including a slot antenna for radiating the microwave into the chamber and having a predetermined pattern of slots, and a microwave-transmitting plate constituting a ceiling plate of the chamber and made of a dielectric material through which the microwave radiated from the slots transmits; temperature detectors for detecting temperatures at plural positions of the antenna part outside the chamber when the microwave plasma is generated; and a frequency controller for receiving detection signals obtained by the temperature detectors and controlling the oscillation frequency of the microwave oscillator so that a plasma density distribution inside the chamber becomes a desired distribution based on the detection signals.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: October 13, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Toshihiko Iwao
  • Patent number: 10804444
    Abstract: A light-emitting device including at least one light-emitting unit, a wavelength conversion adhesive layer, and a reflective protecting element is provided. The light-emitting unit has an upper surface and a lower surface opposite to each other. The light-emitting unit includes two electrode pads, and the two electrode pads are located on the lower surface. The wavelength conversion adhesive layer is disposed on the upper surface. The wavelength conversion adhesive layer includes a low-concentration fluorescent layer and a high-concentration fluorescent layer. The high-concentration fluorescent layer is located between the low-concentration fluorescent layer and the light-emitting unit. The width of the high-concentration fluorescent layer is WH. The width of the low-concentration fluorescent layer is WL. The width of the light-emitting unit is WE. The light-emitting device further satisfies the following inequalities: WE<WL, WH<WL and 0.8<WH/WE?1.2.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: October 13, 2020
    Assignee: Genesis Photonics Inc.
    Inventors: Cheng-Wei Hung, Long-Chi Tu, Jui-Fu Chang, Chun-Ming Tseng, Yun-Chu Chen
  • Patent number: 10804357
    Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: October 13, 2020
    Assignee: Sony Corporation
    Inventors: Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong, Rafael Rios, Abhijit Jayant Pethe, Willy Rachmady
  • Patent number: 10797138
    Abstract: Methods of forming contacts for vertical-transport field-effect transistors and structures for a vertical-transport field-effect transistor and contact. An interlayer dielectric layer is deposited over a gate stack, and a first opening is formed in the interlayer dielectric layer and penetrates through the gate stack to cut the gate stack into a first section and a second section. A dielectric pillar is formed in the first opening and is arranged between the first section of the gate stack and the second section of the gate stack. Second and third openings are formed in the interlayer dielectric layer that penetrate to the gate stack and that are divided by the dielectric pillar. A first contact in the second opening is coupled with the first section of the gate stack, and a second contact in the third opening is coupled with the second section of the gate stack.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Emilie Bourjot, Daniel Chanemougame, Steven Bentley
  • Patent number: 10797150
    Abstract: An apparatus including a non-planar body on a substrate, the body including a channel on a blocking material, and a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel material and a second gate electrode material including a second work function different from the first work function disposed on the channel material and on the blocking material. A method including forming a non-planar body on a substrate, the non-planar body including a channel on a blocking material, and forming a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel and a second gate electrode material including a second work function different from the first work function disposed on the channel and on the blocking material.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Sean T. Ma, Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Gilbert Dewey, Nadia M. Rahhal-Orabi, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Patent number: 10796936
    Abstract: Representative implementations of devices and techniques provide a device and a technique for processing integrated circuit (IC) dies. The device comprises a die tray (such as a pick and place tray, for example) for holding the dies during processing. The die tray may include an array of pockets sized to hold individual dies. The technique can include loading dies on the die tray, cleaning the top and bottom surfaces of the dies, and ashing and activating both surfaces of the dies while on the die tray, eliminating the need to turn the dies over during processing.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: October 6, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 10790376
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers; contacts connecting to at least one gate structure of the plurality of gate structures; and at least one metallization feature connecting to the source and drain regions and extending over the sidewall spacers.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: September 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Chanro Park, Julien Frougier, Kangguo Cheng, Andre P. Labonte
  • Patent number: 10777587
    Abstract: Provided is an active matrix substrate (1001) that includes multiple inspection TFTs (10Q) that are arranged in a non-display area (900), and an inspection circuit (200) that includes multiple inspection TFTs (10Q). At least one or more of the multiple inspection TFTs (10Q) are arranged within a semiconductor chip mounting area (R) in which a semiconductor chip is mounted. Each of the multiple inspection TFTs (10Q) includes a semiconductor layer, a lower gate electrode (FG) that is positioned on a side of the substrate of the semiconductor layer with a gate insulation layer in between, an upper gate electrode (BG) that is positioned on a side opposite to the side of the substrate of the semiconductor layer with an insulation layer including a first insulation layer in between, and a source electrode and a drain electrode that are connected to the semiconductor layer.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: September 15, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Jun Nishimura, Yoshihito Hara, Yoshimasa Chikama, Yukinobu Nakata
  • Patent number: 10777705
    Abstract: The structural characteristics of the light-exiting surface of a light emitting device are controlled so as to increase the light extraction efficiency of that surface when the surface is roughened. A light emitting surface comprising layers of materials with different durability to the roughening process exhibits a higher light extraction efficiency than a substantially uniform light emitting surface exposed to the same roughening process. In a GaN-type light emitting device, a thin layer of AlGaN material on or near the light-exiting surface creates sharper features after etching compared to the features created by conventional etching of a surface comprising only GaN material.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: September 15, 2020
    Assignee: Lumileds LLC
    Inventors: Rajwinder Singh, John Edward Epler
  • Patent number: 10777728
    Abstract: In a masking phase, a first segment of an amorphous mask is formed on an underlying layer of a substrate. The first segment comprises a first set of trenches exposing the underlying layer. In the masking phase, a second segment of the amorphous mask is formed on the underlying layer. The second segment comprises a second set of trenches exposing the underlying layer. The segments are non-overlapping. An open end of one of the first set of trenches faces an open end of one of the second set of trenches, but the ends are separated by a portion of the amorphous mask. In a semiconductor growth phase, semiconductor material is grown, by selective area growth, in the first and second sets of trenches to form first and second sub-networks of nanowires on the underlying layer. The first and second sub-networks of nanowires are joined to form a single nanowire network.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: September 15, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pavel Aseev, Philippe Caroff-Gaonac'h
  • Patent number: 10777773
    Abstract: A display device includes a display region arranged above a substrate, a first light emitting element emitting light of a first color, a second light emitting element emitting light of a second color, and a third light emitting element emitting light of a third color arranged in the display region, and a first optical path length adjustment film, a second optical path length adjustment film, and a third optical path length adjustment film in the display region.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: September 15, 2020
    Assignee: Japan Display Inc.
    Inventor: Takahiro Ushikubo
  • Patent number: 10777656
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Tahir Ghani, Byron Ho, Curtis W. Ward, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 10770366
    Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Tu, Hsien-Wei Chen, Tsung-Fu Tsai, Wen-Hsiung Lu, Yian-Liang Kuo
  • Patent number: 10770471
    Abstract: A semiconductor device according to an embodiment includes a first contact electrically connected to a first conductive layer with a diameter size smaller than a diameter size of a first support pillar at a region position on an inner side in a radial direction of the first support pillar in a first region and extending to the opposite side of the substrate with respect to the first conductive layer; and a second contact electrically connected to a second conductive layer with a diameter size smaller than a diameter size of a second support pillar at a position of penetrating through the first conductive layer at a region position on an inner side in a radial direction of the second support pillar in the first region and extending to the opposite side of the substrate with respect to the second conductive layer.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: September 8, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kojiro Shimizu, Hanae Ishihara, Yumiko Miyano
  • Patent number: 10770417
    Abstract: A chip package for optical sensing includes a substrate, and a semiconductor device positioned on the substrate and coupled to the substrate through a first conducting element. Two molding processes are applied, to form a first colloid body on the substrate so as to cover the semiconductor device and, on the first colloid body, to form a second colloid body which covers an optical device. The optical device is electrically connected to the substrate through a second conducting element. The light transmittance of the second colloid body exceeds that of the first colloid body.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: September 8, 2020
    Assignee: SHUNSIN TECHNOLOGY (ZHONG SHAN) LIMITED
    Inventor: Wang-Lai Yang
  • Patent number: 10763304
    Abstract: The present disclosure provides a semiconductor structure, including a memory region and a logic region adjacent to the memory region. The memory region includes a first Nth metal line, a first stop layer being disposed over a magnetic tunneling junction (MTJ) over the first Nth metal line, and a first (N+1)th metal via being disposed over the MTJ and surrounded by the first stop layer, the first (N+1)th metal via having a first height. The logic region includes a second Nth metal line, a second stop layer being disposed over an (N+1)th metal line, and a second (N+1)th metal via over the (N+1)th metal line and having a second height. N is an integer greater than or equal to 1 and the first height is greater than the second height. A method of manufacturing the semiconductor structure is also disclosed.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chern-Yow Hsu, Yuan-Tai Tseng, Shih-Chang Liu
  • Patent number: 10763225
    Abstract: An antenna module includes a fan-out semiconductor package including an IC, an encapsulant encapsulating at least a portion of the IC, a core member having a first side surface facing the IC or the encapsulant, and a connection member including at least one wiring layer electrically connected to the IC and the core member and at least one insulating layer; and an antenna package including a plurality of first directional antenna members configured to transmit or receive a first RF signal. The fan-out semiconductor package further includes at least one second directional antenna member disposed on a second side surface of the core member opposing the first side surface of the core member, stood up from a position electrically connected to at least one wiring layer, and configured to transmit or receive a second RF signal.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: September 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Il Kim, Yong Ho Baek, Jin Seon Park, Young Sik Hur
  • Patent number: 10756265
    Abstract: In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Kunal Parekh
  • Patent number: 10756204
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins, individual ones of the plurality of fins along a first direction. A plurality of gate structures is formed over the plurality of fins, individual ones of the gate structures along a second direction orthogonal to the first direction. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of one of the plurality of gate structures is removed to expose a portion of each of the plurality of fins. The exposed portion of each of the plurality of fins is removed. An insulating layer is formed in locations of the removed portion of each of the plurality of fins.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Tahir Ghani, Byron Ho, Michael L. Hattendorf, Christopher P. Auth