Patents Examined by Mounir S Amer
  • Patent number: 11158489
    Abstract: Apparatus and methods to control the phase of power sources for plasma process regions in a batch process chamber. A master exciter controls the phase of the power sources during the process sequence based on feedback from the match circuits of the respective plasma sources.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: October 26, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Tsutomu Tanaka, John C. Forster, Ran Liu, Kenichi Ohno, Ning Li, Mihaela Balseanu, Keiichi Tanaka, Li-Qun Xia
  • Patent number: 11152564
    Abstract: The first film forming device is configured to form a film using plasma in a consistent vacuum state. In the forming of the first substrate product, the first substrate product is formed in a consistent vacuum state. The first substrate product has the support base, a first lamination region, and a metal region. The first lamination region is provided on the support base. The metal region is provided on the first lamination region, and has a first metal layer and a second metal layer. The first metal layer is provided on the first lamination region, and the second metal layer is provided on the first metal layer. A material of the first metal layer has TiN or Ta, and a material of the second metal layer has TaN or Ru.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: October 19, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Takuya Kubo, Song yun Kang
  • Patent number: 11152491
    Abstract: A method for forming a semiconductor device structure is provided. The method for forming a semiconductor device structure includes forming a fin structure over a substrate. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method for forming the semiconductor device structure also includes removing the first semiconductor layers of the fin structure in a channel region thereby exposing the second semiconductor layers of the fin structure. The method for forming the semiconductor device structure also includes forming a dielectric material surrounding the second semiconductor layers, and treating a first portion of the dielectric material. The method for forming the semiconductor device structure also includes etching the first portion of the dielectric material to form gaps, and filling the gaps with a gate stack.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Yu Lin, Chansyun David Yang, Fang-Wei Lee, Tze-Chung Lin, Li-Te Lin, Pinyen Lin
  • Patent number: 11152248
    Abstract: Embodiments disclosed herein relate to cluster tools for forming and filling trenches in a substrate with a flowable dielectric material. In one or more embodiments, a cluster tool for processing a substrate contains a load lock chamber, a first vacuum transfer chamber coupled to the load lock chamber, a second vacuum transfer chamber, a cooling station disposed between the first vacuum transfer chamber and the second vacuum transfer chamber, a factory interface coupled to the load lock chamber, a plurality of first processing chambers coupled to the first vacuum transfer chamber, wherein each of the first processing chambers is a deposition chamber capable of performing a flowable layer deposition, and a plurality of second processing chambers coupled to the second vacuum transfer chamber, wherein each of the second processing chambers is a plasma chamber capable of performing a plasma curing process.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: October 19, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Jingmei Liang, Yong Sun, Jinrui Guo, Praket P. Jha, Jung Chan Lee, Tza-Jing Gung, Mukund Srinivasan
  • Patent number: 11152546
    Abstract: A light-emitting device includes a plurality of light-emitting elements, a plurality of light-transmissive members, and a covering member. The light-emitting elements each has a light-extracting surface. The light-emitting elements each includes a layered structure including a semiconductor layer, and a plurality of electrodes connected to the layered structure. The light-transmissive members each has a lower surface facing the light-extracting surface of at least one of the light-emitting elements, and an upper surface opposite to the lower surface and having an area smaller than an area of the lower surface. The upper surface of each of the light transmissive members collectively constitutes a light-emitting part having an outermost periphery with a square shape or a circular shape. The covering member integrally covers lateral surfaces of the light-emitting elements and lateral surfaces of the light-transmissive members.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: October 19, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Yuta Oka, Nami Abe
  • Patent number: 11145538
    Abstract: A multilayer structure is provided, the multilayer structure comprising a semiconductor on insulator structure comprises an insulating layer that enhances the stability of the underlying charge trapping layer.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: October 12, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Jeffery L. Libbert, Qingmin Liu, Gang Wang, Andrew M. Jones
  • Patent number: 11145815
    Abstract: A non-volatile memory circuit in embodiments of the present invention may have one or more of the following features: (a) a logic source, and (b) a semi-conductive device being electrically coupled to the logic source, having a first terminal, a second terminal and a nano-grease with significantly reduced amount of carbon nanotube loading located between the first and second terminal, wherein the nano-grease exhibits non-volatile memory characteristics.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: October 12, 2021
    Assignee: South Dakota Board of Regents
    Inventors: Charles Tolle, Haiping Hong, Christian Widener, Greg Christensen, Jack Yang
  • Patent number: 11139167
    Abstract: A method making it possible to obtain, on an upper surface of a crystalline substrate, a semipolar layer of nitride material comprising any one from among gallium, aluminium or indium, the method comprises the following steps: obtaining, on the upper surface of the crystalline substrate, a plurality of parallel grooves which extend in a first direction, one of the two opposite facets exhibiting a crystal orientation; etching a plurality of parallel slices which extend in a second direction that has undergone a rotation with respect to the first direction of the grooves in such a way as to obtain individual facets exhibiting a crystal orientation; epitaxial growth of the material from the individual facets.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: October 5, 2021
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Michel El Khoury Maroun, Guy Feuillet, Philippe Vennegues, Jesus Zuniga Perez
  • Patent number: 11139336
    Abstract: A method for fabricating a throughput-scalable sensing system is disclosed. The method includes receiving a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer includes a semiconductor substrate and a plurality of sensors disposed in the semiconductor substrate. Each sensor of the plurality of sensors is disposed in a separate semiconductor die of the first semiconductor wafer. The method further includes bonding the first semiconductor wafer to the second semiconductor wafer and preparing the bonded first semiconductor wafer and the second semiconductor wafer for conductive path redistribution. The method further includes forming one or more redistribution paths and dicing an array of semiconductor dies as a group from the plurality of semiconductor dies. The array of semiconductor dies includes a group of sensors associated with the throughput-scalable sensing system.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: October 5, 2021
    Assignee: GeneSense Technology Inc.
    Inventor: Mei Yan
  • Patent number: 11140723
    Abstract: A patch on interposer (PoINT) package is described with a wireless communications interface. Some examples include an interposer, a main patch attached to the interposer, a main integrated circuit die attached to the patch, a second patch attached to the interposer, and a millimeter wave radio die attached to the second patch and coupled to the main integrated circuit die through the interposer to communicate data between the main die and an external component.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventor: Telesphor Kamgaing
  • Patent number: 11139432
    Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Miao Liu, Bwo-Ning Chen, Kei-Wei Chen
  • Patent number: 11133463
    Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Pirovano, Kolya Yastrebenetsky, Anna Maria Conti, Fabio Pellizzer
  • Patent number: 11133435
    Abstract: Provided is a technique for manufacturing a nitride semiconductor substrate with which it is possible to manufacture a nitride semiconductor substrate having sufficiently reduced dislocation density with a large area even if manufactured on an inexpensive substrate made of sapphire, etc. A nitride semiconductor substrate in which a nitride semiconductor layer formed on a substrate is formed by laminating an undoped nitride layer and a rare earth element-added nitride layer to which a rare earth element is added as a doping material, and the dislocation density is of the order of 106 cm?2 or less.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: September 28, 2021
    Assignee: OSAKA UNIVERSITY
    Inventors: Yasufumi Fujiwara, Wanxin Zhu, Atsushi Koizumi, Brandon Mitchell, Tom Gregorkiewicz
  • Patent number: 11131023
    Abstract: A film deposition apparatus includes a process chamber and a turntable provided in the process chamber. The turntable includes a substrate receiving region to receive a substrate thereon and provided along a circumferential direction of the turntable. A source gas supply unit extending along a radial direction of the turntable is provided above the turntable with a first distance from the turntable such that the source gas supply unit covers an entire length of the substrate receiving region in the radial direction. An axial-side supplementary gas supply unit is provided in the vicinity of the source gas supply unit and above the turntable with a second distance from the turntable. The second distance is longer than the first distance. The axial-side supplementary gas supply unit covers a predetermined region of the substrate receiving region on the axial side in the radial direction of the turntable.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: September 28, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Shigehiro Miura, Jun Sato
  • Patent number: 11133320
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, in which a width of the second trench is greater than a width of the first trench; forming a first liner in the first trench and the second trench; forming a second liner on the first liner as the second liner completely fills the first trench and partly fills the second trench; and planarizing the second liner and the first liner to form a first isolation structure and a second isolation structure.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: September 28, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Kun-Hsin Chen, Hsuan-Tung Chu, Tsuo-Wen Lu, Po-Chun Chen
  • Patent number: 11127901
    Abstract: A three-dimensional stacked phase change memory and a preparation method thereof are provided. The method comprises: preparing first horizontal electrodes spaced apart from each other on a substrate; preparing first strip-shaped phase change layers, each having a central gap, between the first horizontal electrodes; preparing first selectors in the central gaps of the first strip-shaped phase change layers; preparing a first insulating layer; preparing second strip-shaped phase change layers at same vertical positions on the first insulating layer; preparing second selectors; then preparing horizontally-oriented insulating holes between the horizontal electrodes; and preparing vertical electrodes between the adjacent insulating holes, thereby forming a multilayer stacked phase change memory with a vertical structure.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 21, 2021
    Assignee: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Xiangshui Miao, Hao Tong, Yushan Shen, Wang Cai
  • Patent number: 11127923
    Abstract: The present disclosure provides a display device, the display device including a first functional member; a second functional member, including a support portion disposed on a surface oriented to the first functional member. Because of the structure, when the display device is deformed, such as the optical adhesive layer deformed to a certain degree, the support portion which disposed on the first functional member will in contact with the second functional member functions to support, at this point, the adhesive layer will not continue to squeeze the adhesive out, so collapse will not occur.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: September 21, 2021
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Jifeng Chen, Bao Chen
  • Patent number: 11121313
    Abstract: A semiconductor structure and a formation method thereof are disclosed. The formation method includes: providing a base; forming a dielectric layer on the base; forming a conductive via running through the dielectric layer; forming a conductive plug in the conductive via; forming a protective layer on the dielectric layer, wherein the protective layer covers the conductive plug; forming an aligner trench in the protective layer and the dielectric layer, wherein the aligner trench is isolated from the conductive plug; after forming the aligner trench, removing the protective layer to expose a top portion of the conductive plug; and after removing the protective layer, forming a magnetic tunnel junction (MTJ) laminated structure on the conductive plug.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: September 14, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventor: Huan Liu
  • Patent number: 11121315
    Abstract: The problem of forming top electrode vias that provide consistent results in devices that include resistance switching RAM cells of varying heights is solved using a dielectric composite that fills areas between resistance switching RAM cells and varies in height to align with the tops of both the taller and the shorter resistance switching RAM cells. An etch stop layer may be formed over the dielectric composite providing an equal thickness of etch-resistant dielectric over both taller and shorter resistance switching RAM cells. The dielectric composite causes the etch stop layer to extend laterally away from the resistance switching RAM cells to maintain separation between the via openings and the resistance switching RAM cell sides even when the openings are misaligned.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Tai Hsiao, Sheng-Chau Chen, Hsun-Chung Kuang
  • Patent number: 11120998
    Abstract: An etching method includes providing a plasma of a first treatment gas to an etching-object to form a deposition layer on the etching-object, the first treatment gas including a fluorocarbon gas and an inert gas, and the etching-object including a first region including silicon oxide and a second region including silicon nitride, providing a plasma of an inert gas to the etching-object having the deposition layer thereon to activate an etching reaction of the silicon oxide, wherein a negative direct current voltage is applied to an opposing part that is spaced apart from the etching-object so as to face an etching surface of the etching-object, the opposing part including silicon, and subsequently, providing a plasma of a second treatment gas to remove an etching reaction product, the second treatment gas including an inert gas and an oxygen-containing gas.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: September 14, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Hyun Lee, Jeon-Il Lee, Sung-Woo Kang, Hong-Sik Shin, Young-Mook Oh, Seung-Min Lee