Abstract: A method for manufacturing an interconnection structure for an integrated circuit is provided. The integrated circuit includes a first insulating layer, a second insulating layer, and a third insulating layer. Electrical contacts pass through the first insulating layer, and a component having an electrical contact region is located in the second insulating layer. The method includes etching a first opening in the third layer, vertically aligned with the contact region. A fourth insulating layer is deposited to fill in the opening, and a second opening is etched to the contact region by passing through the opening in the third insulating layer. A metal level is formed by filling in the second opening with a metal.

Abstract: The present disclosure provides a CMOS image sensor and a pixel structure thereof, and a method for manufacturing a deep trench isolation grid structure in the pixel structure. The method for manufacturing the deep trench isolation grid structure comprises: depositing a first isolation layer and a second isolation layer sequentially on the side walls and bottom surface of each deep trench; and depositing a third isolation layer that fills each deep trench on the upper surface of the second isolation layer, so that the first isolation layer, the second isolation layer and the third isolation layer in the plurality of deep trenches constitute the grid. The deep trench isolation grid structure formed by the method can effectively reduce electrical crosstalk between adjacent grid lines, thereby improving the device performance of the CMOS image sensor which is built upon the deep trench isolation grid structure and the pixel structure thereof.

Abstract: A backside illuminated image sensor and a method of manufacturing the same are disclosed. The backside illuminated image sensor includes a substrate having a frontside surface and a backside surface, pixel regions disposed in the substrate, an insulating layer disposed on the frontside surface of the substrate, a bonding pad disposed on a frontside surface of the insulating layer, a second bonding pad connected to a backside surface of the bonding pad through the substrate and the insulating layer and exposed through the backside surface of the substrate, and a test pad connected to the backside surface of the bonding pad through the substrate and the insulating layer, exposed through the backside surface of the substrate, and for testing whether the second bonding pad is normally connected to the backside surface of the bonding pad.

Abstract: A method for forming a contact pad of a semiconductor device is disclosed. The method includes providing a semiconductor substrate including a first side and a second side. The semiconductor device includes a shallow trench isolation structure, disposed between the first side and the second side, and an intermetal dielectric stack coupled to the second side. The intermetal dielectric stack includes a first metal interconnect. The method further includes etching a first trench into the semiconductor substrate, depositing a dielectric material into the first trench to form a dielectric spacer extending along side walls of the first trench, etching a second trench aligned with the first trench, and depositing a metal material into the second trench to form the contact pad that contacts the first metal interconnect.

Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.

Abstract: A solid state image sensor includes a semiconductor substrate where photoelectric conversion regions for converting light into charges are arranged per pixel planarly arranged; an organic photoelectric conversion film laminated at a light irradiated side of the semiconductor substrate via an insulation film and formed at the regions where the pixels are formed; a lower electrode formed at and in contact with the organic photoelectric conversion film at a semiconductor substrate side; a first upper electrode laminated at a light irradiated side of the organic photoelectric conversion film and formed such that ends of the first upper electrode are substantially conform with ends of the organic photoelectric conversion film when the solid state image sensor is planarly viewed; and a film stress suppressor for suppressing an effect of a film stress on the organic photoelectric conversion film, the film stress being generated on the first upper electrode.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to an encapsulation layer for a semiconductor device having a chalcogenide material, and methods of forming the same. In one aspect, a method of fabricating a semiconductor device comprises providing a substrate having an exposed surface comprising a chalcogenide material. The method additionally comprises forming a low-electronegativity (low-?) metal oxide layer on the chalcogenide material by cyclically exposing the substrate to a low-? metal precursor and an oxygen precursor comprising O2, wherein the low-? metal of the metal precursor has an electronegativity of 1.6 or lower.

Abstract: An integrated circuit (IC) device includes a plurality of TAP cells arranged at intervals in a first direction and a second direction transverse to the first direction. The plurality of TAP cells includes at least one first TAP cell. The first TAP cell includes two first end areas and a first middle area arranged consecutively in the second direction. The first middle area includes a first dopant of a first type implanted in a first well region of the first type. The first end areas are arranged on opposite sides of the first middle area in the second direction. Each of the first end areas includes a second dopant of a second type implanted in the first well region, the second type different from the first type.

Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, and a resistive layer provided between the first electrode and the second electrode, containing at least one of antimony (Sb) and bismuth (Bi) as a first element, and tellurium (Te) as a second element, and having a variable resistance value. The resistive layer includes a first layer having a hexagonal crystal structure containing the first element and the second element. The first layer contains a group 14 element as a third element.

Abstract: In some embodiments, an image sensor is provided. The image sensor comprises a first photodetector disposed within a front-side surface of a semiconductor substrate. A trench isolation structure is disposed over a back-side surface of the semiconductor substrate. The trench isolation structure includes a buffer layer and a dielectric liner. The buffer layer covers the back-side surface of the semiconductor substrate and fills trenches that extend downward into the back-side surface of the semiconductor substrate. The dielectric liner is disposed between the buffer layer and the semiconductor substrate. A composite grid structure has composite grid segments that are aligned over the trenches, respectively. The buffer layer separates the dielectric liner from the composite grid structure. A light shield structure is disposed within the buffer layer and directly overlies the first photodetector.

Abstract: A semiconductor substrate includes a first main surface and a second main surface opposing each other. The semiconductor substrate includes a first semiconductor region of a first conductivity type, and a plurality of second semiconductor regions constituting pn junctions with the first semiconductor region. The semiconductor substrate includes the plurality of second semiconductor in a side of the second main surface. Each of the plurality of second semiconductor regions includes a first region including a textured surface, and a second region including no textured surface. A thickness of the first region at a deepest position of recesses of the textured surface is smaller than a distance between a surface of the second region and the deepest position in a thickness direction of the semiconductor substrate. The first main surface is a light incident surface of the semiconductor substrate.

Abstract: A method of forming a memory device includes the following operations. A first conductive plug is formed within a first dielectric layer over a substrate. A treating process is performed to transform a portion of the first conductive plug into a buffer layer, and the buffer layer caps the remaining portion of the first conductive plug. A phase change layer and a top electrode are sequentially formed over the buffer layer. A second dielectric layer is formed to encapsulate the top electrode and the underlying phase change layer. A second conductive plug is formed within the second dielectric layer and in physical contact with the top electrode. A filamentary bottom electrode is formed within the buffer layer.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.

Abstract: Back-illuminated DUV/VUV/EUV radiation or charged particle image sensors are fabricated using a method that utilizes a plasma atomic layer deposition (plasma ALD) process to generate a thin pinhole-free pure boron layer over active sensor areas. Circuit elements are formed on a semiconductor membrane's frontside surface, and then an optional preliminary hydrogen plasma cleaning process is performed on the membrane's backside surface. The plasma ALD process includes performing multiple plasma ALD cycles, with each cycle including forming an adsorbed boron precursor layer during a first cycle phase, and then generating a hydrogen plasma to convert the precursor layer into an associated boron nanolayer during a second cycle phase. Gasses are purged from the plasma ALD process chamber after each cycle phase. The plasma ALD cycles are repeated until the resulting stack of boron nanolayers has a cumulative stack height (thickness) that is equal to a selected target thickness.

Abstract: A packaging structure for an image sensor used in an electronic device includes a flexible circuit board, a reinforcing plate, an image sensor, and an adhesive layer. The reinforcing plate is disposed on the flexible circuit board. The image sensor is disposed in the reinforcing plate. The adhesive layer bonds the flexible circuit board, the reinforcing plate, the image sensor and the conductor.

Abstract: A backside illuminated image sensor and a method of manufacturing the same are disclosed. The backside illuminated image sensor includes a substrate having a frontside surface, a backside surface and a recess formed in a backside surface portion thereof, pixel regions disposed in the substrate, an insulating layer disposed on the frontside surface of the substrate, a bonding pad disposed on a frontside surface of the insulating layer, a second bonding pad formed with a constant thickness on a bottom surface and an inner side surface of the recess to form a second recess in the recess and electrically connected with the bonding pad, and a third bonding pad formed in the second recess to fill the second recess.

Abstract: A method of forming a semiconductor device includes forming a first dummy gate structure and a second dummy gate structure over a fin; forming a first dielectric layer around the first dummy gate structure and around the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure to form a first recess and a second recess in the first dielectric layer, respectively; forming a gate dielectric layer in the first recess and the second recess; forming a first work function layer over the gate dielectric layer in the first and the second recesses; removing the first work function layer from the first recess; converting a surface layer of the first work function layer in the second recess into an oxide; and forming a second work function layer in the first recess over the gate dielectric layer and in the second recess over the oxide.

Abstract: Frame wiring lines are provided in a frame region, a flattening film in which a frame-shaped slit is formed in the frame region is provided in the display region and the frame region, a plurality of first electrodes constituting light-emitting elements are provided on the flattening film, and conductive layer made of the same material and formed in the same layer as those of each of the plurality of first electrodes are provided covering at least end faces of the frame wiring lines exposed from the slit.

Abstract: A manufacturing method of a package-on-package structure includes at least the following steps. Top packages are mounted on a top side of a reconstructed wafer over a flexible tape, where conductive bumps at a bottom side of the reconstructed wafer is attached to the flexible tape, and during the mounting, a shape geometry of the respective conductive bump changes and at least a lower portion of the respective conductive bump is embraced by the flexible tape. The flexible tape is released from the conductive bumps after the mounting.

Abstract: In an embodiment, a device includes: a first metallization layer over a substrate, the substrate including active devices; a first bit line over the first metallization layer, the first bit line connected to first interconnects of the first metallization layer, the first bit line extending in a first direction, the first direction parallel to gates of the active devices; a first phase-change random access memory (PCRAM) cell over the first bit line; a word line over the first PCRAM cell, the word line extending in a second direction, the second direction perpendicular to the gates of the active devices; and a second metallization layer over the word line, the word line connected to second interconnects of the second metallization layer.