Patents Examined by Mounir S Amer
  • Patent number: 11508859
    Abstract: The disclosure discloses a method for forming a doped epitaxial layer of contact image sensor. Epitaxial growth is performed in times. After each time of epitaxial growth, trench isolation and ion implantation are performed to form deep and shallow trench isolation running through a large-thickness doped epitaxial layer. Through cyclic operation of epitaxial growth, trench isolation and ion implantation, the photoresist and hard mask required at each time do not need to be too thick. In the process of trench isolation and ion implantation, the photoresist and etching morphologies are good, such that the lag problem of the prepared contact image sensor is improved. By forming the large-thickness doped epitaxial layer by adopting the method for forming the doped epitaxial layer of the contact image sensor, a high-performance contact image sensor applicable to high quantum efficiency, small pixel size and near infrared/infrared can be prepared.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: November 22, 2022
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Chenchen Qiu, Jun Qian, Chang Sun, Zhengying Wei
  • Patent number: 11508618
    Abstract: Methods of forming and processing semiconductor devices which utilize the selective etching of aluminum oxide over silicon oxide, silicon nitride, aluminum oxide or zirconium oxide are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: November 22, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Yung-Chen Lin, Qingjun Zhou, Ying Zhang, Ho-yung David Hwang
  • Patent number: 11502253
    Abstract: A phase transformation electronic device comprises: a first conductive layer; a second conductive layer opposite to and spaced from the first conductive layer; a phase transformation material layer disposed between the first conductive layer and the second conductive layer, wherein the phase transformation material layer is formed by a hydrogen-containing transition metal oxide having a structural formula of ABOxHy, wherein A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5; and an ionic liquid layer disposed between the phase transformation material layer and the first conductive layer, wherein the ionic liquid layer is capable of providing hydrogen ions and oxygen ions.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: November 15, 2022
    Assignee: TSINGHUA UNIVERSITY
    Inventors: Pu Yu, Nian-Peng Lu, Jian Wu, Shu-Yun Zhou
  • Patent number: 11502132
    Abstract: A semiconductor memory device including a substrate; a first conductive line on the substrate and extending in a first direction that is parallel to an upper surface of the substrate; a second conductive line extending in a second direction that intersects the first direction; a memory cell between the conductive lines and including a lower electrode pattern, a data storage element, an intermediate electrode pattern, a switching element, and an upper electrode pattern sequentially stacked on the first conductive line; and a sidewall spacer on a side surface of the memory cell, wherein the side surface of the memory cell includes a first concave portion at a side surface of the switching element, and the sidewall spacer includes a first portion on a side surface of the upper electrode pattern, and a second portion on the first concave portion, the second portion being thicker than the first portion.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: November 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinwook Yang, Gyuhwan Oh, Junhwan Paik, Jiyoon Chung
  • Patent number: 11500293
    Abstract: A semiconductor structure comprises a semiconductor substrate, and a multi-layer patterning material film stack formed on the semiconductor substrate. The patterning material film stack comprises at least a hard mask layer and a resist layer formed over the hard mask layer. The hard mask layer is configured to support selective deposition of a metal-containing layer on a developed pattern of the resist layer through inclusion in the hard mask layer of one or more materials inhibiting deposition of the metal-containing layer on portions of the hard mask layer corresponding to respective openings in the resist layer. The hard mask layer illustratively comprises, for example, at least one of a grafted self-assembled monolayer configured to inhibit deposition of the metal-containing layer, and a grafted polymer brush material configured to inhibit deposition of the metal-containing layer.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ekmini Anuja De Silva, Indira Seshadri, Jing Guo, Ashim Dutta, Nelson Felix
  • Patent number: 11495462
    Abstract: A method for forming reliefs on a face of a substrate is provided, successively including forming a protective screen for protecting at least a first zone of the face; an implanting to introduce at least one species comprising carbon into the substrate from the face of the substrate, the forming of the protective screen and the implanting being configured to form, in the substrate, at least one carbon modified layer having a concentration of implanted carbon greater than or equal to an etching threshold only from a second zone of the face of the substrate not protected by the protective screen; removing the protective screen; and etching the substrate from the first zone selectively with respect to the second zone.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: November 8, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Lamia Nouri, Stefan Landis, Nicolas Posseme
  • Patent number: 11489113
    Abstract: A memory cell includes a storage element layer, a bottom electrode, a top electrode and a liner layer. The storage element layer has a first surface and a concaved second surface opposite to the first surface. The bottom electrode is disposed on the first surface and connected to the storage element layer. The top electrode is on the concaved second surface and connected to the storage element layer. The liner layer is surrounding the storage element layer and the top electrode.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: November 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Yu-Chao Lin
  • Patent number: 11489015
    Abstract: A solid state image sensor includes a semiconductor substrate where photoelectric conversion regions for converting light into charges are arranged per pixel planarly arranged; an organic photoelectric conversion film laminated at a light irradiated side of the semiconductor substrate via an insulation film and formed at the regions where the pixels are formed; a lower electrode formed at and in contact with the organic photoelectric conversion film at a semiconductor substrate side; a first upper electrode laminated at a light irradiated side of the organic photoelectric conversion film and formed such that ends of the first upper electrode are substantially conform with ends of the organic photoelectric conversion film when the solid state image sensor is planarly viewed; and a film stress suppressor for suppressing an effect of a film stress on the organic photoelectric conversion film, the film stress being generated on the first upper electrode.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: November 1, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Masahiro Joei, Kaori Takimoto
  • Patent number: 11482442
    Abstract: A subring for holding tape connected to semiconductor dies and spanning a passage in a frame having a first diameter includes a base. An opening extends through the base and has a second diameter at least as large as the first diameter. A projection extends from the base to ends positioned on opposite sides of the base. The projection is adapted to clamp the tape to the frame and adapted to prevent relative movement between the tape, the subring, and the frame.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: October 25, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Matthew John Sherbin, Michael Todd Wyant, Dave Charles Stepniak, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
  • Patent number: 11476295
    Abstract: Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shuang-Ji Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang, Hsiao-Hui Tseng
  • Patent number: 11476418
    Abstract: A semiconductor structure may include a heater surrounded by a second dielectric layer, a projection liner on top of the second dielectric layer, and a phase change material layer above the projection liner. A top surface of the projection liner may be substantially flush with a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: October 18, 2022
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Ruqiang Bao, Andrew Herbert Simon, Kevin W. Brew, Nicole Saulnier, Iqbal Rashid Saraf, Prasad Bhosale
  • Patent number: 11462702
    Abstract: A light-emitting element having low driving voltage and high emission efficiency is provided. In the light-emitting element, a combination of a guest material and a host material forms an exciplex. The guest material is capable of converting triplet excitation energy into light emission. Light emission from the light-emitting layer includes light emission from the guest material and light emission from the exciplex. The percentage of the light emission from the exciplex to the light emission from the light-emitting layer is greater than 0 percent and less than or equal to 60 percent. The energy after subtracting the energy of light emission from the exciplex from the energy of light emission from the guest material is greater than 0 eV and less than or equal to 0.23 eV.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: October 4, 2022
    Inventors: Satomi Mitsumori, Takeyoshi Watabe, Satoshi Seo, Yuko Kubota
  • Patent number: 11462624
    Abstract: A vertical semiconductor triode includes a first layer of semiconductor material, the first layer including first and second surfaces, the first surface being in contact with a first electrode forming a Schottky contact.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: October 4, 2022
    Assignee: STMICROELECTRONICS (TOURS) SAS
    Inventor: Samuel Menard
  • Patent number: 11462629
    Abstract: Transistors might include first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: October 4, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 11456413
    Abstract: A method for forming an in-situ drift-mitigation liner on a sidewall of a phase-change material (PCM) device stack includes providing an intermediate device including a substrate including a bottom wiring portion, a bottom electrode metal layer, a drift-mitigation liner layer, an active area layer, a carbon layer, a top electrode metal layer, patterning the top electrode metal layer to form a top electrode, performing a first intermediate angle ion beam etch (IBE), etching the carbon layer and the active area layer, which are formed on the drift-mitigation liner, to form a carbon portion and an active area portion of the PCM device stack, and performing a low angle IBE, etching the drift-mitigation liner and redepositing material etched from the drift-mitigation liner as a conductive liner material on sidewalls of the PCM device stack including exposed portions of the carbon portion, the active area portion, and the top electrode.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: September 27, 2022
    Assignee: International Business Machines Corporation
    Inventors: Karthik Yogendra, Praneet Adusumilli
  • Patent number: 11456360
    Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: September 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tetsuji Ueno, Ming-Hua Yu, Chan-Lon Yang
  • Patent number: 11456417
    Abstract: A mushroom type phase change memory (PCM) cell includes a projection liner located between a PCM volume and a bottom electrode. The projection liner has been retained from a layer previously utilized as an etch stop layer during the fabrication of PCM cell and/or the fabrication of the higher level IC device. The projection liner may extend beyond the PCM sidewall(s) or side boundary. This section of the projection liner may be located or buried under a dielectric or an encapsulation spacer and may increase thickness uniformity of the projection liner below the PCM volume.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: September 27, 2022
    Assignee: International Business Machines Corporation
    Inventors: Kevin W. Brew, Injo Ok, Iqbal Rashid Saraf, Nicole Saulnier, Matthew Joseph BrightSky, Robert L. Bruce
  • Patent number: 11456419
    Abstract: A variable resistance memory device includes first conductive lines, second conductive lines arranged on the first conductive lines, first cell structures at intersections between the first conductive lines and the second conductive lines, each first cell structure including a switching pattern and a variable resistance pattern, first buried structures filling first trenches between the first conductive lines, and second buried structures filling second trenches between the first cell structures. Each first buried structure includes a first liner pattern covering sidewalls of a corresponding first trench, a first filling pattern being disposed on the first liner pattern and in the corresponding first trench, and a first capping pattern sealing the corresponding first trench. The second buried structures extend in the plurality of second trenches and are connected with first capping patterns of the first buried structures.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: September 27, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Juhyun Moon, Youngju Kwak, Seunghan Yoo
  • Patent number: 11451189
    Abstract: The method of the present invention improves mechanical integrity of a crystalline silicon solar cell having an exposed layer of n-type silicon. A solution of electrically-conductive nanowires in an inert liquid is sprayed onto the exposed layer in order to form a grid pattern of the nanowires on the exposed layer after the inert liquid dries or evaporates.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: September 20, 2022
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Edward E. Foos, Richard Jason Jouet
  • Patent number: 11444126
    Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes word lines, channel layer, gate dielectric layers, a conductive pillar and a storage pillar. The word lines extend along a first direction over a substrate, and are vertically spaced apart from one another. The channel layers respectively line along a sidewall of one of the word lines. The gate dielectric layers respectively line between one of the word lines and one of the channel layers. The conductive pillar and the storage pillar penetrate through the channel layers. The storage pillar includes an inner electrode, a switching layer and an outer electrode. The switching layer wraps around the inner electrode. The outer electrode laterally surrounds the switching layer, and includes annulus portions vertically spaced apart from one another and each in lateral contact with a corresponding one of the channel layers.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: September 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-I Wu, Yu-Ming Lin