Abstract: A light-emitting device includes a plurality of light-emitting elements, a plurality of light-transmissive members, a covering member, and a plurality of pairs of electrodes. The light-emitting elements are arranged in a plurality of columns and a plurality of rows. The covering member integrally covers lateral surfaces of the light-emitting elements. The pairs of electrodes are arranged at a lower surface of the light-emitting device. The pairs of electrodes include first and second pairs of electrodes aligned along a column direction so that the electrodes of the same polarity among the first and second pairs of electrodes are aligned along the column direction, and a third pair of electrodes arranged adjacent to the first pair of electrodes in a row direction so that one of the third pair of electrodes and one of the first pair of electrodes facing each other in the row direction have the same polarity.

Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.

Abstract: An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.

Abstract: A display panel and a manufacturing method are provided. The present disclosure can reduce process steps of the display panel by disposing a first source electrode and a first drain electrode of a low temperature polysilicon thin film transistor and a second source electrode and a second drain electrode of an oxide thin film transistor in a same layer. Therefore, stability of the oxide thin film transistor can be improved, a channel length of the oxide thin film transistor can be shortened correspondingly, resolution of the display panel can be improved, and a thickness of the display panel can be reduced.

Abstract: An integrated circuit (IC) device includes a circuit region, a lower metal layer over the circuit region, and an upper metal layer over the lower metal layer. The lower metal layer includes a plurality of lower conductive patterns elongated along a first axis. The upper metal layer includes a plurality of upper conductive patterns elongated along a second axis transverse to the first axis. The plurality of upper conductive patterns includes at least one input or output configured to electrically couple the circuit region to external circuitry outside the circuit region. The upper metal layer further includes a first lateral upper conductive pattern contiguous with and projecting, along the first axis, from a first upper conductive pattern among the plurality of upper conductive patterns. The first lateral upper conductive pattern is over and electrically coupled to a first lower conductive pattern among the plurality of lower conductive patterns.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

Abstract: A memory includes first and second wires. First and second transistors are connected to the first wires and transfer a first and second voltage. Third and fourth transistors are connected to the second wires and transfer the first and second voltages to the second wires. A first memory cell includes a first diode and a first memory element connected in series. The first diode is connected so that a forward bias direction thereof is from the one first wire to the first signal line. A second memory cell includes a second diode and a second memory element connected in series. The second diode is connected so that a forward bias direction thereof is from the second signal line to the one first wire.

Abstract: A semiconductor memory device in which performance is improved by reducing a wiring resistance is provided. The semiconductor memory device comprising an inter-wiring insulation film on a substrate, a first wiring pattern extending in a first direction, in the inter-wiring insulation film, a barrier insulation film that is on an upper surface of the inter-wiring insulation film, a barrier conductive pattern electrically connected to the first wiring pattern, in the barrier insulation film, a memory cell electrically connected to the barrier conductive pattern and including a selection pattern and a variable resistor pattern, and a second wiring pattern extending in a second direction intersecting the first direction, on the memory cell, wherein a width of the barrier conductive pattern in the second direction is different from a width in the second direction of a portion of the memory cell that is adjacent to the barrier conductive pattern.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a semiconductor substrate comprising a front-side surface opposite a back-side surface. A plurality of photodetectors is disposed in the semiconductor substrate. An isolation structure extends into the back-side surface of the semiconductor substrate and is disposed between adjacent photodetectors. The isolation structure includes a metal core, a conductive liner disposed between the semiconductor substrate and the metal core, and a first dielectric liner disposed between the conductive liner and the semiconductor substrate. The metal core comprises a first metal material and the conductive liner comprises the first metal material and a second metal material different from the first metal material.

Abstract: A semiconductor device includes a substrate including a first device region and a second device region, active regions spaced apart from each other on the substrate, having a constant width, extending in a first direction parallel to an upper surface of the substrate and including a first active region and a second active region provided on the first device region and a third active region and a fourth active region provided on the second device region, a plurality of channel layers provided on the active regions and configured to be spaced apart from each other in a direction perpendicular to the upper surface of the substrate, gate structures provided on the substrate and extending to cross the active regions and the plurality of channel layers, and source/drain regions provided on the active regions on at least one side of the gate structures.

Abstract: The present disclosure provides an impedance-matching method applied to a semiconductor process apparatus, an impedance-matching device, and the semiconductor process apparatus. The impedance-matching method includes adjusting a parameter value of an adjustable element of an impedance-matching device to a preset initial value at beginning of a process, when a radio frequency (RF) power supply is powered on, adjusting the parameter value of the adjustable element according to a pre-stored optimal matching path corresponding to the process, and adjusting the parameter value of the adjustable element using an automatic matching algorithm after reaching end time of the preset matching period until impedance-matching is achieved. The optimal matching path includes parameter values of the adjustable element corresponding to different moments in a preset matching period.

Abstract: Integrated circuit structures having a dielectric anchor void, and methods of fabricating integrated circuit structures having a dielectric anchor void, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure. A second portion of the STI structure on a side of the plurality of horizontally stacked nanowires opposite the dielectric anchor has a trench therein. A dielectric gate plug is on the dielectric anchor.

Abstract: A driving backplane, a display panel and a display apparatus are provided. The driving backplane includes: a base substrate, and a plurality of connection electrode groups and a plurality of correction structures disposed on the base substrate, each of the connection electrode groups includes: a first connection electrode and a second connection electrode the first connection electrode and the second connection electrode are arranged on a same layer; a first gap is formed between the first connection electrode and the second connection electrode, and a first group of opposite edges includes: an edge, close to the first gap, of the first connection electrode; and an edge, close to the first gap, of the second connection electrode; a second group of opposite edges includes: an edge, far away from the first gap, of the first connection electrode; and an edge, far away from the first gap, of the second connection electrode.

Abstract: A semiconductor device includes a pair of first and second dummy active regions extending in a first horizontal direction and spaced apart from each other in a second horizontal direction; a pair of first and second circuit active regions extending in the first horizontal direction and spaced apart in the second horizontal direction; and a plurality of line patterns extending in the second horizontal direction and spaced apart in the first horizontal direction. The pair of first and second dummy active regions may be between a pair of line patterns adjacent to each other among the plurality of line patterns. At least one of the first and second dummy active regions may have a width-changing portion in which a width of the at least one of the first and second dummy active regions changes in the second horizontal direction between the pair of line patterns adjacent to each other.

Abstract: An image sensor comprises a first photodiode, a second photodiode, and a deep trench isolation structure. The first photodiode and the second photodiode are each disposed within a semiconductor substrate. The first photodiode is adjacent to the second photodiode. The deep trench isolation structure has a varying depth disposed within the semiconductor substrate between the first photodiode and the second photodiode. The DTI structure extends the varying depth from a first side of the semiconductor substrate towards a second side of the semiconductor substrate. The first side of the semiconductor substrate is opposite of the second side of the semiconductor substrate.

Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.

Abstract: A semiconductor device includes a first type of light sensing units, where each instance of the first type of light sensing units is operable to receive a first amount of radiation; and a second type of light sensing units, where each instance of the second type of light sensing units is operable to receive a second amount of radiation, and the second type of light sensing units is arranged in an array with the first type of light sensing units to form a pixel sensor. The first amount of radiation is smaller than the second amount of radiation, and at least a first instance of the first type of light sensing units is adjacent to a second instance first type of light sensing unit.

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, and a storage element layer. The storage element layer is disposed between the bottom and top electrodes. An extending direction of a sidewall of the storage element layer is different from an extending direction of a sidewall of the top electrode. A semiconductor device having the memory cell is also provided.

Abstract: Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.