Patents Examined by Mounir S Amer
-
Patent number: 11903222Abstract: A memory device may include an insulating structure including a first surface and a protrusion portion protruding from the first surface in a first direction, a recording material layer on the insulating structure and extending along a protruding surface of the protrusion portion to cover the protrusion portion and extending onto the first surface of the insulating structure, a channel layer on the recording material layer and extending along a surface of the recording material layer, a gate insulating layer on the channel layer; and a gate electrode formed on the gate insulating layer at a location facing a second surface of the insulating structure. The second surface of the insulating structure may be a protruding upper surface of the protrusion portion.Type: GrantFiled: March 17, 2023Date of Patent: February 13, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Yumin Kim, Seyun Kim, Jinhong Kim, Soichiro Mizusaki, Youngjin Cho
-
Patent number: 11901395Abstract: A method of forming an insulation structure inside and on top of a first semiconductor substrate, including the steps of: a) forming a trench vertically extending in the first substrate from a first surface of the first substrate; b) filling the trench, from the first surface of the first substrate, with a polysilicon region; c) thinning the first substrate on the side of a second surface of the first substrate, opposite to the first surface, to expose the polysilicon region at the bottom of the trench; d) removing the polysilicon region from the second surface of the first substrate; and e) filling the trench, from the second surface of the first substrate, with a metal.Type: GrantFiled: July 7, 2021Date of Patent: February 13, 2024Assignee: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Norbert Moussy, Cédric Giroud-Garampon
-
Patent number: 11901396Abstract: Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate.Type: GrantFiled: January 21, 2021Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shuang-Ji Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang, Hsiao-Hui Tseng
-
Patent number: 11894452Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer; an insulating layer; a first region disposed between the nitride semiconductor layer and the insulating layer and containing at least one element of hydrogen and deuterium; and a second region disposed in the nitride semiconductor layer, adjacent to the first region, and containing fluorine.Type: GrantFiled: December 8, 2021Date of Patent: February 6, 2024Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Masahiko Kuraguchi, Toshiya Yonehara, Akira Mukai
-
Patent number: 11894238Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.Type: GrantFiled: July 11, 2022Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen, Ru-Gun Liu, Shau-Lin Shue, Tsai-Sheng Gau, Yung-Hsu Wu
-
Patent number: 11894456Abstract: A face-down mountable chip-size package semiconductor device includes a semiconductor layer and N (N is an integer greater than or equal to three) vertical MOS transistors in the semiconductor layer. Each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor. The semiconductor layer includes a semiconductor substrate. The semiconductor substrate functions as a common drain region for the N vertical MOS transistors. For each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor.Type: GrantFiled: June 6, 2023Date of Patent: February 6, 2024Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Kouki Yamamoto, Haruhisa Takata
-
Patent number: 11889777Abstract: A semiconductor memory device includes a first wiring to a fifth wiring, a plurality of memory cells disposed between the wirings, and a first contact electrode to a third contact electrode. The first contact electrode is disposed between the first wiring and the fifth wiring, and is electrically connected to the first wiring and the fifth wiring. The second contact electrode is disposed between the first contact electrode and the fifth wiring, and is electrically connected to the first wiring and the fifth wiring. The third contact electrode is disposed between the second contact electrode and the fifth wiring, and is electrically connected to the first wiring and the fifth wiring. The second contact electrode has a width larger than a width of the first contact electrode and larger than a width of the third contact electrode.Type: GrantFiled: May 6, 2022Date of Patent: January 30, 2024Assignee: Kioxia CorporationInventors: Hiroyuki Ode, Kotaro Noda
-
Patent number: 11887896Abstract: Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.Type: GrantFiled: June 13, 2022Date of Patent: January 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yao-Wen Hsu, Ming-Chi Huang, Ying-Liang Chuang
-
Patent number: 11889772Abstract: Methods of manufacturing memory devices, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a memory device includes (a) removing a portion of an insulative material to define a recess, (b) forming a memory stack in the recess, and (c) etching the memory stack to define a plurality of memory elements. In some embodiments, the method can further include forming conductive vias in a remaining portion of the insulative material, and forming a metallization structure electrically coupling the conductive vias to corresponding ones of the memory elements.Type: GrantFiled: June 6, 2022Date of Patent: January 30, 2024Assignee: Micron Technology, Inc.Inventor: Michael B. Jeppson
-
Patent number: 11887818Abstract: Apparatus and methods to control the phase of power sources for plasma process regions in a batch process chamber. A master exciter controls the phase of the power sources during the process sequence based on feedback from the match circuits of the respective plasma sources.Type: GrantFiled: October 11, 2021Date of Patent: January 30, 2024Assignee: Applied Materials, Inc.Inventors: Tsutomu Tanaka, John C. Forster, Ran Liu, Kenichi Ohno, Ning Li, Mihaela Balseanu, Keiichi Tanaka, Li-Qun Xia
-
Patent number: 11882708Abstract: A method of manufacturing an electronic device comprises: forming a plurality of line patterns on a substrate extending in a first direction and including a first conductive line and a memory pattern; forming a first liner layer on sidewalls of each of the plurality of line patterns, the first liner layer including a plurality of layers having different energy band gaps; forming an insulating interlayer on the substrate; forming a plurality of second conductive lines on the line patterns and the insulating interlayer; etching the first liner layer, the insulating interlayer and the memory pattern using the second conductive lines as an etch barrier to expose the first conductive line to form a plurality of memory cells; and forming a second liner layer on both sidewalls of each of the memory cells, the etched first liner layer and both sidewalls of the etched insulating interlayer.Type: GrantFiled: March 31, 2023Date of Patent: January 23, 2024Assignee: SK hynix Inc.Inventor: Sung Kil Seo
-
Patent number: 11877523Abstract: Embodiments of a Majorana-based qubit are disclosed herein. The qubit is based on the formation of superconducting islands, some parts of which are topological (T) and some parts of which are non-topological. Also disclosed are example techniques for fabricating such qubits. In one embodiment, a semiconductor nanowire is grown, the semiconductor nanowire having a surface with an oxide layer. A dielectric insulator layer is deposited onto a portion of the oxide layer of the semiconductor nanowire, the portion being designed to operate as a non-topological segment in the quantum device. An etching process is performed on the oxide layer of the semiconductor nanowire that removes the oxide layer at the surface of the semiconductor nanowire but maintains the oxide layer in the portion having the deposited dielectric insulator layer. A superconductive layer is deposited on the surface of the semiconductor nanowire, including over the dielectric insulator layer.Type: GrantFiled: July 7, 2021Date of Patent: January 16, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Roman Lutchyn, Michael Freedman, Andrey Antipov
-
Patent number: 11869939Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.Type: GrantFiled: March 24, 2022Date of Patent: January 9, 2024Assignee: Sony Group CorporationInventors: Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong, Rafael Rios, Abhijit Jayant Pethe, Willy Rachmady
-
Patent number: 11869919Abstract: A sensor device includes: a semiconductor substrate having a sensing region which extends vertically below a main surface region of the semiconductor substrate into the substrate; a semiconductor capping layer that extends vertically below the main surface region into the substrate; a buried deep trench structure that extends vertically below the capping layer into the substrate and laterally relative to the sensing region, the buried deep trench structure including a doped semiconductor layer that extends from a surface region of the buried deep trench structure into the substrate; a trench doping region that extends from the doped semiconductor layer of the buried deep trench structure into the substrate; and electronic circuitry for the sensing region in a capping region of the substrate vertically above the buried deep trench structure. Methods of manufacturing the sensor device are also provided.Type: GrantFiled: November 25, 2020Date of Patent: January 9, 2024Assignee: Infineon Technologies Dresden GmbH & Co. KGInventors: Magali Glemet, Boris Binder, Henning Feick, Dirk Offenberg
-
Patent number: 11864477Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, and a storage element layer. The storage element layer is disposed between the bottom and top electrodes. The storage element layer has a first inclined sidewall, the top electrode has a second inclined sidewall, and an angle of the first inclined sidewall is greater than an angle of the second inclined sidewall. A semiconductor device having the memory cell is also provided.Type: GrantFiled: April 27, 2022Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chao Lin, Tung-Ying Lee
-
Patent number: 11854898Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: GrantFiled: May 17, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
-
Patent number: 11849570Abstract: A semiconductor memory device and associated methods, the device including first and second lower conductive lines extending in a first direction; a first middle conductive line on the first and second lower conductive lines and extending in a second direction; first and second memory cells between the first and second lower conductive lines and the first middle conductive line; an air gap support layer between the first and second memory cells; and a first air gap between the first and second memory cells and under the air gap support layer, wherein an upper surface of the air gap support layer lies in a same plane as the first and second memory cells, the first and second memory cells include first and second OTS layers and first and second phase-change layers, and the first air gap overlaps the first and second phase-change layers.Type: GrantFiled: June 16, 2021Date of Patent: December 19, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byeong Ju Bae, Seung-Heon Lee, Ik Soo Kim, Byoung Deog Choi
-
Patent number: 11839166Abstract: A resistive random access memory (RRAM) device may be provided, including: a base layer, a vertical electrode stack arranged over the base layer, where the vertical electrode stack may include alternating mask elements and first electrodes, and each first electrode may include an extended portion extending beyond at least one side surface of at least one mask element adjoining the first electrode, a switching layer arranged along the extended portion of each first electrode and along the at least one side surface of the at least one mask element adjoining the first electrode, and a second electrode including a surface in contact with the switching layer. The RRAM device may have a 3D structure.Type: GrantFiled: April 6, 2020Date of Patent: December 5, 2023Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Xinshu Cai, Shyue Seng Tan, Eng Huat Toh
-
Patent number: 11832536Abstract: A resistive memory device includes a first stacked structure and a second stacked structure. The first stacked structure includes a first bottom electrode, a first top electrode disposed on the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode in a vertical direction. The second stacked structure includes a second bottom electrode, a second top electrode disposed on the second bottom electrode, and a second variable resistance layer disposed between the second bottom electrode and the second top electrode in the vertical direction. A thickness of the first variable resistance layer is less than a thickness of the second variable resistance layer for increasing the number of switchable resistance states of the resistive memory device.Type: GrantFiled: June 7, 2022Date of Patent: November 28, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventor: Po-Yu Yang
-
Patent number: 11822099Abstract: An array imaging module includes a molded photosensitive assembly which includes a supporting member, at least a circuit board, at least two photosensitive units, at least two lead wires, and a mold sealer. The photosensitive units are coupled at the chip coupling area of the circuit board. The lead wires are electrically connected the photosensitive units at the chip coupling area of the circuit board. The mold sealer includes a main mold body and has two optical windows. When the main mold body is formed, the lead wires, the circuit board and the photosensitive units are sealed and molded by the main mold body of the mold sealer, such that after the main mold body is formed, the main mold body and at least a portion of the circuit board are integrally formed together at a position that the photosensitive units are aligned with the optical windows respectively.Type: GrantFiled: December 7, 2020Date of Patent: November 21, 2023Assignee: NINGBO SUNNY OPOTECH CO., LTD.Inventors: Mingzhu Wang, Bojie Zhao, Takehiko Tanaka, Nan Guo, Zhenyu Chen, Heng Jiang, Zhongyu Luan, Fengsheng Xi, Feifan Chen, Liang Ding