Abstract: A memory device includes a substrate including a memory cell region and a dummy cell region, a plurality of first conductive lines disposed on the substrate and extending in a first direction, a plurality of second conductive lines disposed on the substrate and extending in a second direction, and a plurality of memory cells formed at intersections of the plurality of first conductive lines and the plurality of second conductive lines. Each of the plurality of memory cells includes a switching unit and a variable resistance memory unit. Each of the plurality of first conductive lines includes a first conductive line main region disposed in the memory cell region, and a first conductive line edge region disposed in the dummy cell region and spaced apart from the first conductive line main region.

Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are respectively formed in the first dielectric layer on the memory region and the logic region. A memory cell is formed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer continuously covers a top surface and a sidewall of the memory cell and directly contacts a top surface of the second conductive structure. A second dielectric layer is formed on the first cap layer. A third conductive structure penetrates through the second dielectric layer and the first cap layer to contact the memory cell.

Abstract: A phase change memory device based on a nano current channel is provided. A nano current channel layer structure is adopted and configured to limit the current channel. As such, when flowing through the layer, the current enters the phase change layer from nano crystal grains with high electrical conductivity, and the current is thereby confined in the nano current channels. By using the nano-scale conductive channels, the contact area between the phase change layer and the electrode layer is significantly decreased, the current density at local contact channel is significantly increased, and heat generation efficiency of the current in the phase change layer is improved. Moreover, an electrically insulating and heat-insulating material with low electrical conductivity and low thermal conductivity prevents heat in the phase change layer from being dissipated to the electrode layer, and Joule heat utilization efficiency of the phase change layer is thereby improved.

Abstract: This disclosure relates to a low-resistance a multi-layer electrode and method of making a multi-layer electrode. Silicon is deposited on a substrate to form a top silicon layer. Nickel is deposited onto the top silicon layer to form a nickel layer. The substrate is annealed for a first time period and at a first temperature to form a di-nickel silicide layer with a remainder silicon layer between the di-nickel silicide layer and the substrate. Unreacted nickel of the nickel layer is removed to expose the di-nickel silicide layer. The substrate is annealed for a second time period and at a second temperature to form a nickel monosilicide layer from the di-nickel silicide layer and the remainder silicon layer such that the nickel monosilicide layer forms between a remainder di-nickel silicide layer and the substrate. The remainder di-nickel silicide layer and nickel monosilicide layer form a multi-layer electrode.

Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.

Abstract: A system and method for thermally calibrating semiconductor process chambers is disclosed. In various embodiments, a first non-contact temperature sensor can be calibrated to obtain a first reading with the semiconductor process chamber. The first reading can be representative of a first temperature at a first location. The first non-contact temperature sensor can be used to obtain a second reading representative of a second temperature of an external thermal radiation source. The second temperature of the external thermal radiation source can be adjusted to a first temperature setting of the external radiation source such that the second reading substantially matches the first reading. Additional non-contact temperature sensor(s) can be directed at the external thermal radiation source and can be adjusted such that the reading(s) of the additional non-contact sensors are calibrated and matched to one another.

Abstract: Memory devices and methods of forming the same are provided. A memory device includes a substrate, a first conductive layer, a phase change layer, a selector layer and a second conductive layer. The first conductive layer is disposed over the substrate. The phase change layer is disposed over the first conductive layer. The selector layer is disposed between the phase change layer and the first conductive layer. The second conductive layer is disposed over the phase change layer. In some embodiments, at least one of the phase change layer and the selector layer has a narrow-middle profile.

Abstract: A patch on interposer (PoINT) package is described with a wireless communications interface. Some examples include an interposer, a main patch attached to the interposer, a main integrated circuit die attached to the patch, a second patch attached to the interposer, and a millimeter wave radio die attached to the second patch and coupled to the main integrated circuit die through the interposer to communicate data between the main die and an external component.

Abstract: An integrated circuit including a first active region and a second active region extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a power rail and a ground rail extending in the first direction and spaced apart from the first and second active regions and each other in the second direction; source/drain contacts extending in the second direction on at least a portion of the first or second active region, gate structures extending in the second direction and on at least a portion of the first and second active regions, a power rail configured to supply power through source/drain contact vias, and a ground rail configured to supply a ground voltage through source/drain contact vias.

Abstract: A method of fabricating a device, wherein the device comprises a plurality of lengths of material and at least one junction joining two or more of the lengths of material. In a masking phase, a mask is formed on an underlying layer of the device. The mask comprises a plurality of trenches exposing the underlying layer, each trench corresponding to one of the lengths of material. A respective section of two or more of the trenches either (a) narrow down, or (b) are separated by a discontinuity, at a position corresponding to the at least one junction. In a selective area growth phase, material is grown in the set of trenches to form the lengths of material on the underlying layer. The two or more lengths of material are joined at the at least one junction.

Abstract: A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (BEOL) metallization stack, and including a scribe line opening; a conductive pad having an upper surface that is substantially flush with an upper surface of the semiconductor substrate, the conductive pad including an upper conductive region and a lower conductive region, the upper conductive region being confined to the scribe line opening substantially from the upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower conductive region protruding downward from the upper conductive region, through the BEOL metallization stack; a passivation layer arranged over the semiconductor substrate; and an array of pixel sensors arranged in the semiconductor substrate adjacent to the conductive pad.

Abstract: Provided are a memory device and a method of forming the same. The memory device includes a plurality of bit lines extending along a first direction; a plurality of word lines extending along a second direction different from the first direction; a plurality of memory pillars; and a selector. The plurality of word lines are disposed over the plurality of bit lines. The plurality of memory pillars are disposed between the plurality of bit lines and the plurality of word lines, and respectively positioned at a plurality of intersections of the plurality of bit lines and the plurality of word lines. The selector is disposed between the plurality of memory pillar and the plurality of word lines. The selector extends from a top surface of one memory pillar to cover a top surface of an adjacent memory pillar. A semiconductor device having the memory device is also provided.

Abstract: An imaging device includes a photoelectric converter, a charge holding section that is provided on a side of the photoelectric converter opposite to a light entrance side of the photoelectric converter and holds a signal charge generated by the photoelectric converter, and a light shielding section that has a first light shielding surface extending toward the charge holding section from between the charge holding section and the photoelectric converter.

Abstract: A semiconductor device includes a semiconductor part including a first surface, a second surface, a first region provided between the first surface and the second surface, and a second region provided between the first surface and the second surface; a common electrode provided at the second surface; a first electrode provided on the first surface at the first region; a second electrode provided on the first surface at the second region and separated from the first electrode; a first control electrode provided in the first region; and a second control electrode provided in the second region. A first trench is provided in the common electrode.

Abstract: A three-dimensional (3D) semiconductor memory device including first cell stacks arranged in first and second directions; second cell stacks disposed on the first cell stacks and arranged in the first and second directions; first conductive lines extending in the first direction and provided between a substrate and the first cell stacks; common conductive lines extending in the second direction and provided between the first and second cell stacks; etch stop patterns extending in the second direction and provided between the common conductive lines and top surfaces of the first cell stacks; second conductive lines extending in the first direction and provided on the second cell stacks; and a capping pattern covering a sidewall of the common conductive lines and a sidewall of the etch stop patterns, wherein each of the common conductive lines has a second thickness greater than a first thickness of each of the first conductive lines.

Abstract: Aspects of the present invention provide a semiconductor structure for a phase change memory device that includes a heater element on a bottom electrode that is surrounded by a dielectric material. The phase change memory device includes a metal nitride liner over the heater element, where the metal liner is oxide-free with a desired electrical resistance. The phase change memory device includes a phase change material is over the heater element and the dielectric material and a top electrode is over the phase change material.

Abstract: A method of fabricating an electronic device including a semiconductor memory includes forming a first conductive structure extending in a first direction and having a closed-loop shape, forming a second conductive structure extending in a second direction and having a closed-loop shape, the second direction intersecting the first direction, forming a memory cell located at an intersection of the first conductive structure and the second conductive structure, forming first conductive patterns extending in the first direction by etching an end portion of the first conductive structure, forming second conductive patterns extending in the second direction by etching an end portion of the second conductive structure, forming a first protective layer on an etched surface of each of the first conductive patterns and the second conductive patterns, and forming a gap-fill layer on the first protective layer.

Abstract: Disclosed herein is an apparatus that includes: a first diffusion region extending in a first direction; second diffusion regions arranged in the first direction; a first metallic line overlapping with the first diffusion region; second metallic lines each overlapping with an associated one of the second diffusion regions; a third metallic line overlapping with the first and second metallic lines; first contact plugs connecting the first metallic line to the first diffusion region; second contact plugs each electrically connecting an associated one of the second metallic lines to an associated one of the second diffusion regions; and third contact plugs each electrically connecting the third metallic line to an associated one of the second metallic lines.

Abstract: A memory device and method of making the same is provided. The memory device comprises a first electrode having a length along a first axis, a second electrode having a length along a second axis that is perpendicular to the first axis, and a switching layer adjacent to the first electrode. A portion of the switching layer is positioned between a first electrode edge and a second electrode portion. The cross-sections of the first and second electrodes may have a polygonal shape.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a lower conductive structure over a substrate. A data storage structure is formed on the lower conductive structure. A bandgap of the data storage structure discretely increases or decreases at least two times from a top surface of the data storage structure in a direction towards the substrate. An upper conductive structure is formed on the data storage structure.