Abstract: An iterative turbo decoder for a wireless transmit receive unit (WTRU) of a wireless communication system and method for error correcting received communication signal data are provided. The decoder implements a stopping rule through use of signature codes to determine whether successive iterations of decoder data are the same.

Abstract: Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.

Abstract: An apparatus for generating a function activation signal to activate a function in an integrated circuit device comprises a power-on circuit receiving a power input and initializing and generating a test activation signal, a test circuit receiving the test activation signal and generating a test result signal, and a threshold decision circuit receiving the test result signal and generating the function activation signal. The test circuit models a function of the integrated circuit device and generates the test result signal when the power input has reached a sufficient voltage to perform the function of the integrated circuit device. The threshold decision circuit generates the function activation signal if the test result signal indicates the power input has reached a sufficient voltage to perform the function of the integrated circuit device.

Abstract: A path-select-signal memory section in the Viterbi detector outputs each decoded data B?Sik corresponding to a branch that occurred a prescribed time ago in a surviving path to each state at a present time, in response to path select signals SEL0, SEL1. A shift register stores the path select signals SEL0, SEL1 in order of time. A binary output unit outputs a decoded bit corresponding to a branch that occurred a prescribed time ago in a surviving path. Output signal lines of the binary output unit and a selector train are connected according to a trellis diagram that corresponds to encoding operation.

Abstract: An encoding method and apparatus for a DCH (Dedicated Channel) encoder and a DSCH (Downlink Shared Channel) encoder in a transmitter for a mobile communication system including the DCH encoder for encoding k bits among 10 input TFCI (Transport Format Combination Indicator) bits and the DSCH encoder for encoding remaining (10-k) bits among the input TFCI bits. The method comprises generating, by the DCH encoder, a first coded bit stream by encoding the k input bits into 32 bits, and outputting a (3k+1)-bit stream by puncturing the first coded bit stream according to a specific mask pattern corresponding to the k value; and generating, by the DSCH encoder, a second coded bit stream by encoding the (10-k) input bits into 32 bits, and outputting a {3*(10-k)+1}-bit stream by puncturing the second coded bit stream according to a specific mask pattern corresponding to the (10-k) value.

Abstract: A data sequence may be encoded in a plurality of layers of multiple description coding. The layers of multiple description coding may include a first and a second layer of multiple description coding. The first layer of multiple description coding may include an initial part of a data sequence as well as forward error correction code for the initial part. The second layer of multiple description coding may include a next part of the data sequence as well as forward error correction code for the next part. A first set of data sequence breakpoints may be determined for the first layer of multiple description coding. A second set of data sequence breakpoints may be determined for the second layer. The data sequence may be encoded in the plurality of layers of multiple description coding as a function of the first and second sets of data sequence breakpoints.

Abstract: A method for generating error detection code is disclosed. Firstly, a first error detection code PEDC is derived by using 12-byte unknown sector data information including ID, IED, RSV and the 2048-byte main data while the main data is delivered from a host. Secondly, a second error detection code MEDC is obtained by using known 12-byte sector data information including ID, IED, RSV and the 2048-byte main data. Thereafter, the real error detection code EDC is obtained by applying an exclusive-OR operation to both the PEDC and MEDC.

Abstract: A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused.

Abstract: The invention relates to a Reed-Solomon decoder and to a method of soft decision decoding of Reed-Solomon codes, wherein a syndrome polynomial, an erasure polynomial, and a modified syndrome polynomial are computed on-the-fly in parallel by iteratively updating coefficients of these polynomials.

Abstract: A flexible and relatively hardware efficient LDPC encoder is described. The encoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the encoding process. Each command of a relatively simple microcode used to describe the code structure can be stored and executed multiple times to complete the encoding of a codeword. Different codeword lengths can be supported using the same set of microcode instructions but with the code being implemented a different number of times depending on the lifting factor selected to be used. The LDPC encoder can switch between encoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor used to control the encoding processes. When coding codewords shorter than the maximum supported codeword length some block storage locations and/or registers may go unused.

Abstract: A content addressable memory (CAM). A data portion of the CAM array includes word data storage. Each word line includes CAM cells (dynamic or static) in the data portion and a common word match line. An error correction (e.g., parity) portion of the CAM array contains error correction cells for each word line. Error correction cells at each word line are connected to an error correction match line. A match on an error correction match line enables precharging a corresponding data match line. Only data on word lines with a corresponding match on an error correction match line are included in a data compare. Precharge power is required only for a fraction (inversely exponentially proportional to the bit length of error correction employed) of the full array.

Abstract: A data driven clock recovery system comprising a viterbi detector for detecting data and tentatively deciding the closest approximation, and a circuit for retrieving the tentative decision in stages. Preferably, the clock recovery system further comprises a combination series-parallel comparison circuit for selecting one value of a set of values for input to the viterbi and for applying said one value to the viterbi.

Abstract: A method for designing a new prunable S-random interleaver class to be used as a constituent part of turbo codes. With respect to previously proposed solutions the method has the advantage of being prunable to different block sizes while exhibiting at the same time, for any considered block size, performance comparable with the optimized “ad hoc” S-random interleavers. Another advantage is that, as for every S-random interleaver, the design rules are independent of the constituent codes and of the puncturing rate applied to the turbo code. Therefore, these interleavers potentially can find applications in any turbo code scheme that requires interleaver size flexibility and code rate versatility, thanks to the advantage of requiring a single law storage (i e., one ROM storage instead of several ROMs) from which all the others are obtained by pruning, without compromising the overall error rate performance.

Abstract: A data storage comprises memory having a plurality of memory cells operative to retain data until read. A buffer cooperates, under the control of an address and buffer manager, with the memory to receive data read from the memory cells of a plurality of memory blocks of the memory. Error correction logic is operatively configured to examine the data read from the memory blocks and determine and correct corrupt data thereof. After the data has been processed by the error correction logic, the address and buffer manager enables write circuitry to write-back the select blocks of memory cells with the processed data of the buffer.

Abstract: In an exemplary described implementation, an electronic device is configured to perform operations that include: activate a platform dependent module that is targeted to run on a current platform of the electronic device; activate an error detection module for the current platform using the platform dependent module; retrieve an error detection scheme; apply the retrieved error detection scheme to received data to determine error detection data; compare the determined error detection data to received error detection data; and if the determined error detection data matches the received error detection data, provide at least one feature with respect to the received data. Other apparatus, method, arrangement, system, media, etc. implementations are described herein.

Abstract: Provided are a method, system, and program for generating parity data when updating old data stored in an array of storage devices in a data organization type which utilizes parity data. In one embodiment, a logic engine has plural registers or store queues in which new data obtained in a read operation is stored. A logic function such as an Exclusive-OR function is performed on the new data in each of the plural registers using old data obtained in another read operation. A logic function such as an Exclusive-OR function is performed on the intermediate data in one of the plural registers using old parity data of a first type obtained in another read operation, to generate new parity data of the first type. A logic function such as an Exclusive-OR function is performed on the intermediate data in another of the plural registers using old parity data of a second type obtained in another read operation, to generate new parity data of the second type.

Abstract: A method of embedding an additional layer of error correction into an error correcting code, where information is encoded into code words that are arranged in columns of a code block. The method includes reducing the length of each row of the code block by adding row symbols together according to a predetermined adding rule resulting in a reduced code block; encoding the shortened rows of the reduced code block using a horizontal error correcting code to obtain horizontal parities; and embedding the horizontal parities as additional layer in the error correcting code.

Abstract: A method of decoding possibly mutilated code words (r) of a code (C) includes decoding the differences (D) of a number (L?1) of pairs of possibly mutilated code words (rib, ri+1) to obtain estimates (u, v) for the differences of the corresponding pairs of code words (ci, ci+1), combining the estimates (u, v) to obtain a number (L) of at least two corrupted versions (wj) of a particular code word (c), forming a code vector (z) from the number (L) of corrupted versions (wj) of the particular code word (c) in each coordinate, decoding the code vector (z) to a decoded code word (c?) in the code (C), and using the generator matrix (G) to obtain the information word (m) and the address word (a) embedded in the decoded code word (c?).

Abstract: A method and system for repairing defective memory in a semiconductor chip. The chip has memory locations, redundant memory, and a central location for ordered fuses. The ordered fuses identify in compressed format defective sections of the memory locations. The defective sections are replaceable by sections of the redundant memory. The ordered fuses have an associated a fuse bit pattern of bits which sequentially represents the defective sections in the compressed format. The method and system determines the order in which the memory locations are wired together; designs a shift register of latches through the memory locations in accordance with the order in which the memory locations are wired together; and associates each of the latches with a corresponding bit of an uncompressed bit pattern from which the fuse bit pattern is derived. The uncompressed bit pattern comprises a sequence of bits, representing the defective sections in uncompressed format.

Abstract: The present invention describes direct decoding of Error Correction Codes (ECC) such as, for example, FIRE and similar codes, and detecting and correcting errors occurring in burst, without requiring any pattern shift or sequential logic. According to the present invention, the syndrome of a code generated with a degree-d polynomial is split into sub-syndromes that are combined to form at least one kind of error pattern from which an error pattern is picked. If the picked error pattern does not correspond to an uncorrectable error and errors are not confined within first d bits, one of the sub-syndromes is selected according to the correction mode. The ranks of this selected sub-syndrome and picked error pattern in the Galois field generated by a factor of the degree-d polynomial are determined.