Abstract: A method begins by a processing module of a dispersed storage network (DSN) receiving a DSN retrieval request regarding a data object and performing a scoring function using properties of the DSN retrieval request and properties of DSN memory of the DSN to produce a storage scoring resultant. The method continues with the processing module identifying a set of primary storage units based on the storage scoring resultant and sending a set of retrieval requests to the set of primary storage units. When a primary storage unit does not provide a favorable response, using the storage scoring resultant to identify an alternative storage unit. When the alternative storage unit is identified, sending a corresponding retrieval request to the alternative storage unit.

Abstract: Automatic retransmission in communications systems. In one embodiment, a portion of data is identified to be retransmitted based on feedback information indicating a negative acknowledgement (NACK) during a cyclic redundancy check (CRC) on a previous transmission of the portion of data. A retransmission mode is selected for the portion of data, from at least a first mode that retransmits the portion of data on at least a first transmitter antenna while transmitting new data on at least a second transmitter antenna, based on first desired transmission characteristics; and a second mode that retransmits the portion of data simultaneously on at least the first and second transmitter antennas, based on second desired transmission characteristics.

Abstract: A semiconductor integrated circuit pertaining to the present invention comprises a plurality of storage elements for storing and holding an input signal, a majority circuit that outputs a result of a majority decision of outputs from the plurality of storage elements; an error detector circuit that detects a mismatch among the outputs of the plurality of storage elements and outputs error signals; and a monitor circuit that monitors the error signals from the error detector circuit, wherein the monitor circuit, based on the error signals, orders a refresh action that rewrites data for rectification to a storage element in which an output mismatch occurs out of the plurality of storage elements and, if rewrite and rectification by the refresh action are unsuccessful, sends a notification to an external unit or process.

Abstract: A concatenated error correction device may be provided that includes: a first encoder which encodes a plurality of blocks arranged in a column direction and a row direction into a block-wise product code consisting of column codes and row codes by applying a first error correction code to the blocks in each of the column direction and the row direction; and a second encoder which receives K number of source symbols and applies a second error correction code to the source symbols, and then encodes into N number of symbols including N-K number of parity symbols. The N number of symbols form the plurality of blocks. K and N are natural numbers.

Abstract: An apparatus and method decode LDPC code. The apparatus includes a memory and a number of LDPC processing elements. The memory is configured to receive a LDPC codeword having a length equal to a lifting factor times a base LDPC code length, wherein the lifting factor is greater than one. The number of LDPC processing elements configured to decode the LDPC codeword, wherein each of the number of LDPC processing elements decode separate portions of the LDPC codeword.

Abstract: Systems and methods for correcting errors in a depth map generated by a structured light system are disclosed. In one aspect, a method includes receiving valid and invalid codewords, the valid spatial codewords included in a codebook. The method includes detecting the invalid codeword. The method includes retrieving a set of candidate valid codewords a lowest Hamming distance between the invalid codeword and the valid codewords in the codebook. The method includes estimating a median depth of neighboring locations of the invalid codeword. The method includes associating a depth with each candidate codeword and selecting the candidate with an associated depth closest to the depth estimate. The method includes assigning the depth associated with the selected candidate codeword to the location of the invalid codeword.

Abstract: An apparatus and method for encoding data are disclosed that may allow for different encoding levels of transmitted data. The apparatus may include an encoder unit and a plurality of transceiver units. The encoder unit may be configured to receive a plurality of data words, where each data word includes N data bits, wherein N is a positive integer greater than one, and encode a first data word of the plurality of data words. The encoded first data word may include M data bits, where M is a positive integer greater than N. Each transceiver unit may transmit a respective data bit of the encoded first data word. The encoder unit may be further configured to receive information indicative of a quality of transmission of the encoded first data word, and encode a second data word of the plurality of data words dependent upon the quality.

Abstract: A memory circuit is described comprising a plurality of memory elements, wherein each memory element is configured to store one data element of a plurality of data elements, an error correction information memory configured to store joint error correction information of the plurality of data elements, for each memory element, an error detection information memory storing error detection information for the data element stored in the memory element and a memory access circuit configured to, for an access to a memory element of the plurality of memory elements, check whether the error detection information for the data element stored in the memory element indicates an error of the data element stored in the memory element and, depending on whether the error detection information for the data element stored in the memory element indicates an error of the data element stored in the memory element, to process the error correction information for the access.

Abstract: Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize performance. The memory circuitry may be loaded with interleaved parity check bits in conjunction with the interleaved structure to provide multi-bit error detection capability. The parity check bits may be precomputed using design tools or computed during device configuration. In response to detection of a memory error, the error correction circuitry may be used to scan desired portions of the memory circuitry and to correct the memory error.

Abstract: According to one embodiment, a memory controller includes a decoder configured to perform approximate maximum likelihood decoding, the decoder including: an initial value generation unit configured to calculate first data on the basis of a received word read from a non-volatile memory; a storage unit configured to store the first data and a predetermined number of second data; an update unit configured to calculate new second data by using the predetermined number of second data stored and update the storage unit; an arithmetic unit configured to output an addition result of the first data and the latest second data as decoded word information; and a selection unit configured to select a decoded word with the maximum likelihood on the basis of a plurality of the decoded word information.

Abstract: Data bits are mapped to a lower number of slots than the number of slots available for a retransmission frame and control channels are transmitted in all available slots of the retransmission frame. The number of available slots in the retransmission frame is greater than the number of available slots in the original frame.

Abstract: A method begins by a processing module storing a set of encoded data slices in storage units. A data segment of data is encoded, in accordance with dispersed storage error encoding parameters, to produce the set of encoded data slices. The dispersed storage error encoding parameters include a decode threshold number and a pillar width number, which is at least twice the decode threshold number. The method continues with the processing module processing a first request for retrieval of the data segment by retrieving a first sub-set of encoded data slices, which includes the decode threshold number, and decoding them to produce a first recovered data segment. The method continues with the processing module processing a second request for retrieval of the data segment by retrieving a second sub-set of encoded data slices, which includes the decode threshold number, and decoding them to produce a second recovered data segment.

Abstract: The present disclosure presents a method and an apparatus for reducing cyclic redundancy check (CRC) false detections at a user equipment (UE). For example, the method may include receiving a data packet at the UE, determining whether a state metric value for each of a plurality of vector elements of a last path metric vector of the data packet is less than or equal to a first threshold, incrementing a counter when the state metric value of a vector element of the plurality of vector elements is less than or equal to the first threshold, determining whether the counter is lower than a second threshold, and providing the data packet to an upper layer protocol entity of the UE when a CRC pass for the data packet is determined and the counter is lower than the second threshold. As such, reduced CRC false detections at a UE may be achieved.

Abstract: The present invention concerns a wireless device and a method at a wireless device for transmitting a packet, said method comprising the steps of setting a lifetime value to a packet to transmit and, while the packet lifetime has not expired and the packet transmission fails: retransmitting the packet up to a retry limit, and suspending transmitting said packet during a pause time before transmitting the packet up to a retry limit.

Abstract: In one aspect, the present disclosure provides a storage device for accounting for transmission errors to improve a usable life span of memory blocks. In some embodiments, the storage device includes: a memory array including a plurality of memory blocks; and a memory controller in communication with the memory array via an interface, wherein the memory controller is configured to detect an error event associated with data from one of the plurality of memory blocks; determine an origin of the error event; increment an error count if the origin of the error event indicates a data error in the one of the plurality of memory blocks and not if the origin of the error event indicates a transmission error; compare the error count to a threshold value; and mark the one of the plurality of memory blocks as bad when the error count exceeds the threshold value.

Abstract: Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a Low Density Parity Check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a plurality of modulation symbols, wherein the modulator is configured to map bits included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of each of the modulation symbols.

Abstract: A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved.

Abstract: A digital broadcasting system is provided. The system includes an RS (Reed-Solomon) encoder configured to encode mobile service data for FEC (Forward Error Correction) to build RS frames including the mobile service data and a signaling information table, a signaling encoder configured to encode signaling information including fast information channel (FIC) data and transmission parameter channel (TPC) data, a group formatter configured to form data groups, wherein at least one of the data groups includes encoded mobile service data, known data sequences, the FIC data and the TPC data, and a transmission unit configured to transmit the broadcast signal including a parade of the data groups.

Abstract: A method is provided for generating a maximized linear correcting code from a base linear correcting code, the base correcting code and the maximized linear correcting code being associated with one and the same parity matrix H, the matrix being used to generate syndromes, the syndromes being used for decoding code words. The method comprises a step of identifying the syndromes unused for decoding the base linear correcting code, a step of identifying the errors that can affect the code words and make it possible to obtain the unused syndromes when a code word is multiplied by the matrix H and a step of selecting a unique error for each unused syndrome from among the identified errors, the error being called additional error.