Abstract: Digital communications systems employ Forward Error Correction (FEC) for robustness against fading, noise and interference. FEC is designed to support different code rates to meet different requirements. Different code rates may be achieved by performing puncturing or repetition operation. At the receiver the decoding may be performed on the baseline code rate to enable common decoder module. To enable this capability, the input to the decoder of the error correcting code must be initialized to zeros for the bit positions corresponding to bits that are not transmitted. For high throughput systems, it is not efficient to initialize particular bit positions to zero. A method and apparatus are disclosed for joint Rate Matching and deinterleaving that enable the decoder to begin the decoding operation on the received bits without explicitly initializing the punctured bit positions to zero.

Abstract: A method for communication includes encoding data using at least one Error Correction Code (ECC) to generate first and second output data streams. The first output data stream is processed to generate a first output signal, which has a first acquisition time. The second output data stream is processed to generate a second output signal, which has a second acquisition time that is smaller than the first acquisition time. The first and second output signals are transmitted simultaneously over a communication channel.

Abstract: A list decoding method for a polar code includes generating a tree-type decoding graph for input codeword symbols; the generating a tree-type decoding graph including, generating a decoding path list to which a decoding edge is added based on a reliability of a decoding path, the decoding path list being generated such that, among decoding paths generated based on the decoding edge, decoding paths within a threshold number of critical paths survive within the decoding path list in an order of high likelihood probability, and determining an estimation value, which corresponds to a decoding path having a maximum likelihood probability from among decoding paths of the decoding path list, as an information word.

Abstract: A method to decode low-density parity check (LDPC) encoded data using a parity check matrix having a plurality of layers, includes receiving a plurality of values at a decoder. Each value of the plurality of values represents one of a plurality of bits of an LDPC codeword encoded using the parity check matrix. The LDPC codeword is decoded using layered scheduling. A functional adjustment is applied to an approximation of belief propagation used during the decoding. At least one layer specific functional adjustment is used to provide an estimate of the codeword. An apparatus to decode low-density parity check (LDPC) encoded data using a parity check matrix having a plurality of layers includes a decoder. The decoder includes circuitry to decode, layer by layer, the LDPC encoded data utilizing functional adjustments and an algorithmic approximation to belief propagation to provide an estimate of the LDPC codeword.

Abstract: A method of sending the value of a status variable from a sending device to a receiving device as part of a standardized binary coded radio message. The message includes fields for predetermined information to be sent with the message as well as a buffer field. The method includes causing the sending device to assemble, calculate a checksum for, digitally store and periodically transmit a predetermined type of message in the form of a radio signal readable by a receiving device. The status variable is not related to the predetermined information. Before the checksum is calculated, the sending device inserts the value of the status variable in binary coded format into the message in a buffer field. According to a governing messaging standard, the buffer field is not intended to transmit information. The receiving device interprets the binary value as the value of the status variable.

Abstract: An apparatus and method for optimizing the performance of satellite communication system receivers by using the Soft-Input Soft-Output (SISO) BCJR (Bahl, Cocke, Jelinek and Raviv) algorithm to detect a transmitted information sequence is disclosed. A Sliding Window technique is used with a plurality of reduced state sequence estimation (RSSE) equalizers to execute the BCJR algorithm in parallel. A serial data stream is converted into a plurality of data blocks using a serial-to-parallel converter. After processing in parallel by the equalizers, the output blocks are converted back to a serial data stream by a parallel-to-serial converter. A path history is determined using maximum likelihood (ML) path history calculation.

Abstract: A communication device and associated method is provided. The communication device includes: a controller; a packet buffer, configured to store a current packet segment and a previous packet segment of an incoming packet; and a plurality of cyclic redundancy check (CRC) circuits, wherein each CRC circuit is individually fed with a portion of the current packet segment and/or a portion of the previous packet segment in a respective cycle of the incoming packet, and an initial value, wherein the plurality of CRC circuits are arranged in parallel.

Abstract: According to one embodiment, a memory device includes a first address memory storing a first address; a controller which is based on a first interface which transmits a signal serially and outputs a first command in accordance with the first interface; and a memory which stores data in a nonvolatile manner, is based on the first interface, and stores received write data in an address based on the first address when the memory receives the first command.

Abstract: The various implementations described herein include systems, methods and/or devices for modifying an error correction format of a respective memory portion of non-volatile memory in a storage device. In one aspect, the method includes, for respective memory portions of the non-volatile memory, obtaining a performance metric of the respective memory portion, and modifying a current error correction format in accordance with the measured performance metric, the current error correction format corresponding to a code rate, codeword structure, and error correction type. Furthermore, data is stored, and errors are detected and corrected, in the respective memory portion in accordance with the modified error correction format. The current and modified error correction formats are distinct, and comprise two of a sequence of predefined error correction formats, wherein a plurality of the sequence of predefined error correction formats have a same number of error correction bits and different numbers of data bits.

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that performs programming and reading out with respect to the non -volatile memory, a code processor that generates a code word by encoding; and a controller that sets a threshold -voltage read level for determining whether a value of each bit in a received word read out from the non-volatile memory is “0” or “1”. A difference between the number of bits which have value equals “0” and the number of bits which have value equals “1” in the code word depends on a code rate of the encoding. The controller obtains the threshold-voltage read level based on the code rate.

Abstract: A wireless device generates a High Efficiency Signal B (HE-SIG-B) field by Block Convolution Code (BCC) encoding and rate-matching a BCC block of the HE-SIG-B field, generates a Physical Layer Protocol Data Unit (PPDU) including the HE-SIG-B field, and transmits the PPDU. A total number N is a total number of bits of the HE-SIG-B field that precede the BCC block, and is greater than 0. The BCC block has a puncturing pattern depending on the total number N. A wireless device receives a PPDU. The PPDU includes an HE-SIG-B field that includes an encoded BCC block. The wireless device de-rate-matches the encoded BCC block having a puncturing pattern depending on a total number N. The total number N is a total number of decoded bits of the HE-SIG-B field that preceded the BCC block, and the total number N is greater than 0.

Abstract: A storage system for constructing RAID on the basis of flash memory comprises: one or more RAID processors and a plurality of flash memories. The RAID processor comprises a plurality of read-and-write processing units, a data block pointer unit, a data block counter and a parity check code buffer. One read and write processing unit can control one or more flash memory units. A method for constructing RAID in a storage system on the basis of flash memory can realize the function of RAID in a very small logic area and approximately negligible time and realize the unification of the function and performance of a storage system such as an enterprise-level SSD.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to perform a low-density parity check (LDPC) encoding on input bits using a parity check matrix to generate an LDPC codeword comprising information word bits and parity bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Abstract: A method includes receiving a plurality of streams of data from a plurality of data sources. During a first time interval of receiving the streams of data, the method further includes dividing each of the plurality of streams into a first time-aligned data segment to produce a set of first time-aligned data segments. The method further includes generating a first data matrix from data blocks of the set of first time-aligned data segments. The method further includes encoding the first data matrix using an encoding matrix to produce a first coded matrix. The method further includes slicing the first coded matrix into a first set of encoded data slices based on the first orientation. The method further includes outputting a first set of encoded data slices of the first coded matrix.

Abstract: A soft output detector is programmed with a first set of parameters. Soft information is generated according to the first set of parameters, including likelihood information that spans a maximum likelihood range. Error correction decoding is performed on the soft information generated according to the first set of parameters. In the event decoding is unsuccessful, the soft output detector is programmed with a second set of parameters, soft information according is generated to the second set of parameters (including likelihood information that is scaled down from the maximum likelihood range), and error correction decoding is performed on the soft information generated according to the second set of parameters.

Abstract: Aspects of the present disclosure are directed to circuits, apparatuses and methods for operating volatile memory circuits. According to an example embodiment, an apparatus includes a volatile memory circuit and a control circuit coupled to the volatile memory circuit. The control circuit is configured to generate and store parity data for data blocks written to the volatile memory circuit. The control circuit places the volatile memory circuit in a sleep mode in response to a first control signal. In response to a second control signal, the control circuit places the volatile memory into an active mode. In further response to the second control signal the control circuit detects and corrects errors in the data blocks stored in the volatile memory using the stored parity data.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Abstract: Embodiments include device, storage media, and methods for decoding a codeword of encoded data. In embodiments, a processor may be coupled with a decoder and configured to multiply the codeword and a parity-check matrix of the encoded data to produce a syndrome. If the syndrome is non-zero then the processor may identify a bit error in the codeword based at least in part on a comparison of the syndrome to one or more columns of the parity-check matrix. Other embodiments may be described and claimed.

Abstract: A method for delocalizing an error checking on a data in a pipelined processor from the data checked. A first check-data is generated at a first location on a first data. A second location receives the first data and the first check-data. A second check-data is generated on the first data and the first check-data is compared with the second check-data at the second location. A second data is generated from the first data and a third check-data is generated on the second data at the second location. A third check-data is generated on the second data at the second location and the second data is transferred to a third location. The third check-data is transferred to a fourth location. A fourth check-data is generated on the second data and is transferred to the fourth location. The fourth check-data and the third check-data are compared at the fourth location.

Abstract: A distributed storage system includes a plurality of storage devices and an information processing devices including a storage unit that is accessed more preferentially than the plurality of storage devices, and a processor. The processor deletes the data that can be restored from the storage unit when data that belongs to data stored in a first storage device and which can be restored is stored in the storage unit. The processor writes data that belongs to the data stored in the first storage device and which will not be restored to the storage unit. The processor switches the first storage device to the power-off state after writing the data. The processor reads the data that has been stored in the storage unit and which will not be restored when a request to read the data that will not be restored is given.