Abstract: A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

Abstract: Embodiments of the present disclosure include an apparatus. The apparatus includes a flash memory with a device threshold voltage for an on/off state, a sense circuit, a decoupling capacitor, and a bleeder circuit. The sense circuit is configured to sense a voltage level of a voltage supply line. The bleeder circuit is configured to bleed a remaining charge available on the decoupling capacitor. The sense circuit is configured to determine a state of the flash memory based on the voltage level of the voltage supply line. The bleeder circuit is configured to bleed the decoupling capacitor in an off state and to preserve the remaining charge available in an on state.

Abstract: Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline.

Abstract: A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.

Abstract: Techniques and mechanisms for changing a consistency with which a cell circuit (“cell”) settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCI) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCI stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.

Abstract: A method and system for measuring alternating-current system quantities through measurement connections producing frequency-dependent errors, in which method the analog signal of at least one measurement channel is sampled at a selected an approximately measured frequency fm at a multiple frequency fs, creating a base series depicting a period on each measurement channel, from each base series the fundamental frequency and the magnitude or phase-angle values or both of at least one harmonic frequency component are calculated with the aid of Fourier analysis or similar, each of which is corrected with the aid of a calibrated frequency-dependent function k(f), when the selected quantities are calculated from the calibrated values.

Abstract: A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a second state different than the first state, the method includes dynamically operating each column of a first subset of columns of the plurality of columns to access each bit cell of a corresponding row within the first subset of columns during the access operation, and maintaining each column of a second subset of columns of the plurality of columns in a static state during the access operation.

Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.

Abstract: A sense amplifier includes a first transistor having a source/drain connected to a data line, a drain/source connected to a first node and a gate connected to a setting line. The sense amplifier further includes a second transistor having a source/drain connected to ground or a power supply voltage, a drain/source connected to a second node and a gate connected to the setting line.

Abstract: A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N? well and an anti-fuse cell formed on the N? well. The anti-fuse cell includes a drain P+ diffusion deposited in the N? well, a source P+ diffusion deposited in the N? well, and an oxide layer deposited on the N? well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region.

Abstract: Disclosed is a device including a sinking circuit to sink current from an output node and a driver circuit coupled to the sinking circuit. The driver circuit includes complementary differential pairs to receive a voltage at the output node and generate a control signal according to the received voltage. The sinking circuit is configured to change the current from the output node according to the control signal.

Abstract: The present disclosure includes apparatuses and methods to change data category values. An example is a memory device that includes an array having a plurality of sequences of memory cells, where each of the respective sequences of memory cells includes a plurality of designated subsets of memory cells, and the array includes a counter corresponding to one of the plurality of designated subsets of memory cells. The memory device is configured to receive input corresponding to a data batch, where the input includes a designation that corresponds to the one of the plurality of designated subsets of memory cells to be conditionally updated, and to change a numerical value stored by the counter corresponding to the one of the plurality of designated subsets of memory cells.

Abstract: An information acquisition method includes: acquiring a specific piece of data using information for specifying a position of the specific piece of data in a document of a certain site by referring to a storage that stores therein information for specifying the position of the specific piece of data in the document of the certain site and information for specifying a position of another piece of data having a predetermined relation to the specific piece of data in the document, by a processor; and acquiring the other piece of data using the position of the other piece of data related to the specific piece of data in the document by referring to the storage, and acquiring data having the predetermined relation to the other piece of data using the acquired other piece of data, by the processor.

Abstract: A non-volatile memory device of the disclosure includes a memory cell, a writing circuit, and a current controller. The memory cell is disposed at an intersection of a first wiring and a second wiring, and includes a variable resistance element having a resistance state that is variable between a first resistance state and a second resistance state. The writing circuit varies the variable resistance element from the first resistance state to the second resistance state, and thereby performs writing of data on the memory cell. The current controller controls a current and thereby limits the current to a predetermined limit current value. The current is caused to flow through the first wiring or the second wiring by the writing circuit upon performing of the writing of the data.

Abstract: The present disclosure includes apparatuses and methods to determine timing of operations. An example method includes performing a first operation type that uses a shared resource in a memory device. The method includes applying a scheduling policy for timing of continued performance of the first operation type based upon receipt of a request to the memory device for performance of a second operation type that uses the shared resource.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for plate coupled sense amplifiers. An example embodiment may include a sense amplifier which may sense a voltage from a memory cell. The sense amplifier may also monitor a change in the voltage, and determine a logical value of the memory cell based on the time when the voltage reaches a trigger voltage. The memory cell may be coupled to a plate with a plate voltage, wherein a change in the plate voltage determines the change of the voltage from the memory cell.

Abstract: A computer system includes a main memory device and a processor. The main memory device includes a non-volatile memory and a memory controller to control the non-volatile memory. The processor is connected to the main memory device, executes an application program loaded to the non-volatile memory, and provides the memory controller with a command including context property information of an allocation region. The memory controller receives the command and controls the non-volatile memory based on the context property information.

Abstract: An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second. The technique reduces or eliminates the number of previously programmed cells from being adversely incrementally programmed by an adjacent cell being programmed to higher program levels, and reduces the magnitude of adverse incremental programming for most of the memory cells, which is caused by floating gate to floating gate coupling. The memory device includes an array of non-volatile memory cells and a controller configured to identify programming values associated with incoming data, and perform a programming operation in which the incoming data is programmed into at least some of the non-volatile memory cells in a timing order of descending value of the programming values.

Abstract: Embodiments of the present disclosure include an apparatus. The apparatus includes a voltage supply line, a sense circuit coupled to the voltage supply line, and a bleeder circuit. The sense circuit is configured to sense a voltage level of the voltage supply line. The bleeder circuit is configured to bleed a remaining charge available on a capacitor when the voltage level reaches a device threshold voltage. The device threshold voltage arises from a device connected to the apparatus.

Abstract: Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline.