Abstract: A memory device includes a command interface configured to receive a write command and internal write adjust (IWA) circuitry. The IWA circuitry is configured to receive the write command from the command interface, generate an internal write signal (IWS) based upon the received write command and train a data strobe (DQS) signal to generate a DQS signal having a set amount of phase alignment with a clock (CLK) of the memory device to capture a data signal (DQ) using the IWS.

Abstract: A data write device for a resistive memory element, the resistive memory element including: a conductive electrode provided at one end of the memory element; and a reading electrode provided at the other end of the memory element being configured to vary a resistance of the memory element by applying a write current to the conductive electrode, the data write device for the resistive memory element further includes: a writing means, an output means, and a control means. The output means is provided between a power supply and the reading electrode. As output signals, a read signal from the memory element and a monitor signal to monitor a writing status of the memory element written by the writing means are output from the output means. By the monitor signal, a termination of data-writing into the resistive memory element is detected.

Abstract: The present technology includes a memory device and a method of operating the same. The memory device in which an interface circuit and a semiconductor memory are packaged together includes a centrally located region in a ball mapping region of a memory device in which data input/output pins for an operation of the interface circuit and the semiconductor memory are disposed, and a test pin region in which test pins for a test operation of the interface circuit are disposed.

Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.

Abstract: A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.

Abstract: Systems, devices, and methods related to non-volatile memory are described. A non-volatile memory array may be employed as a main memory array for a system on a chip (SoC) or processor. A controller may interface between the non-volatile memory array and the SoC or processor using a protocol agnostic to characteristics of non-volatile memory operation including different page sizes or access time requirements, etc. A virtual memory bank at the controller may be employed to facilitate operations between the SoC or processor and the non-volatile memory array. The controller may be coupled with a buffer to facilitate rapid data operation, and the controller may be configured to selectively access data at the non-volatile array to account for data stored in the virtual memory bank or the buffer. The controller, the virtual memory bank, and the buffer may be configured on one chip separate from the SoC or processor.

Abstract: A selection circuit includes: a first selection device coupled between a write IO line and a first node; a second selection device coupled between a read IO line and a second node; a third selection device controllable by a first address decode signal, and coupled between a first bit line and a third node; a fourth selection device controllable by a second address decode signal, and coupled between a second bit line and the third node; a first suppression device controllable by a write enable signal, and coupled between the second node and ground; a second suppression device controllable by a read enable signal, and coupled between the first node and ground; a first isolation device controllable by the write enable signal, and coupled between the first and third nodes; and a second isolation device controllable by the read enable signal, and coupled between the second and third nodes.

Abstract: Various implementations described herein are related to a device having an array of bitcells that are accessible via wordlines and bitlines including unselected bitlines and a selected bitline. Each bitcell in the array of bitcells may be selectable via a selected wordline of the wordlines and the selected bitline of the bitlines. The device may include precharge circuitry that is configured to selectively precharge the unselected bitlines and the selected bitline before arrival of a wordline signal on the selected wordline.

Abstract: A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

Abstract: A memory system includes: a memory device including a three dimensional (3D) cell array, in which memory cells having the same height are coupled to a component word line by units of rows and component word lines having the same height are coupled to a group word line; and a controller suitable for controlling the memory device to perform a program operation with a program data into memory cells coupled to a data component word line selected from a plurality of component word line included in a single group word line and to perform a dummy program operation with dummy data into memory cells coupled to remaining dummy component word lines among the plurality of component word lines.

Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.

Abstract: An anti-fuse device includes an anti-fuse array and a biasing circuit. The anti-fuse array includes an anti-fuse cell that has a gate node, a gate oxide layer and a source-drain node. The biasing circuit is coupled to the anti-fuse array and is configured to bias the gate node of the anti-fuse cell with a first bias voltage during a program operation, and bias the source-drain node of the anti-fuse with a second bias voltage during the program operation. A voltage level of the first bias voltage is lower than a voltage level of the second bias voltage, and a voltage difference between the first bias voltage and the second bias voltage is higher than a gate oxide breakdown voltage of the gate oxide layer.

Abstract: A memory device includes a plurality of memory blocks and each memory block includes a plurality of columns of memory cells. Each column of memory cells is coupled to a corresponding bit line. Upon completion of a power-up sequence, detect if a current leakage of corresponding columns in a group of memory blocks is greater than a predetermined level. If the current leakage of the corresponding columns in the group of memory blocks is greater than the predetermined level, perform an over-erasure correction on the corresponding columns.

Abstract: According to one embodiment, a semiconductor memory device comprising: a first memory layer including a plurality of memory units electrically coupled to one another; a first memory area including a first memory unit for data writing of the memory units; a second memory area including a second memory unit for data reading of the memory units; and a controller configured to write data in the first memory unit, shift the data written in the first memory unit to the second memory unit, and read data written in the second memory unit.

Abstract: An integrated circuit and a computing method thereof are provided. The integrated circuit includes a memory array, word lines, bit lines and a page buffer. The memory array includes memory cells, each configured to be programmed with a weight. The word lines respectively connect a row of the memory cells. The bit lines are respectively connected with a column of the memory cells that are connected in series. More than one of the bit lines in a block of the memory array or more than one of the word lines in multiple blocks of the memory array are configured to receive input voltages. The memory cells receiving the input voltages are configured to multiply the weights stored therein and the received input voltages. The page buffer is coupled to the memory array, and configured to sense products of the weights and the input voltages.

Abstract: A memory cell arrangement is provided that may include: a read-out circuit and a memory cell including: a first terminal, a second terminal, and a third terminal; the memory cell may be configured to control current flow between the second terminal and the first terminal as a function of a first voltage present at the first terminal, a third voltage applied at the third terminal, and a memory state of the memory cell. The read-out circuit is configured to: generate a characteristic voltage at the bitline by applying the third voltage at the third terminal and a second voltage at the second terminal, the characteristic voltage representing the memory state of the memory cell, and to determine the memory state of the memory cell based on sensing the characteristic voltage.

Abstract: According to one embodiment, a memory device includes: a first and a second interconnects; a memory cell including a variable resistive element, the memory cell between the first and second interconnects; and a write circuit including a current source circuit and a voltage source circuit, the write circuit writing data to the memory cell by using a write pulse. The write circuit supplies the write pulse to the memory cell by using the current source circuit in a first period from a first time of a start of supply of the write pulse to a second time, and supplies the write pulse to the memory cell by using the voltage source circuit in a second period from a third time to a fourth time of an end of the supply of the write pulse.

Abstract: Methods, systems, and devices for phase clock correction are described. The clock correction may, in some examples, include two stages of duty cycle adjustment. In a first stage, the duty cycles of multiple clock signals may be adjusted. These clock signals may be based on an input clock signal and its complement. The duty cycle adjustment provided to a clock signal during this stage may be based on a difference between the duty cycle of the clock signal before adjustment and the duty cycle of another clock signal. In the second stage, the duty cycle of the input clock signal and its complement may be adjusted. The duty cycle adjustment provided to the input clock signal and/or its complement may be based on clock signals generated from the multiple clock signals after their duty cycles have been adjusted.

Abstract: Apparatuses and methods for compensation of sense amplifiers, for example, threshold voltage compensation, are disclosed. Prime memory sense amplifiers used for accessing prime memory and redundant memory sense amplifiers used for accessing redundant memory are concurrently compensated while determining whether a memory address is remapped from prime memory to redundant memory. Following the determination, sense amplifiers (e.g., prime memory sense amplifiers and/or redundant memory sense amplifiers) that are not used for accessing the memory corresponding to the memory address are precharged.

Abstract: A controller controlling a memory device includes an elapsed time calculator suitable for receiving an absolute time from a host whenever a state is changed between an active state and an inactive state, calculating an average hibernation elapsed time for elapsed times between first and second absolute times, and calculating a system time based on a third absolute time and the average hibernation elapsed time, and a flash translation layer suitable for controlling a program operation for the memory device in response to a program command for a memory region, calculating a program operation time for the memory region based on the system time, and controlling a read operation for the memory device using a read voltage, which is determined based on an elapsed time since the program operation time, in response to a read command for the memory region.