Abstract: The inventive mechanism has a run-time optimization system (RTOS) embedded in hardware. When the code is first moved into Icache, a threshold value is set into a counter associated with the instruction or instruction bundle of the particular cache line of the Icache. Each time the instruction or instruction bundle is executed and retired, the counter is decremented by one. When the counter reaches zero, a trap is generated to inform that the code is hot. A trace selector will form a trace starting from the hot instruction (or instruction bundle) from the Icache line. The Icache maintains branch history information for the instructions in each cache line which is used to determine whether a branch should be predicted as taken or fall through. After the trace is formed, it is optimized and stored into a trace memory portion of the physical memory. The mapping between the original code of the trace and the optimized trace in the trace memory is maintained in a mapping table.

Abstract: A system and method for detecting and locating improper or illicit use of digitized information such as illegal pirating, copying, alteration, and the like. The digitized information may include software, digital music, digital movies, multimedia or the like that may be placed on a user's computer and possibly copied to other computers. The system or method preferably operates in the background so as to be unnoticeable to the user and preferably does not interfere with operation of the digitized information even if determined that copying or alteration has occurred. Thus, there is little motivation to remove the routine that effects transmission over the Internet to a server of information such as a program identification indicia, a computer identification indicia, program alteration identification.

Abstract: To provide an improved approach to traffic data evaluation in a network using dynamic routing there is provided a traffic data evaluation apparatus for a network using dynamic routing comprising traffic data collection means (12) to collect data with respect to a real traffic flow in the network. Further, the traffic data evaluation apparatus comprises a network modelling unit (14, 16) to model the network through a virtual network having virtual links without capacity restrictions imposed thereon. Still further, there is provided a network load evaluation means (18) to map the real traffic flow onto the virtual network assuming optimal routing and to compare the capacity used for each virtual link with the capacity assigned thereto. Thus, it is possible to draw conclusions on the network load by real network measurements also for a network using a dynamic routing protocol.

Abstract: A computer system utilizing a processing system capable of efficiently comparing register identifiers to detect data hazards between instructions of a computer program is used to execute the computer program. The processing system utilizes at least one pipeline, a first decoder, a second decoder, and comparison logic. The pipeline receives and simultaneously processes instructions of a computer program. The first and second decoders are coupled to the pipeline and decode register identifiers associated with instructions being processed by the pipeline. The comparison logic is interfaced with the first and second decoders and respectively compares the decoded register identifiers produced by the first and second decoders to other decoded register identifiers.

Abstract: A system for managing an assemblage of entities. The entities interface within the assemblage for control of primary information handling functions and further interface with the system to permit the carrying out of management functions. The system includes management modules adapted to carry out management functions by independently interpreting and executing commands and a kernel including a table of dispatch pointers for directing the commands to the respective modules in which they are to be interpreted and executed. In addition, the system includes storage containing domain information defining groups of entities, where the kernel may issue a command to a group by issuing individual commands to appropriate modules.

Abstract: In a multifunctional apparatus used by a plurality of users, image data entered in a variety of formats from various information sources such as a scanner, computer, facsimile machine and electronic mail is stored on a memory medium such as a hard disk in correspondence with user IDs. By operating the multifunctional apparatus storing this image data to enter a user ID, a list of image data stored in correspondence with the user ID is displayed together with information relating to the image data. Desired image data is selected from the list and is subjected to processing such as printing or deletion. Image data for which a password has been set can be processed by entering the correct password. By virtue of the processing described, handling of the entered image data is facilitated and protection of confidentiality is made possible.

Abstract: A procedure for operating a server (SERV) that supplies subscribers with data streams of different contents (CONT1 to CONT3), as well as a server and a control unit for executing the procedure. The contents (CONT1 to CONT3) are each stored in a memory unit or in several memory units of the server, and in order to supply a subscriber (SUB1 to SUB8) with a data stream of a particular content, the particular content is read out from the memory unit or from one of the memory units in which the content is stored, and sent to the subscriber as a data stream. A Busy list is set up for each of the contents (CONT1 to CONT3) stored in the memory units (DSD1 to DSD5) of the server (SERV). Each memory unit (DSD1 to DSD4) in which a content is stored, is allocated to the Busy list of the content stored in it. Each memory unit (DSD5) that is not at that time needed for supplying a subscriber, is allocated to a Free list.

Abstract: An apparatus is described that comprises a data processing unit and at least one coprocessor. The data processing unit comprises a register file having registers, a memory, a plurality of execution units, a coprocessor interface for coupling the at least one coprocessor with the data processing unit, and a pipeline configuration for processing instructions having a fetch stage for fetching an instruction from the memory, a decode stage for decoding an operational code from the instruction, an execution stage for activating one of the execution units, and a write-back stage for God writing back from the execution unit. The data processing unit comprises read-and write-lines coupling the register file with the coprocessor for exchanging operands, at least one control line indicating that the coprocessor is busy, and a plurality of control lines from the decode stage for controlling the coprocessor which are operated upon detection of a coprocessor instruction.

Abstract: A network link tester couples to a LAN port with the LAN port having both a network transmit pair and a node transmit pair line. The link detector scans the network transmit pair and node transmit pair lines for the presence of link signals. Upon finding a link signal, the link tester indicates if the link signals were on the network transmit pair or on the node transmit pair line. Further, the link tester determines the network standard used and identifies the available operational nodes. The process of using a LAN tester includes coupling the tester to the LAN port, scanning network lines for the presence of link signals and determining and displaying operational capabilities. Optionally, the link tester may generate a tone signal on the network lines to assist in identifying line faults. Further, the link tester may generate link signals responsive to receive link signals.

Abstract: The inventive mechanism uses a cache table to map branch targets. When a fetch instruction is initiated, the inventive mechanism searches the IP-to-TM cache to determine whether the branch target instruction has been optimized and placed into the trace memory. If there is a match with the P-to-TM cache, then the code in the trace is executed. This cache is examined in parallel with Instruction Translation Lookup Buffer (ITLB). If not a match is found in the IP-to-TM cache, the original binary in the physical address provided by the ITLB will be executed.

Abstract: The inventive mechanism provides fast profiling and effective trace selection. The inventive mechanism partitions the work between hardware and software. The hardware automatically detects which code is executed very frequently, e.g. which code is hot code. The hardware also maintains the branch history information. When the hardware determines that a section or block of code is hot code, the hardware sends a signal to the software. The software then forms the trace from the hot code, and uses the branch history information in making branch predictions.

Abstract: A system for instructing a data processor, the system including an instruction root having an operation selection field for selecting an operation to be performed by said data processor and an instruction prefix. The instruction prefix has a field selected from the group of a conditional execution field for selecting a condition under which a data processor will perform said selected operation, an operand length modification field for modifying the selected operation so as to be performed on an operand having a different length, an instruction group field for selecting a length of an instruction group that includes the instruction root, and a prefix length selection field for selecting a length of said instruction prefix. A data processor system responsive to this instruction system is also disclosed. An instruction system for statically grouping instructions without using an instruction prefix is also disclosed.

Abstract: A method of dynamically adjusting a multiple stage pipeline to execute one of a set of instructions, wherein each stage has a latency and performs a selected data operation. An instruction to be executed is received and a number of stages of the pipeline is selected to execute the instruction as needed to perform a corresponding data operation. Unnecessary stages are bypassed to a reduced latency and the instruction is executed with the selected stages.

Abstract: A data streaming transmission method and system is disclosed having a network server connected to client device through a communication network with one or more of caching servers. The network server has a data streaming application and a memory for storing data. A series of connections, each using a data streaming arrangement, is formed in the path between the source network and client device by the caching servers. Each caching server can absorb network congestion in its downstream connection by utilizing an expandable buffer for storing additional segments of the streamed data and varying the transmission data rate in the down stream connection.

Abstract: The invention handles message publishing between entities whether they are in the same process, or they are different processes. The invention includes one message broker for each process, which is internal to the process, and which will handle the distribution of events within the process. The invention uses a bus to facilitate distribution messages external to the process. A third party broker distributes the messages between processes. Thus, an object that is internal to the process may subscribe to an event type via the message broker. Likewise, an object can subscribe to an event from an external source. Thus, when an exported event is published via the message broker, the bus will export the message to the third party broker. This event will then be distributed to subscribing processes by the broker. When an event comes into a process via the bus, it is republished using the internal message broker to the interested objects of the process.

Abstract: A technique for managing register assignments. The technique involves maintaining, in a register list memory circuit having entries that respectively correspond to physical registers, a list of register assignments that assign logical registers to the physical registers. The technique further involves maintaining, in a vector memory circuit having bits that respectively correspond to the physical registers, a valid vector that forms, in combination with the list of register assignments, a list of valid register assignments. Furthermore, the technique involves storing, for an instruction that is mapped by the data processor, a copy of the valid vector from the vector memory circuit to a silo memory circuit. Preferably, the processor using the technique has the ability to execute branches of instructions speculatively, and to recover if it is determined that the processor executed down an incorrect instruction branch.

Abstract: A power recycle circuit is for use in a power management system. An input of the power recycle circuit is for receiving a clock signal. A detection circuit is for sensing a minimum disable pulse when a clock signal is received and when a clock signal is not received. A power recycle circuit is for generating a power recycle signal in response to the minimum disable pulse. A state machine is for holding the power recycle signal for at least two clock cycles.

Abstract: The present invention comprises a LSU which executes instructions relating to load/store. The LSU includes a DCACHE which temporarily stores data read from and written to the external memory, an SPRAM used to specific purposes other than cache, and an address generator generating virtual addresses for access to the DCACHE and the SPRAM. Because the SPRAM can load and store data by a pipeline of the LSU and exchanges data with an external memory through a DMA transfer, the present invention is especially available to high-speedily process a large amount of data such as the image data. Because the LSU can access the SPRAM with the same latency as that of the DCACHE, after data being stored in the external memory is transferred to the SPRAM, the processor can access the SPRAM in order to perform data process, and it is possible to process a large amount of data with shorter time than time necessary to directly access an external memory.

Abstract: A data processing system and method are described for permitting a server computer system to remotely access asset information stored within one of a plurality of client computer systems. The client computer systems are coupled to the server computer system utilizing a network. Asset information is stored in a storage device within the particular client computer system. The asset information includes information identifying a plurality of components of the client computer system. The server computer system transmits a message to the client computer system while the client computer system is powered-off. A network adapter is included within the client computer system. The network adapter accesses the storage device to obtain the asset information while the client computer system is powered-off.

Abstract: A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated whenever one or more instructions are dispatched. A microprocessor employing the reorder buffer is also configured with fixed, symmetrical issue positions. The symmetrical nature of the issue positions may increase the average number of instructions to be concurrently dispatched and executed by the microprocessor. The average number of unused locations within the line decreases as the average number of concurrently dispatched instructions increases. One particular implementation of the reorder buffer includes a future file. The future file comprises a storage location corresponding to each register within the microprocessor.