Abstract: The present invention switches a source of a streaming session between a primary server and its client, from the primary server to another server at arbitrary points during the progress of the streaming session. The switching of the source is accomplished through the use of a virtual socket capable of simultaneously phasing in a new streaming connection while phasing out an old streaming connection during a streaming session that preserves the temporal progress of the session. The virtual socket acts as a client-based intermediary between the client and one or more streaming servers, thus enabling a client application to establish a streaming connection with respect to content and not to the end-party, i.e., server.

Abstract: An electronic system is provided that includes a plurality of power consuming electronic circuits and a power management system that interfaces a power supply to the plurality of power consuming electronic circuits. The power management system includes a power level detect circuit that includes a voltage level detector circuit that receives an analog voltage level signal indicative of a level of voltage provided from the power supply. The power level detect circuitry also includes digital encoding circuitry that encodes the analog voltage level signal as a digital powered level signal also indicative of the level of the power supply voltage. Each of the power consuming electronic circuit includes configuration circuitry to receive the digital power level signal and to configure operation of that particular power consuming electronic circuit responsive to the digital power level signal.

Abstract: The present invention relates to a method and an arrangement for communicating packet information in a digital telecommunications system. Through the invention is selected a set of designated communication resources (ch1-chn) from an available amount of resources. Every packet (P) is forward error correction encoded into an encoded packet (Pci), via one of at least two different coding schemes (ci), prior to being transmitted to a receiving party, over the designated communication resources (ch1-chn). An estimated transmission time is calculated for all combinations of coding scheme (ci) and relevant distribution (dj) of the encoded data blocks (B1-B&Ggr;), in the encoded packet (Pci) over the set of designated communication resources (ch1-chn), and the combination (ci,dj) is selected, which minimises the estimated transmission time.

Abstract: An indirect VLIW (iVLIW) architecture is described which contains a minimum of two instruction memories. The first instruction memory (SIM) contains short-instruction-words (SIWs) of a fixed length. The second instruction memory (VIM), contains very-long-instruction-words (VLIWs) which allow execution of multiple instructions in parallel. Each SIW may be fetched and executed as an independent instruction by one of the available execution units. A special class of SIW is used to reference the VIM indirectly to either execute or load a specified VLIW instruction (called an “XV” instruction for “eXecute VLIW”, or LV for “Load VLIW”). In these cases, the SIW instruction specifies how the location of the VLIW is to be accessed. Other aspects of this approach relate to the application of data memory addressing techniques for execution or loading of VLIWs that parallel the addressing modes used for data memory accesses.

Abstract: A high performance network interface receives network traffic in the form of packets. The network interface parses one or more headers of a received packet in order to determine whether the packet has been formatted with a pre-selected protocol. If so, one or more efficient enhancements in the processing of a packet may be enabled for the packet. During parsing, header data that may be useful in the processing enhancements may be saved. A packet conforming to one or more of a set of pre-selected protocols may be more completely parsed than a packet not conforming to any of the pre-selected protocols. Instructions for parsing a packet to determine a protocol and to extract useful data are stored in a writeable random-access memory. The instructions may be replaced, modified or supplemented depending upon the composition of network traffic and the protocols selected for enhanced processing.

Abstract: The present invention provides an apparatus and method for transmitting serial data bits in a computer system having both an IEEE 1394 bus and a universal serial bus. The arrangement comprises a networked entertainment system comprising a host computer system and a remote peripheral consumer electronics device. The host system includes a processor, a bus, a memory, and a graphics card. A host interface circuit is coupled to the host system to provide an interface with a remote peripheral device. A remote interface circuit is coupled to the remote peripheral device to provide an interface with the host system. The host interface circuit and the remote interface circuit are connected to each other by an IEEE 1394 bus cable. The host interface circuit provides a USB port for connecting a USB device to the host system. The remote interface circuit provides USB ports for connecting USB devices.

Abstract: In a load/store unit within a microprocessor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. When a load instruction is issued for execution, a determination is made whether the load instruction is attempting to load data to a memory location that is the same as a previously executed store instruction is waiting to complete. If so, then the data waiting to be stored within the cache by the store instruction is directly forwarded to the load instruction.

Abstract: A system and method for sending and receiving data with a reliable communication protocol. The system includes a computer at a node having a backplane, a CPU board plugged into the backplane, software instructions for the CPU, and a special network board plugged into the backplane. The CPU board, software, and network card act to implement the TCP/IP protocol suite. The network card or board includes an interface to receive data packets from the physical layer, and circuitry to verify the TCP checksum before de-encapsulation and routing of the TCP segment by the network layer software. It also includes circuitry to automatically prepare the acknowledgement signal to be sent by the receiving computer to the sending computer. It additionally includes circuitry to calculate the error detecting code on outgoing signals from the sending computer to the receiving computer.

Abstract: A method of downloading resources to a client (1) from a content server (3) over a data network. A resource request message is sent from the client (1) and is intercepted at a proxy (2) located in the data network between the client (1) and the content server (3). A header request is sent from the proxy (2) to the content server (3), requesting the content server (3) to transmit a header, associated with the requested resource, to the proxy (2). The header is received at the proxy (2) which determines whether or not the header contains billing and/or access restrictions. In the event that the header does contain billing and/or access restrictions, the client's right to receive the requested resource is authenticated and, providing the client is authenticated, the resource request message is delivered from the proxy (2) to the content server (3) and subsequently the resource is downloaded from the content server (3) to the client (1).

Abstract: A data broadcasting station transmits a multiplexed signal in which multimedia data encoded in a prescribed coding system are at least multiplexed in a broadcasting form. A file manager stores the multimedia data received by a tuner and decoded by a decoder in a storage device while creating management information therefor and registering it in a table. A browser requests of the file manager multimedia data to be referred to, and lets it be displayed on a monitor. The file manager increments/decrements a retention coefficient on the basis of a frequency of reference to the multimedia, and determines whether or not to delete each multimedia data stored in the storage device. Thus provided is a terminal device which can effectively utilize the capacity of the storage device without deleting multimedia data frequently referred to by the user.

Abstract: An intermediate system authenticates using cryptography. The authentication routine requires a user to supply a secret known only to the user before allowing data to be transmitted. The secret is never transmitted. The invention may be incorporated into an intermediate system, into intermediate system software, or into application specific integrated circuits designed for use in an intermediate system. The invention may include components that interact specifically with installed components in an end system or elsewhere in a network.

Abstract: An instruction queue is physically divided into two (or more) instruction queues. Each instruction queue is configured to store a dependency vector for each instruction operation stored in that instruction queue. The dependency vector is evaluated to determine if the corresponding instruction operation may be scheduled for execution. Instruction scheduling logic in each physical queue may schedule instruction operations based on the instruction operations stored in that physical queue independent of the scheduling logic in other queues. The instruction queues evaluate the dependency vector in portions, during different phases of the clock. During a first phase, a first instruction queue evaluates a first portion of the dependency vectors and generates a set of intermediate scheduling request signals. During a second phase, the first instruction queue evaluates a second portion of the dependency vector and the intermediate scheduling request signal to generate a scheduling request signal.

Abstract: A one-chip microcomputer including a Reduced Instruction Set Computer (RISC) type processor and one or more coprocessors for performing processes independent from said RISC type processor. The RISC type processor is coupled to the coprocessors via a coprocessor bus and is provided with a bypass circuit which facilitates execution of conditional branch instructions.

Abstract: Apparatus selects a state machine bit group from a plurality of state machine bit groups of a digital system for debugging the state machine connected to the selected bit group. The apparatus is adapted to output the bits of the selected bit group using existing output pins of the digital system, and includes a first multiplexer which is adapted to be connected to the plurality of state machine bit groups for outputting the selected state machine bit group. A second multiplexer is adapted to be connected to system signals and the selected state machine bit group from the first multiplexer, and outputs one of the system signals and the selected state machine bit group via the output pins of the system. A control circuit supplies a first select signal to the first multiplexer for selecting the selected state machine bit group output by the first multiplexer, and supplies a second select signal to the second multiplexer for selecting one of the selected bit group and the system signals.

Abstract: A reorder buffer is provided which stores a last in buffer (LIB) indication corresponding to each instruction. The last in buffer indication indicates whether or not the corresponding instruction is last, in program order, of the instructions within the buffer to update the storage location defined as the destination of that instruction. The LIB indication is included in the dependency checking comparisons. A dependency is indicated for a given source operand and a destination operand within the reorder buffer if the operand specifiers match and the corresponding LIB indication indicates that the instruction corresponding to the destination operand is last to update the corresponding storage location. At most one of the dependency comparisons for a given source operand can indicate dependency. According to one embodiment, the reorder buffer employs a line-oriented configuration.

Abstract: A system and method for transferring digital computer software and data from one digital computer to one or more digital computers through a network of electrical connections between the two or more digital computers. An installation agent is established at each target machine and software to be transferred is placed within a software package, wherein the software package includes the software and installation commands for installing the software. The software package is transferred to each target machine and installed by alerting the installation agent that a software package has arrived and executing commands within the installation agent to send an install message to the software package, wherein the install message causes the software package to execute the installation commands.

Abstract: In a multiprocessing computer system, a cache-coherent data transfer scheme that also conserves the system memory bandwidth during a memory read operation is described. A source processing node sends a read command to a target processing node to read data from a designated memory location in a system memory associated with the target processing node. In response to the read command, the target processing node transmits a probe command to all the remaining processing nodes in the computer system regardless of whether one or more of the remaining nodes have a copy of the data cached in their respective cache memories. Probe command causes each node to maintain cache coherency by appropriately changing the state of the cache block containing the requested data and sending respective probe responses to the source node. Probe command also causes the node having an updated copy of the cache block to send the cache block to the source node through a read response.

Abstract: An intelligent method, apparatus and computer program product are provided for automated refreshing of internet web pages. Page data are stored including a record of page data values for each user selected internet web page. The page data values include at least one refresh interval, a last time refreshed and a last time accessed. A user request for refreshing an internet web page is received and the internet web page is refreshed. Utilizing the refreshed internet web page, checking for changes in the refreshed internet web page is performed. Then scanning the stored page data is performed and for each user selected internet web page, the stored refresh interval is compared with a current refresh time interval. For each user selected internet web page, responsive to the current refresh time interval being greater than the stored refresh time interval, the internet web page is refreshed.

Abstract: A method and system are disclosed for managing Internet presentation materials in a single file format for ease of administration while presenting to an Internet requestor only those portions of the file requested, for maximum performance. Also disclosed is a system and method for presenting Internet materials using borderless presentation areas, where the background specification is decoupled from the presentation area specification. The invention also relates to a system and method for using a dynamic web page builder to generate and manage multiple instances of information to be simultaneously displayed in multiple presentation areas, in which one of the presentation areas contains table of contents information listing various selectable web pages stored in a single file. The table of contents information is continuously displayed on-screen when any of the items listed in the table of contents is selected for ease of navigation through a web site.

Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.