Abstract: A method of initializing node addresses for use in an electronic switching system comprises the steps of: (a) storing all possible sets of node addresses, each set corresponding to an inter-processor communications configuration, and pointers in a residue of a memory; (b) receiving information on a designated set of node addresses which corresponds to a selected inter-processor communications configuration to be used; (c) locating a pointer corresponding to the designated set of node addresses; and (d) writing each address in the designated set of node addresses onto each corresponding register.

Abstract: A system within a multisystem environment is selected to run a real-time application. The selection process looks for a system in which the amount of a processor resource for delivering a real-time data stream of the real-time application has the least impact on other work proseccing on the selected system. The real-time application is allocated an amount of a processor resource that does not exceed a limit chosen for a group of one or more real-time applications. A selected amount of the processor resource remains available for at least one non-real-time application of the multisystem environment.

Abstract: A processor reduces or avoids a degradation of computing performance in a computer system using a RISC-based CISC processor by selectively bypassing a CISC-to-RISC translator or decoder and supplying native RISC codes directly to the RISC core. The processor that executes CISC-type instructions on a RISC core includes a native mode Op supply circuit for supplying RISC Ops directly from an instruction memory to a RISC execution engine.

Abstract: A microprocessor includes a control register having a predetermined bit which is unconditionally writable to either a first state or a second state. Additional bits of the control register are writable to either the first or second state when the predetermined bit has the first state. Each additional bit is not writable when the predetermined bit has the second state. The microprocessor further includes at least one circuit controlled by the state of a corresponding one of the additional bits of the control register. The writability of the additional bits is preferably further conditioned upon the state of a machine status register, which is unconditionally writable to either the first state or the second state. A primary AND gate and a secondary AND gate corresponding to each additional bit control the writability of the additional bits.

Abstract: Arbitration apparatus is described for arbitrating between a number of jobs, for example for distributing message traffic over a data transmission network. The arbitration apparatus comprises an activity register containing a number of activity bits indicating which of a number of transmission jobs is currently active. The apparatus also includes a two-tier token ring arrangement comprising an outer ring and a number of inner rings. Each ring consists of a number of registers, holding a token which is passed cyclically around the ring. Each register has a bypass path which bypasses the register if a corresponding job or group of jobs is inactive. The positions of the tokens in the rings determines which job is to be scheduled next. Each ring also includes a keeper register for preserving the token if all the jobs are inactive.

Abstract: A buffer monitor includes a first counter for counting bits of incoming data as they arrive at a data buffer that stores and then forwards the incoming data. Each bit of outgoing data resets the first counter's count. If its count reaches a first limit before being reset by an outgoing data bit, the first counter asserts an alarm. The buffer monitor also includes a second counter for counting bits of outgoing data as they depart the buffer. Each bit of incoming data resets the second counter's count. If its count reaches a second limit level before being reset by an incoming data bit, the second counter asserts an alarm. The first counter will sound an alarm when the buffer fails to forward output data after having received a substantial amount of input data. The second counter will assert an alarm when the buffer has forwarded a substantial amount of output data without having received any input data.

Abstract: A distributed interrupt controller system for use in a multiprocessor environment, having at least two local programmable interrupt controllers (LOPICs) coupled to at least one central programmable interrupt controller (COPIC) via a dedicated bus. One of the at least one COPICs functions as a master arbiter, while the LOPICs, each of which may be integrated with its corresponding processing unit, and other non-master COPICs are treated as bus agents. Bus grant is achieved by a "round robin" arbitration protocol. For distributed delivery of interrupts, the master arbiter compares a current-task-priority-register value associated with each bus agent to determine the agent that is least busy for delivery of the interrupt thereto.

Abstract: A data driven information processor includes an input control portion for producing a first data packet including common identification information and a plurality of pieces of data, a junction portion for controlling input of the first data packet and a second data packet, a firing control portion for detecting data to be paired with data in the selected data packet and outputting paired data, an operation processing portion for operating the paired data, a program storage portion for producing and outputting a second data packet based on a result of operation, and a branching portion for controlling whether to output the second data packet to the junction portion or to another data driven information processor. A plurality of such data driven information processors are connected for parallel processing.

Abstract: Scheduler logic which tracks the relative age of stores with respect to a particular load (and of loads with respect to a particular store) allows a load-store execution controller constructed in accordance with the present invention to hold younger stores until the completion of older loads (and to hold younger loads until completion of older stores). Address matching logic allows a load-store execution controller constructed in accordance with the present invention to avoid load-store (and store-load) dependencies. Hierarchical scan logic supplies the relative age indications of loads with respect to stores (and of stores with respect to loads).