Abstract: A system for processing a floating point instruction includes a stack, virtual registers, a stack pointer pointing to one of the virtual registers as top of stack, physical registers, and a reference table mapping the virtual registers to the physical registers, entries of the reference table pointing to physical register locations. An instruction unit generates a plurality of instructions, and a decode unit having a plurality of decoders receives the plurality of instructions from the instruction unit, respectively. The decode unit decodes the plurality of instructions and determines whether any one of the instructions contains a floating point instruction including a floating point exchange instruction. A logic unit is coupled to the reference table and includes a plurality of logic devices coupled to the plurality of decoders in the decode unit, respectively.

Abstract: A laptop computer has a first relatively powerful and fast data processor and a second relatively slower data processor. The first data processor has a higher power consumption factor than the second. A switch mechanism controls which of the two processors is operatively connected to the computer system components. When external power is available, the faster more powerful processor is used. When external power is unavailable and the computer must be operated from the internal power source, the second processor is used to drive the system components in order to provide a longer total operating duty cycle before the internal power source is exhausted.

Abstract: The invention relates to a method and an arrangement for operating a bus system having at least one master unit and at least one slave unit, having a bus and a bus control unit for the bus arbitration and for controlling the data transfer. The data transmission is split into a request data transfer and a response data transfer, and, in the time between the request data transfer and the response data transfer, the bus is cleared for the data transmissions of other master units in a first data transmission configuration, or the bus is blocked between the request data transfer and the response data transfer, in a second data transmission configuration and slave units. In the case of a response transfer, the master and slave are changed round.

Abstract: A computer system including a microprocessor employing a reorder buffer is provided which stores a last in buffer (LIB) indication corresponding to each instruction. The last in buffer indication indicates whether or not the corresponding instruction is last, in program order, of the instructions within the buffer to update the storage location defined as the destination of that instruction. The LIB indication is included in the dependency checking comparisons. A dependency is indicated for a given source operand and a destination operand within the reorder buffer if the operand specifiers match and the corresponding LIB indication indicates that the instruction corresponding to the destination operand is last to update the corresponding storage location. At most one of the dependency comparisons for a given source operand can indicate dependency. According to one embodiment, the reorder buffer employs a line-oriented configuration.

Abstract: A reconfigurable circuit wherein part or all of an instruction or a result of decoding thereof and output of said register file are inputted and a circuit structure thereof can be changed by an external signal is provided. If a bug occurs when part or all of the instruction or the result of decoding thereof and the output of the register file satisfy a particular condition, the reconfigurable circuit is reconstructed by an external signal so as to output a first signal under that particular condition. An interrupt control circuit controls a processing unit so as to carry out processing based on the first signal or processing to avoid the bug when the first signal is inputted.

Abstract: In a massively parallel processing (MPP) system, bandwidth efficiency and message packet latency rates are improved by providing routing elements that detect, isolate and identify various routing errors. More specifically, during the transmission of a message packet from a first routing element to a second routing element in the MPP system, link lock-up can be prevented effectively by determining whether the message packet contains a certain predefined quantity of data. Control codes, used for establishing the end to the message packet, can then be inserted into the message packet if it is determined that the message packet does, in fact, contain the predefined quantity of data.

Abstract: A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated whenever one or more instructions are dispatched. A microprocessor employing the reorder buffer is also configured with fixed, symmetrical issue positions. The symmetrical nature of the issue positions may increase the average number of instructions to be concurrently dispatched and executed by the microprocessor. The average number of unused locations within the line decreases as the average number of concurrently dispatched instructions increases. One particular implementation of the reorder buffer includes a future file. The future file comprises a storage location corresponding to each register within the microprocessor.

Abstract: A microprocessor stores cache-line-related data (e.g. branch predictions or predecode data, in the illustrated embodiments) in a storage which includes fewer storage locations than the number of cache lines in the instruction cache. Each storage location in the storage is mappable to multiple cache lines, any one of which can be associated with the data stored in the storage location. The storage may thereby be smaller than a storage which provides an equal number of storage locations as the number of cache lines in the instruction cache. Access time to the storage may be reduced, therefore providing for a higher frequency implementation. Still further, semiconductor substrate area occupied by the storage may be decreased. In one embodiment, the storage is indexed by a subset of the index bits used to index the instruction cache. The subset comprises the least significant bits of the cache index.

Abstract: Methods, systems (apparatus) and computer program products are provided which control access to a shared resource in a data processing system by predicting utilization of the shared resource based upon historical utilization of the shared resource. Users of the shared resource are then notified of a potential shortage of the shared resource if the prediction predicts that the shared resource will be over-utilized. The prediction may utilize a linear extrapolation to predict future utilization of the share resource. Furthermore, the interval between predictions of the future utilization may be based on time, number of utilization events or a combination of the two.

Abstract: A superscalar microprocessor implements a microcode instruction unit that predicts the end of microcode loops. The microcode instruction unit detects a microcode loop and begins counting the number of iterations of the loop. The microcode sequence that implements the loop includes a microcode instruction that uses the string count as an operand and/or a result. The microcode instruction unit captures the string count when it is available on either an operand or address bus. The string count is compared to the number of iterations of the string loop to determine when to terminate the microcode loop. If the string count is not captured prior to the microcode instruction unit dispatching more microcode instructions than necessary, the microcode instruction unit notifies other components via a cancel bus. In this manner, the end of a loop is detected prior to the functional unit detecting a mispredicted branch instruction within the microcode loop.

Abstract: The data processing circuit has a self-timed instruction execution unit, which operates asynchronously, signalling the completion of processes and starting subsequent processes in response to such signalling. In order to satisfy real time constraints upon program execution ready signals generated after completion of selected instructions are gated with a timer signal before they are used to start a next instruction. In an embodiment, the amount of time left between the ready signal is used to start a next instruction is measured and used to regulate a power supply voltage of the instruction execution unit so that it is just high enough to make the instruction execution unit sufficiently fast to meet the real time constraints.

Abstract: A method and system in a superscalar data processing system are disclosed for the temporary designation and utilization of a plurality of physical registers as a stack. For each of the multiple instructions to be processed during a single clock cycle by the data processing system, a determination is made whether each of the instructions is a particular type of instruction. If a determination is made that an instruction is a particular type of instruction, a quantity of physical registers to be temporarily designated as a stack is determined utilizing the instruction. A second plurality of physical registers available to be utilized as a stack are determined whether the second plurality of the quantity. The second plurality of physical registers are then temporarily designated and utilized as a stack.

Abstract: A distributed, compiler-oriented database is disclosed with operating modes including parallel compilation, parallel simulation and parallel execution of computer programs and hardware models. The invention utilizes a hardware apparatus consisting of shared memory multiprocessors, optionally augmented by processors with re-configurable logic execution pipelines or independently scheduled re-configurable logic blocks and a software database apparatus, manifest in the hardware apparatus, in order to efficiently support parallel database clients such as a source code analyzer, an elaborator, an optimizer, mapping and scheduling, code generation, linking/loading, execution/simulation, debugging, profiling, user interface and a file interface.

Abstract: An apparatus is provided for sampling instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus includes a fetch unit for fetching instructions into a first stage of the pipeline. Certain randomly selected instructions are identified, and state information of the system is sampled while a particular selected instruction is in any stage of the pipeline. Software is informed when the particular selected instruction leaves the pipeline so that the software can read any of the sampled state information.

Abstract: An unpacking circuit and operating method in a very long instruction word (VLIW) processor provides for parallel handling of a packed wide instruction in which a packed wide instruction is divided into groups of syllables. An unpacked instruction representation includes a plurality of syllables, which generally correspond to operations for execution by an execution unit. The syllables in the unpacked instruction representation are assigned to groups. The packed instruction word includes a sequence of syllables and a header. The header includes a descriptor for each group. The descriptor includes a mask and may include a displacement designator. The multiple groups are handled in parallel as the displacement designator identifies a starting syllable. The mask designates the syllables which are transferred from the packed instruction to the unpacked representation and identifies the position of NOPs in the unpacked representation.

Abstract: A microcomputer with embedded flash memory is provided, which has an on-chip programming capability that allows new data to be reprogrammed by the microcomputer itself into the embedded flash memory, without having to use external reprogramming tools. Moreover, a method is provided for programming data into the embedded flash memory of the microcomputer. The microcomputer includes a microprocessor unit, an embedded flash memory unit, a register set, and a bus multiplexer. The embedded flash memory unit is partitioned into a loader block for storing a loader program and a user block for storing at least one user application program. The new data that are to be programmed into the user block of the embedded flash memory unit are first transferred to and stored in the register set. In the embedded flash memory unit, only one of the loader block and the user block can be in active operation, which is controlled by the microprocessor unit.

Abstract: A processor having a modified Harvard architecture having first and second memories, an address register file divided into first and second sets of registers, first and second stream registers, and a general purpose register file for performing data streaming. The first and second sets of registers respectively address the first and second memories which, in turn, load data into the first and second stream registers. An arithmetic logic unit (ALU) accepts the stream registers and general purpose registers as inputs. Stream instructions are encoded such that a single instruction specifies an ALU operation performed on selected ALU inputs and where to store the results of the ALU operation, loads new values into the stream registers, and updates the address registers. A stream instruction has three operand fields respectively specifying two operands for the next ALU operation and a location to store the result of the current ALU operation.

Abstract: An electronic still camera is adapted for use with a portable computer which has a computer housing formed with a battery receiving chamber for receiving removably a battery pack therein, a power supplying device, and a set of first battery charging contacts mounted in the battery receiving chamber for connecting electrically the battery pack to the power supplying device so as to permit recharging of the battery pack when the power supplying device is active, and so as to enable the battery pack to supply electrical power to the portable computer when the power supplying device is inactive.

Abstract: A system within a multisystem environment is selected to run a real-time application. The selection process looks for a system in which the amount of a processor resource for delivering a real-time data stream of the real-time application has the least impact on other work processing on the selected system. The real-time application is allocated an amount of a processor resource that does not exceed a limit chosen for a group of one or more real-time applications. A selected amount of the processor resource remains available for at least one non-real-time application of the multisystem environment.

Abstract: A distributed interrupt controller system for use in a multiprocessor environment, having at least two local programmable interrupt controllers (LOPICs) coupled to at least one central programmable interrupt controller (COPIC) via a dedicated bus. One of the at least one COPICs functions as a master arbiter, while the LOPICs, each of which may be integrated with its corresponding processing unit, and other non-master COPICs are treated as bus agents. Bus grant is achieved by a "round robin" arbitration protocol. For distributed delivery of interrupts, the master arbiter compares a current-task-priority-register value associated with each bus agent to determine the agent that is least busy for delivery of the interrupt thereto.