Abstract: A light emitting diode driving integrated circuit with a multi-step current setting function includes a regulator circuit, a variable resistor circuit, and a current generation unit. The regulator circuit provides a supply voltage to a first terminal of at least one series of light emitting diodes to drive the at least one series of light emitting diodes, and regulates a second terminal voltage of the at least one series of light emitting diodes to a target voltage. The variable resistor circuit is used for changing a resistance of the variable resistor circuit in a plurality of steps according to a switching signal. The current generation unit is coupled to the variable resistor circuit for changing current flowing through the at least one series of light emitting diodes in a plurality of steps according to a reference voltage and variation of the resistance of the variable resistor circuit.

Abstract: Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block.

Abstract: A system and method of controlling a lighting system is provided. Lamp insertion detectors are coupled to a ballast and detect when relamping occurs. The outputs of the lamp insertion detectors are coupled together to provide a single input of a timing circuit. The timing circuit generates an output having a predetermined duration. This timing circuit output is received by a ballast driver circuit, which causes the ballast to provide a high voltage to a lamp socket for a predetermined duration of the timing circuit output to ignite the new lamp.

Abstract: According to one embodiment, a lighting system includes a luminaire and a lighting control device. The lighting control device includes an operation section, a target-value managing section, a transmitting section, and a display section and controls the luminaire. The target-value managing section stores an operation state of the luminaire and, when the operation section is operated, calculates an operation target value on the basis of the stored operation state of the luminaire and updates the operation state to the operation target value serving as an operation state of the luminaire after the operation. The transmitting section transmits the operation target value as a radio signal. The display section performs display based on the operation target value.

Abstract: The present invention relates to a preheating control device controlling lamp preheating, a lamp driving device including the same, and a preheating control method thereof. A preheating control device according to an exemplary embodiment of the present invention generates a preheating control voltage that is changed according to a passage of a preheating time of a lamp and generation of a lamp current of the lamp. An oscillator signal having a frequency according to a preheating control voltage is generated, and if the lamp current is generated in the lamp, the preheating control voltage is changed to more than a predetermined reference voltage such that the frequency of the oscillator signal may be decreased.

Abstract: A circuit for lighting a semiconductor light source is provided. The circuit includes: a switching regulator including a switching element and configured to generate a drive current for the semiconductor light source using the switching element; and a control circuit configured to control on-off of the switching element such that the magnitude of the drive current comes close to a targeted value. The control circuit includes: a comparator configured to compare the magnitude of the drive current with the targeted value; an up/down counter configured to count a digital value in a counting-up direction or counting-down direction, based on a comparison result of the comparator; a digital-to-analog converter configured to convert the counted digital value into an analog signal; and a drive circuit configured to control on/off of the switching element based on the analog signal.

Abstract: An electronic ballast for driving a light-emitting device, includes a square wave generator having a plurality of switch elements for converting a DC input voltage into a square-wave AC voltage. A transformer has a driving winding and a plurality of inductive windings mutually connected with each other, in which at least a portion of the inductive windings are respectively connected to a control terminal of the switch element. A resonant circuit connects the driving winding and a light-emitting device and converts the square-wave voltage into an AC output voltage to drive the light-emitting device. An auxiliary control unit connected to the transformer regulates a voltage waveform of the driving winding or a voltage waveform of the inductive winding according to a control signal, thereby changing the voltage waveform of the inductive winding connected to the switch element to adjust the switching frequencies of the switch elements.

Abstract: A device includes an output circuit including a plurality of unit buffers, each of the unit buffers having an adjustable impedance; a controller circuit operable to selectively activate at least one of the unit buffers; and an impedance adjustment part operable to adjust the impedance of each of the unit buffers in response to a change of the number of the unit buffers that are selectively activated by the controller circuit.

Abstract: A method of sharing in use an impedance matching circuit of a memory circuit to perform an initial calibration and a full time refresh mode calibration includes supplying power to the memory circuit, utilizing the impedance matching circuit to perform the initial calibration on the memory circuit, the memory circuit exiting the initial calibration, the memory circuit entering a driving mode, the memory circuit exiting the driving mode every a predetermined interval, utilizing the impedance matching circuit to perform the full time refresh mode calibration on the memory circuit according to a refresh command, an output voltage detection circuit determining a level of an output voltage of the memory circuit, and performing a corresponding operation according to a determination result generated by the output voltage detection circuit.

Abstract: Methods and apparatus for controlling a high intensity discharge lamp and a power supply system for the high intensity discharge lamp are disclosed. The system relates to a method for controlling high intensity discharge lamp comprising supplying a signal of variable frequency and constant filling factor from a switches cascade to a ballast circuit and the lamp, said ballast circuit having at least one condenser and at least one inductance. The method uses the signal of periodically fluctuating frequency and constant filling factor of 50%, supplied from the electronic switches cascade of the half-bridge type, connected with the ballast circuit and the lamp, where the ballast circuit includes at least first condenser, the lamp and includes first inductance and second condenser forming a resonant circuit. A supply system for high intensity discharge lamp is also disclosed.

Abstract: New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is an AND-Inverter Cone (AIC), which is a binary tree including one or more AND gates with a programmable conditional inversion and a number of intermediary outputs. Compared to LUTs, AICs are richer in terms of input and output bandwidth, because the area of the AICs grows only linearly with the number of inputs. Also, the delay grows only logarithmically with the input count. The new logic blocks can map circuits more efficiently than LUTs, because the AICs are multi-output blocks and can cover more logic depth due to the higher input bandwidth.

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Abstract: A multiple signal format output driver is configurable to provide a current-mode logic (CML) output signal in response to a CML value of one or more first values of the control signal. The output driver is configurable to provide a low-power, low-voltage positive emitter-coupled logic (low-power LVPECL) output signal in response to a low-power LVPECL value of the one or more first values of the control signal. The output driver is configurable to provide a low-voltage differential signaling (LVDS) output signal in response to an LVDS value of the one or more first values of the control signal. The output driver may be configurable to provide a LVPECL output signal in response to a second value of the control signal. The output driver may be configurable to provide a high-speed current steering logic (HCSL) output in response to a third value of the control signal.

Abstract: A bandgap ready circuit for an RFID tag includes a bandgap circuit for providing a bandgap voltage, a first comparator for monitoring first and second voltages in the bandgap circuit and for providing a first logic signal, a second comparator for monitoring third and fourth voltages in the bandgap circuit and for providing a second logic signal, and a logic circuit for combining the first and second logic signals to provide a bandgap ready logic signal.

Abstract: The present invention relates to an LED light emitting device and a driving method thereof. The LED light emitting device supplies a power supply voltage to at least two LED channels. The LED light emitting device samples channel voltages of the at least two LED channels to detect a minimum voltage from among the sampled voltages, and amplifies a difference between the detected minimum voltage and a predetermined reference voltage to generate an error amplifying signal. The LED light emitting device generates an enable signal having a duty extended by a predetermined delay period from a duty of a dimming signal for controlling light emission periods of the at least two LED channels. In this instance, the error generator is operable by the enable signal.

Abstract: Methods and apparatus for decoding of binary addresses and scanning rows and columns of an addressable array. In one example, an address decode circuit includes a first decoder circuit configured to partition an N-bit address into a plurality of address segments, each address segment including fewer than N bits, and N being a positive integer, the first decoder circuit configured to provide a plurality of first-stage decoded address outputs, and a second orthogonal decoder circuit coupled to the first decoder circuit and configured to receive the first-stage decoded address outputs and to produce 2N unique addresses from unique combinations of the plurality of first-stage decoded address outputs.

Abstract: A tamper-resistant bus architecture for secure lock bit transfer in an integrated circuit includes a nonvolatile memory having an n-bit storage region for storing encoded lock bits, A plurality of read access circuits are coupled to the nonvolatile memory. An n-bit tamper-resistant bus is coupled to the read access circuits. A decoder is coupled to the tamper-resistant bus. A k-bit decoded lock signal bus is coupled to the decoder. A controller is coupled to the k-bit decoded lock signal bus.

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring a portion of a memory array. The PR circuitry may include a host circuit, a control circuit, an address register, and first, second, and third data registers. The host circuit may send a series of PR instructions to the control circuit. The control circuit may include a decompression circuit for decompressing compressed instructions, a decryption circuit for decrypting encrypted instructions, an error checking circuit for detecting errors in the instructions, and a logic circuit. The address register may select a desired frame. The selected frame may be loaded into the third data register. The contents of the third data register may be shifted into the first data register. The contents of the first data register may be modified according to a desired logic function using the logic circuit, shifted into the second data register, and written into the selected frame.

Abstract: The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs have a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.

Abstract: A LED lamp includes housing, a circuit layer, at least one LED die, a light-transmitting adhesive, a lamp shade, a light-transmitting liquid and the conductive connector. One end of the housing has a protrusion. The circuit layer is placed on the protrusion. The LED die is placed on the protrusion and electrically connected to the circuit layer. The light-transmitting adhesive covers the circuit layer and the light emitting die. The lamp shade including a plurality of ventilating holes is connected to the housing, and an accommodating space is cooperatively defined by the lamp shade and the housing. The light-transmitting liquid is filled within the accommodating space, and the LED die is sunk therein.