Abstract: The present invention relates to a method for producing an electrical conductor element with a housing and a conductor element, whereby the housing is made by a molding process and the conductor is embedded in the housing, whereby the conductor is produced by an electroforming process on a metallic layer. The conductor and the metallic layer are covered with the housing by a molding process, and the metallic layer is removed from the conductor and the molding housing. This method advantageously combines the well known molding process and the well known electroforming process for providing a reliable process for producing an electrical conductor element.

Abstract: An integrated circuit and method of fabricating the integrated circuit. The integrated circuit, including: one or more power distribution networks; one or more ground distribution networks; one or more data networks; and fuses temporarily and electrically connecting power, ground or data wires of the same or different networks together, the same or different networks selected from the group consisting of the one or more power distribution networks, the one or more ground distribution networks, the one or more data networks, and combinations thereof.

Abstract: In one embodiment, a power switch device (33) includes a first MOSFET device 41 and a second MOSFET device (42). A split gate structure (84) including a first gate electrode (48,87) controls the first MOSFET device (41). A second gate electrode (49,92) controls the second MOSFET device (42). A current limit device (38) is coupled to the first gate electrode (48,97) to turn on the first MOSFET device during a current limit mode. A comparator device (36) is coupled to the second gate electrode (49,92) to turn on the second MOSFET device (42) when the power switch device (33) is no longer in current limit mode.

Abstract: A tunnel barrier in proximity with a layer of a rare earth element-transition metal (RE—TM) alloy forms a device that passes negatively spin-polarized current. The rare earth element includes at least one element selected from the group consisting of Gd, Tb, Dy, Ho, Er, Tm, and Yb. The RE and TM have respective sub-network moments such that the absolute magnitude of the RE sub-network moment is greater than the absolute magnitude of the TM sub-network moment. An additional layer of magnetic material may be used in combination with the tunnel barrier and the RE—TM alloy layer to form a magnetic tunnel junction. Still other layers of tunnel barrier and magnetic material may be used in combination with the foregoing to form a flux-closed double tunnel junction device.

Abstract: The absolute value of the threshold voltage of a P-channel TFT is reduced by making its channel length shorter than that of an N-channel TFT by at least 20%, to thereby approximately equalize the threshold voltage absolute values of those TFTs.

Abstract: A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface of the stripes. ROM cell personalization is the presence or absence of a diode and/or contact.

Abstract: A metal interconnect structure formed over a substrate in an integrated circuit that traverses a scribe-line boundary between a first die and a second die includes at least one metal interconnect line that traverses the scribe-line boundary. A switch is coupled between the at least one metal interconnect line and the substrate, the switch having a control element coupled to a scribe-cut control line. The control line turns the switch on if the two dice are separated into individual dice and turns the switch off if the two dice are to remain physically connected so that the interconnect line may be used to make connections between circuits on the two dice.

Abstract: The invention relates to a semiconductor element with metallic and non-metallic surfaces, with the non-metallic surfaces of the semiconductor being provided with a layer which has irregularities, so that adhesion between the non-metallic surface and the molding compound is thus increased.

Abstract: A high voltage device with retrograde well is disclosed. The device comprises a substrate, a gate region formed on the substrate, and a retrograde well placed in the substrate next to the gate region, wherein the retrograde well reduces a dopant concentration on the surface of the substrate, thereby minimizing damages to the gate region.

Abstract: A negative resistance field-effect element that is a negative differential resistance field-effect element capable of achieving negative resistance at a low power supply voltage (low drain voltage) and also enabling securement of a high PVCR is formed on its InP substrate 11 having an asymmetrical V-groove whose surface on one side is a (100) plane and surface on the other side is a (011) plane with an InAlAs barrier layer (12) that has a trench (TR) one of whose opposed lateral faces is a (111) A plane and the other of which is a (331) B plane. An InGaAs quantum wire (13) that has a relatively narrow energy band gap is formed at the trench bottom surface as a high-mobility channel. An InAlAs modulation-doped layer (20) having a relatively wide energy band gap is formed on the quantum wire as a low-mobility channel.

Abstract: Device structures for sheets of light active material. A first substrate has a transparent first conductive layer. A pattern of light active semiconductor elements are fixed to the first substrate. The light active semiconductor elements have an n-side and a p-side. Each light active semiconductor element has either of the n-side or the p-side in electrical communication with the transparent conductive layer. A second substrate has a second conductive layer. An adhesive secures the second substrate to the first substrate so that the other of said n-side or said p-side of each said light active semiconductor element is in electrical communication with the second conductive layer. Thus forming a solid-state light active device.

Abstract: A semiconductor device is disclosed that includes a semiconductor element, a circuit board electrically connected to the semiconductor element, a heat dissipation member fixed to the first surface of the circuit board and thermally coupled to the semiconductor element, and an interposer provided to the second surface of the circuit board facing away from the heat dissipation member. The interposer is electrically connected to the circuit board. An opening is formed in the circuit board and the interposer so that the semiconductor element is thermally coupled directly to the heat dissipation member through the opening.

Abstract: Provided is a non-planar transistor with a multi-gate structure that includes a germanium channel region, and a method of manufacturing the same. The non-planar transistor includes a silicon body and a channel region that covers exposed surfaces of the silicon body. The channel region is formed of a germanium layer and includes a first channel region and a second channel region. In order to form the germanium channel region, a mesa type active region is formed on the substrate, and a germanium layer is formed to cover two sidewalls and an upper surface of the active region.

Abstract: In a semiconductor optical device, a first conductive type semiconductor region is provided on a surface of GaAs. The first conductive type semiconductor region has a first region and a second region. An active layer is provided on the first region of the first conductive type semiconductor region. The active layer has a pair of side surfaces. A second conductive type semiconductor region is provided on the sides and top of the active layer, and the second region of the first conductive type semiconductor region. The bandgap energy of the first conductive type semiconductor region is greater than that of the active layer. The bandgap energy of the second conductive type semiconductor region is greater than that of the active layer. The second region of the first conductive type semiconductor region and the second conductive type semiconductor region constitute a pn junction.

Abstract: In a semiconductor device including a memory unit and a logic unit, a generation of a step in a terminal end surface of an electroconductive plug in a region above a capacitor element is inhibited. Such semiconductor device includes an insulating layer provided on the semiconductor substrate extending from the memory unit to the logic unit; a plurality of second interconnect connecting plugs embedded in the interlayer insulating film and the interlayer insulating film in the logic unit; capacitor elements embedded in the interlayer insulating film in memory unit; and dummy plugs, embedded in the interlayer insulating film and the interlayer insulating film in a region above a region that is provided with the capacitor element in the memory unit, and insulated from the capacitor element. A plurality of second interconnect connecting plugs and the dummy plug are terminated in the top surface of the interlayer insulating film.

Abstract: Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells sharing a bit-line contact include a first capacitor below the substrate surface. The pair of memory cells further include a second capacitor such that at least a portion of the second capacitor is underlying the first capacitor. Such memory cell capacitors can thus have increased surface area for a given capacitor height versus memory cell capacitors formed strictly laterally adjacent one another. The memory cell capacitors can be fabricated using silicon-on-insulator (SOI) techniques. The memory cell capacitors are useful for a variety of memory arrays, memory devices and electronic systems.

Abstract: In an integrated circuit package, a method for insulation and reinforcement of individual bonding wires in an integrated circuit package. Using an airbrush, bonding wires are sprayed and coated with an insulating material prior to the molding process. Mold flow induced short rejects are eliminated as a result of: (a) Electrically insulating the bonding wires by coating them with an insulating mixture; (b) Physically isolating the bonding wires as a result of bead formation around individual bonding wires, with the insulating beads acting as contact barriers between the bonding wires; and (c) Enhancing the structural rigidity of the bonding wires as a result of the coating. Reinforcement and separation of bonding wires also reduces inductive coupling and/or crosstalk interference due to proximity of bonding wires.

Abstract: A production method for an image sensor which is provided with a plurality of sensor portions arranged on a semiconductor substrate and each having a first photodiode constituted by a first region of a first conductivity type and a second region of a second conductivity type different from the first conductivity type and a second photodiode constituted by the second region and a third region of the first conductivity type. The method includes the steps of: forming a second region of the second conductivity type on a first region defined in a semiconductor substrate by epitaxial growth; and forming a third region of the first conductivity type on the second region by epitaxial growth.

Abstract: A method for patterning a magnetic memory cell junction is provided herein, which includes etching exposed portions of a stack of layers to a level spaced above a tunneling barrier layer of the stack of layers. In addition, the method may include implanting dopants into exposed portions of the stack of layers. For example, the method may include oxidizing and/or nitriding the exposed portions of the stack of layers. In some embodiments, the steps of etching and implanting dopants may form an upper portion of the magnetic cell junction. Alternatively, the method may include alternating the steps of etching and implanting dopants throughout the thickness of the exposed portions of the stack of layers. In either case, the stack of layers may include a magnetic layer which includes a material adapted to prevent the introduction of dopants underlying the tunneling barrier layer during the step of implanting.

Abstract: A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film provided on the semiconductor substrate, a floating gate electrode provided on the tunnel insulating film, the width of the floating gate electrode changing in the height direction of the non-volatile memory cell in channel width or length direction there, and being thinnest between a region above the bottom surface of the floating gate electrode and a region below the upper surface thereof, a control gate electrode above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.