Abstract: There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal is sliced so as to be tilted from the (100) plane in a direction of [101] or [10-1] when a notch is formed in a direction of [010], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [0-10] or [010] when a notch is formed in a direction of [001], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [001] or [00-1] when a notch is formed in a direction of [0-10], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [010] or [0-10] when a notch is formed in a direction of [00-1].

Abstract: There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal is sliced so as to be tilted from the (100) plane in a direction of [101] or [10-1] when a notch is formed in a direction of [010], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [0-10] or [010] when a notch is formed in a direction of [001], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [001] or [00-1] when a notch is formed in a direction of [0-10], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [010] or [0-10] when a notch is formed in a direction of [00-1].

Abstract: A method of manufacturing a semiconductor device that provides a semiconductor device having improved channel mobility includes a process of forming a gate insulation film of silicon oxide film, silicon nitride film or silicon oxide nitride film or the like on a silicon oxide substrate, and following formation of the gate insulation film on the silicon oxide substrate with heat treatment for a given time at a temperature range of 900° C. to 1000° C. in an atmosphere containing not less than 25% H2O (water).

Abstract: A method of forming a device (and the device so formed) comprising the following steps. A structure having a gate structure formed thereover is provided. Respective low doped drains are formed within the structure at least adjacent to the gate structure. A pocket implant is formed within the structure. The structure adjacent the gate structure is etched to form respective trenches having exposed side walls. Respective first liner structures are formed at least over the exposed side walls of trenches. Respective second liner structures are formed over the first liner structures. Source/drain implants are formed adjacent to, and outboard of, second liner structures to complete formation of device.

Abstract: A metal oxide semiconductor transistor comprising a first doping type substrate, an isolation layer, a plurality of gates, a masking layer, a gate oxide layer, a plurality of second doping type source/drain regions and spacers. The first doping type substrate has a plurality of trenches patterning out a plurality of first doping type strips. The isolation layer is disposed within the trenches. The gates is disposed over the first doping type strips and oriented in a direction perpendicular to the first doping type strips. The masking layer is disposed over the first doping type substrate. The gate oxide layer is disposed between the sidewall of the first doping type strips and the gate. The second doping type source/drain regions are disposed in the first doping type strip on each side of the gate. The spacers are disposed on the sidewalls of the gates and the first doping type strips.

Abstract: A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction <100>) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.

Abstract: The invention provides a carbon nanotube field effect transistor including a nanotube having a length suspended between source and drain electrodes. A gate dielectric material coaxially coats the suspended nanotube length and at least a portion of the source and drain electrodes. A gate metal layer coaxially coats the gate dielectric material along the suspended nanotube length and overlaps a portion of the source and drain electrodes, and is separated from those electrode portions by the gate dielectric material. The nanotube field effect transistor is fabricated by coating substantially the full suspended nanotube length and a portion of the source and drain electrodes with a gate dielectric material. Then the gate dielectric material along the suspended nanotube length and at least a portion of the gate dielectric material on the source and drain electrodes are coated with a gate metal layer.

Abstract: A semiconductor device (1) has a source (2) a gate (3) and a drain (4), a single deep-pocket ion implant (8) in a source-drain depletion region, and a single shallow-pocket ion implant (9) in the source-drain depletion region.

Abstract: A semiconductor device having a nonconductive cap layer comprising a first metal element. The nonconductive cap layer comprises a first metal nitride, a first metal oxide, or a first metal oxynitride over conductive lines and an insulating material between the conductive lines. An interface region may be formed over the top surface of the conductive lines, the interface region including the metal element of the cap layer. The cap layer prevents the conductive material in the conductive lines from migrating or diffusing into adjacent subsequently formed insulating material layers. The cap layer may also function as an etch stop layer.

Abstract: A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.

Abstract: A memory circuit and method to reduce array noise due to wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). Each row has a first part (1102) and a second part (1108). A first conductor (750) is coupled to a respective column of memory cells in each first part. A second conductor (752) is coupled to a respective column in each second part. A third conductor is coupled to a control terminal of each memory cell in the first part (1102) of a first row and the second part (1108) of a second row.

Abstract: To increase the lattice constant of AlInGaP LED layers to greater than the lattice constant of GaAs for reduced temperature sensitivity, an engineered growth layer is formed over a substrate, where the growth layer has a lattice constant equal to or approximately equal to that of the desired AlInGaP layers. In one embodiment, a graded InGaAs or InGaP layer is grown over a GaAs substrate. The amount of indium is increased during growth of the layer such that the final lattice constant is equal to that of the desired AlInGaP active layer. In another embodiment, a very thin InGaP, InGaAs, or AlInGaP layer is grown on a GaAs substrate, where the InGaP, InGaAs, or AlInGaP layer is strained (compressed). The InGaP, InGaAs, or AlInGaP thin layer is then delaminated from the GaAs and relaxed, causing the lattice constant of the thin layer to increase to the lattice constant of the desired overlying AlInGaP LED layers. The LED layers are then grown over the thin InGaP, InGaAs, or AlInGaP layer.

Abstract: A micromechanical switch comprises a substrate, at least one pair of support members fixed to the substrate, at least one pair of beam members placed in proximity and parallel to each other above the substrate, and connected to one of the support members, respectively, each of the beam members having a moving portion which is movable with a gap with respect to the substrate, and a contact portion provided on the moving portion, and a driving electrode placed on the substrate between the pair of beam members to attract the moving portions of the beam members in a direction parallel to the substrate with electrostatic force so that the contact portions of the beam members which are opposed to each other are short-circuited.

Abstract: A split gate type flash memory device and a method of manufacturing the split gate type flash memory device are disclosed. The split gate type flash memory device includes a silicon epitaxial layer formed in an active region of a bulk silicon substrate and a disturbance-preventing insulating film formed in the bulk silicon substrate between a source region and a drain region of the device. According to selected embodiments of the invention, the disturbance-preventing insulating film is formed using a Shallow Trench Isolation (STI) forming process.

Abstract: A memory device comprising a access circuits, an electrode layer over the access circuits, an array of phase change memory bridges over the electrode layer, and a plurality of bit lines over the array of phase change memory bridges. The electrode layer includes electrode pairs. Electrode pairs include a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. A bridge of memory material crosses the insulating member, and defines an inter-electrode path between the first and second electrodes across the insulating member.

Abstract: A MOSgated trench device has a reduced on resistance by forming a less than about a 13 nm thick strained SiGe layer on the silicon surface of the trenches and forming a thin (30 nm or less) layer of epitaxially deposited silicon on the SiGe layer which epi layer is converted to a gate oxide layer. The conduction channel formed by the SiGe layer is permanently strained to increase its mobility particularly hole mobility.

Abstract: A transistor fabrication method includes forming an electrode overlying a channel of a semiconductor on insulator (SOI) substrate. Source/drain structures are formed in the substrate on either side of the channel. The source/drain structures include a layer of a second semiconductor over a first semiconductor. The first and second semiconductors have different bandgaps. The second semiconductor extends under the gate electrode. The source/drain structures may be formed by doping the source/drain regions and etching the doped regions selectively to form voids. A film of the second semiconductor is then grown epitaxially to fill the void. A film of the first semiconductor may be grown to line the void before growing the second semiconductor. Alternatively, the second semiconductor is a continuous layer that extends through the channel body. A capping layer of the first semiconductor may lie over the second semiconductor in this embodiment.

Abstract: A Schottky barrier rectifier, in accordance with embodiments of the present invention, includes a first conductive layer and a semiconductor. The semiconductor includes a first doped region, a second doped region and a plurality of third doped regions. The second doped region is disposed between the first doped region and the first conductive layer. The plurality of third doped regions are disposed in the second doped region. The first doped region of the semiconductor is heavily doped with a first type of dopant (e.g., phosphorous or arsenic). The second doped region is moderately doped with the first type of dopant. The plurality of third doped regions are moderately to heavily doped with a second type of dopant.

Abstract: A semiconductor layout structure for an electrostatic discharge (ESD) protection circuit is disclosed. The semiconductor layout structure includes a first area, in which one or more devices are constructed for functioning as a silicon controlled rectifier, and a second area, in which at least one device is constructed for functioning as a trigger source that provides a triggering current to trigger the silicon controlled rectifier for dissipating ESD charges during an ESD event. The first area and the second area are placed adjacent to one another without having a resistance area physically interposed or electrically connected therebetween, such that the triggering current received by the silicon controlled rectifier is increased during the ESD event.

Abstract: A semiconductor light emitter includes a quantum well active layer which includes nitrogen and at least one other Group-V element, and barrier layers which are provided alongside the quantum well active layer, wherein the quantum well active layer and the barrier layers together constitute an active layer, wherein the barrier layers are formed of a Group-III-V mixed-crystal semiconductor that includes nitrogen and at least one other Group-V element, a nitrogen composition thereof being smaller than that of the quantum well active layer.