Abstract: Methods of forming and the integrated circuit device structure formed having vertical interfaces adjacent an existing crack stop around a perimeter of a chip, whereby the vertical interface controls cracks generated during side processing of the device such as dicing, and in service from penetrating the crack stop. The vertical interface is comprised of a material that prevents cracks from damaging the crack stop by deflecting cracks away from penetrating the crack stop, or by absorbing the generated crack energies. Alternatively, the vertical interface may be a material that allows advancing cracks to lose enough energy such that they become incapable of penetrating the crack stop. The present vertical interfaces can be implemented in a number of ways such as, vertical spacers of release material, vertical trenches of release material or vertical channels of the release material.

Abstract: A mixed-signal integrated circuit includes a metal-insulator-metal or polysilicon-insulator-polysilicon capacitor. The electrical path from one electrode of the capacitor passes through a first interconnecting line, then through multiple via holes to a second interconnecting line. During the fabrication process, the capacitor is first charged during a plasma deposition process used to deposit an interlayer dielectric film between the first and second interconnecting lines, then abruptly discharged during a plasma etching process that forms the via holes. The discharge does not damage the floors of the via holes, however, because each of the multiple via holes carries only part of the discharge current.

Abstract: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layer is less than 1500 ?, e.g., between 100 and 750 ?. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting of aluminum is formed on top of the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.

Abstract: A sensor includes an array of pixels organized in rows and columns and a plurality of metal busses overlaying the array of pixels. A first column of pixels includes a proximal set of first pixels and a distal set of first pixels separated by a first jog region. A second column of pixels includes a proximal set of second pixels and a distal set of second pixels separated by a second jog region. The first jog region is displaced in a column direction and in a lateral direction transverse to the column direction from the second jog region. A first metal bus is insulatively disposed over both the first and second jog regions.

Abstract: An EEPROM cell that combines a FET transistor and a capacitor. The transistor has a well that is shared by potentially all of the EEPROM cells in the array thereby reducing size. A gate terminal is formed over the well. Source and drain terminals are formed in the well. The well is isolated from the gate terminal using a dielectric layer. A first terminal of the capacitor is connected to the gate terminal using a dielectric layer. A first terminal of the capacitor is connected to the gate terminal, and may be oppositely doped from the gate terminal to improve retention. The second terminal is formed by a second well that is underneath the first terminal and isolated from the first terminal. The capacitance may be increased without area increase by forming a metal layer over the first terminal and separated from the first terminal by a thick dielectric layer, and connected to the second well via a conductive via.

Abstract: The claimed invention discloses an ESD protection circuit that is applied to an IC with power-down-mode operation. When the IC goes into power-down-mode operation, leakage current and charging from the I/O pad to the VDD power line could be prevented by applying the present invention. Therefore, the malfunction of the IC can be avoided. There still have two ESD clamp circuits respectively connected between the VDD power line and the VSS power line and between ESD bus line and VSS power line, so as to achieve the whole chip ESD protection scheme. The present invention can prevent ESD protection circuit from resulting in leakage current or malfunction under power-down-mode operation, and moreover achieve whole chip ESD protection scheme.

Abstract: The invention relates to an avalanche radiation detector comprising a semiconductor substrate (HK) with a front side (VS) and a back side (RS), an avalanche region (AB) which is arranged in the semiconductor substrate (HK) on the front side (VS) of the semiconductor substrate (HK) and a control electrode (R) for adjusting the electric field strength in the avalanche region (AB). It is proposed that the control electrode (R) is also arranged on the front side of the semiconductor substrate (HK).

Abstract: Each of an electrooptical device and a driving substrate for the electrooptical device includes a first substrate having a display section provided with pixel electrodes and a peripheral-driving-circuit section provided on the periphery of the display section, a second substrate, and an optical material disposed between the first substrate and the second substrate. A gate section including a gate electrode and a gate-insulating film is formed on one surface of the first substrate, a compound layer having high lattice matching with single-crystal silicon is formed on the surface of the first substrate, and a single-crystal silicon layer is formed on the first substrate including the compound layer and the gate section. The single-crystal silicon layer constitutes a channel region, a source region, and a drain region.

Abstract: Method of manufacturing a semiconducting organic laminated structure, for use in an electronic circuit, in particular a logic and/or memory circuit, wherein a substrate is coated with a solution or dispersion containing a small proportion of an organic composite and having a certain wet-layer thickness, which by drying is converted into an organic thin layer with semiconducting properties that adheres to the substrate and has a dry-layer thickness substantially less than the wet-layer thickness, in particular by an order of magnitude or more, the drying being accomplished by brief irradiation with electromagnetic radiation that has its main effective component in the near-infrared range, in particular in the region between 0.8 and 1.5 ?m.

Abstract: An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor. The interface layer may include a layer of a passivating material (e.g., made from nitrogen, oxygen, oxynitride, arsenic, hydrogen and/or fluorine) and sometimes also includes a separation layer. In some cases, the interface layer may be a monolayer of a semiconductor passivating material. The interface layer thickness corresponds to a minimum specific contact resistance of less than or equal to 10 ?-?m2 or even less than or equal to 1 ?-?m2 for the electrical device.

Abstract: Stress balanced semiconductor device packages, a method of forming, and a method of modifying a mold segment for use in the method are disclosed. A semiconductor die is attached to one side of a substrate having discrete conductive elements such as a ball grid array (BGA) on the opposing side thereof. An envelope of encapsulant material is disposed over the semiconductor die on one side of the substrate while a stress balancing structure comprising at least one stem member and at least one transversely extending branch member formed of encapsulant material is disposed over the opposing side of the substrate in an arrangement which does not interfere with the discrete conductive elements. The envelope and the stress balancing structure may be simultaneously formed.

Abstract: Some spin tunnel transistors with a larger current transmittance and a higher MR ratio are described. One of the spin tunnel transistor comprises a collector; an emitter; a base formed between the collector and the emitter, including a first ferromagnetic metal layer variable in its magnetization under an external magnetic field; a barrier layer formed between the first ferromagnetic metal layer and one of the collector and the emitter, the other of the collector and the emitter including a semiconductor crystal layer; and a transition metal silicide crystal layer between the semiconductor crystal layer and the base. The transition metal silicide crystal layer may be replaced with a palladium layer, a transition metal nitride layer, or a transition metal carbide layer.

Abstract: Devices and systems including a heat spreader with possibly controlled thermal expansion. For example, an integral heat spreader may include an insert formed of a high thermal conductivity material with a first coefficient of thermal expansion, and a ring formed of a stiff material with a second coefficient of thermal expansion, wherein the second coefficient of thermal expansion is smaller or significantly smaller than the first coefficient of thermal expansion. An integral heat spreader may optionally include, for example, a plating, a coating, or a patch, and may be included, for example, in a semiconductor device.

Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Abstract: A vertical unipolar component formed in a semiconductor substrate. An upper portion of the substrate includes insulated trenches filled with a vertical multiple-layer of at least two conductive elements separated by an insulating layer, the multiple-layer depth being at most equal to the thickness of the upper portion.

Abstract: A method for routing signals in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with at least one differential signal line pair aligned along a common plane that is substantially transverse to a top surface of the multilayer substrate, jogging a first differential signal line associated with a differential signal line pair at a first redistribution layer in a direction along the common plane, and jogging a second differential signal line associated with the differential signal line pair at a second redistribution layer along the common plane in a same direction as the first differential signal line to provide a substantially balanced differential signal line pair.

Abstract: This invention provides a horizontal MOS transistor capable of improving current drivability and reducing ON resistance by optimizing the gate wiring structure and the disposition structure of source/drain layers. First gate wirings are disposed in the X direction at a pitch Y1 in the Y direction and second gate wirings 12 are disposed in the Y direction with two pieces as a pair such that they meander at a pitch X1 in the X direction. The meandering of the second gate wiring 12 is formed so as to sandwich the bent portions 14 substantially in the center of the pitch Y1. A bottle-like shape diffusion layer region in which the wide-width region and narrow-width region are combined is sectioned by adjacent first and second wirings. A contact 16 for connecting the diffusion layer region to the wiring layer 18 is disposed in the wide-width region and wiring layers 18 are disposed such that two rows run in parallel in the X direction.

Abstract: A nitride semiconductor substrate having a diameter of 10 mm or more, which has a single-layer structure composed of a nitride semiconductor layer having a basic composition represented by AlxGa1?xN (0?x?1), or a multi-layer structure comprising the nitride semiconductor layer, the mass density of the nitride semiconductor layer being 98% or more of a theoretical mass density ? (x) represented by the following general formula (1): ? ? ( x ) = 4 ? ( M x + M N ) 3 ? a x 2 ? c x ? N a , ( 1 ) wherein ax=aGaN+(aAlN?aGaN)x, wherein aGaN represents an a-axis length of GaN, and aAlN represents an a-axis length of AlN; cx=cGaN+(cAlN?cGaN)x, wherein cGaN represents a c-axis length of GaN, and CAlN represents a c-axis length of AlN; Mx=MGa+(MAl?MGa)x, wherein MGa represents the atomic weight of Ga, and MAl represents the atomic weight of Al; MN represents the atomic weight of nitrogen; and Na represents Avogadro's number.

Abstract: A magnetoresistive or magnetic memory element and a magnetic random access memory having one or more magnetic memory elements. The memory element includes a magnetic tunnel junction including first and a second magnetic layers. The first magnetic layer having a free magnetization. The free magnetization of the first magnetic layer is magnetically coupled to a first current line and a second current line for switching the free magnetization, and a mechanism for applying a static magnetic offset field in the direction of at least one of the first and second current lines.

Abstract: A lower cladding layer is laminated on a substrate and constituted of at least one layer. A light absorption layer is laminated on the lower cladding layer. An upper cladding layer is laminated above the light absorption layer and constituted of at least one layer. A light incident end surface is provided on at least one of the substrate and the lower cladding layer, and, when a light is made incident at a predetermined angle, enables the light to be absorbed in the light absorption layer and to be output as a current. An equivalent refractive index of the at least one of the substrate and the lower cladding layer is larger than that of the upper cladding layer. The predetermined angle is an angle enabling a light incident into the light absorption layer to be reflected at a lower surface of the upper cladding layer.