Patents Examined by Ngan V. Ngo
  • Patent number: 10410999
    Abstract: A semiconductor package having an internal heat distribution layer and methods of forming the semiconductor package are provided. The semiconductor package can include a first semiconductor device, a second semiconductor device, and an external heat distribution layer. The first semiconductor device can comprise a first semiconductor die and an external surface comprising a top surface, a bottom surface, and a side surface joining the bottom surface to the tope surface. The second semiconductor device can comprise a second semiconductor die and can be stacked on the top surface of the first semiconductor device. The external heat distribution layer can cover an external surface of the second semiconductor device and the side surface of the first semiconductor device. The external heat distribution layer further contacts an internal heat distribution layer on a top surface of the first semiconductor die.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 10, 2019
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Bora Baloglu, Ron Huemoeller, Curtis Zwenger
  • Patent number: 10411217
    Abstract: An OLED device and a manufacturing method thereof and a display apparatus are provided. The OLED device includes an anode, a cathode, and a functional layer disposed between the anode and the cathode, the cathode includes an organometallic layer, and the organometallic layer includes an organic metal. The OLED device is capable of increasing the stability of the cathode in the OLED device and reducing the cost of the OLED device.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: September 10, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Fengwei Pei, Ziyi Zhao, Jinzhong Zhang, Ninghao Quan
  • Patent number: 10410966
    Abstract: Embedded resistors which have tunable resistive values located between interconnect levels are provided. The embedded resistors have a pillar structure, i.e., they have a height that is greater than their width, thus they occupy less real estate as compared with conventional planar resistors that are typically employed in BEOL technology.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Oscar van der Straten, Praneet Adusumilli
  • Patent number: 10403861
    Abstract: The present disclosure relates to a top-emissive organic light-emitting diode display. The organic light-emitting diode comprises a substrate, an auxiliary cathode, a passivation film, a planarization film, an under-cut opening, a connecting terminal, an under-area, a bank, an organic emission layer, and a cathode. The auxiliary cathode is placed on the substrate. The connecting terminal makes contact with the top surface of the one end exposed through the under-cut opening and protrudes into the under-cut opening, being longer in length than the one end of the auxiliary cathode. The under-area is formed between the end of the connecting terminal and the one end of the auxiliary cathode. The cathode is stacked on the organic emission layer, makes contact with the side of the connecting terminal not covered by the organic emission layer, and extends all the way to the under-area.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: September 3, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Jaesung Lee, Seungwon Yoo, Joonsuk Lee
  • Patent number: 10403810
    Abstract: A magnetic artificial honeycomb lattice comprising a multiplicity of connecting elements separated by hexagonal cylindrical pores, wherein: (a) the hexagonal cylindrical pores: (i) have widths that are substantially uniform and an average width that is in a range of about 15 nm to about 20 nm; and (ii) are substantially equispaced and have an average center-to-center distance that is in a range of about 25 nm to about 35 nm; and (b) the connecting elements comprise a magnetic material layer, and the connecting elements have: (i) lengths that are substantially uniform and an average length that is in a range of about 10 nm to about 15 nm; (ii) widths that are substantially uniform and an average width that is in a range of about 4 nm to about 8 nm; and (iii) a thickness of the magnetic material layer that is substantially uniform and an average thickness that is in a range of about 2 nm to about 8 nm; and (c) the magnetic artificial honeycomb lattice has a surface area, disregarding the presence of th
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: September 3, 2019
    Assignee: The Curators of the University of Missouri
    Inventors: Deepak Kumar Singh, Brock Summers, Ashutosh Dahal
  • Patent number: 10403549
    Abstract: A method for fabricating a semiconductor structure includes forming a plurality of initial fin structures on a substrate, each including a first region used as a first fin structure, a second region on the first region, and a third region on the second region; forming a first isolation layer on the substrate; removing each third region to form a first opening in the first isolation layer; forming a second isolation layer on sidewall surfaces of each first opening; and removing each second region to form an initial second opening; performing an etching process on the first isolation layer on sidewall surfaces of each initial second opening to form a second opening; forming a second fin structure in each first opening and the second opening; and removing a portion of the first isolation layer and the second isolation layer to expose a portion of sidewall surfaces of each second fin structure.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: September 3, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10396104
    Abstract: A display substrate is disclosed. The display device includes a first electrode, a second electrode, and a vertical storage capacitor in an insulating layer. The vertical storage capacitor includes a first plate and a second plate which are spaced apart. The first plate is connected with the first electrode, the second plate is connected with the second electrode, and the first plate and the second plate are perpendicular with or tilted with respect to the substrate. A method for fabricating the display substrate and a display device are also disclosed.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: August 27, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Pengfei Gu
  • Patent number: 10396214
    Abstract: Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10388591
    Abstract: According to an embodiment of a method for fabricating a trench field-effect transistor (trench FET), the method includes: the method includes: patterning a contact pad from a first metal layer situated over a surface of an active die; forming a dielectric layer over the contact pad; patterning the dielectric layer to form a plurality of dielectric islands spaced apart from one another by respective voids; and forming a second metal layer between and over the plurality of dielectric islands so as to substantially fill the respective voids. The contact pad, plurality of dielectric islands, and second metal layer provide the reliable and robust electrical contact.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: August 20, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Hugo Burke
  • Patent number: 10386687
    Abstract: A wire substrate, a display device including a wire substrate, and a method of fabricating a wire substrate are disclosed. The display device comprises: a first base; and a first wiring layer disposed on the first base and comprising a conductive metal layer and a metal oxide layer stacked on one another, wherein the metal oxide layer comprises MoxTayOz, wherein a content of tantalum is equal to or less than 2.0 at % (atomic percent) based on a total number of metal atoms.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 20, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chan Woo Yang, Hong Sick Park, Hyun Eok Shin, Joon Yong Park, Gyung Min Baek, Sang Won Shin, Ju Hyun Lee
  • Patent number: 10381368
    Abstract: A semiconductor memory device according to an embodiment comprises: when three directions intersecting each other are assumed to be first through third directions, and two directions intersecting each other in a plane extending in the first and second directions are assumed to be fourth and fifth directions, a memory cell array including: a conductive layer stacked in the third direction above a semiconductor substrate and having a first region; and a first columnar body penetrating the first region of the conductive layer in the third direction and including a semiconductor film, the first columnar body having a cross-section along the first and second directions in which, at a first position which is a certain position in the third direction, a length in the fourth direction is shorter than a length in the fifth direction.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: August 13, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kotaro Noda
  • Patent number: 10380494
    Abstract: A technique relates to a superconducting qubit. A Josephson junction includes a first superconductor and a second superconductor formed on a non-superconducting metal. A capacitor is coupled in parallel with the Josephson junction.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David W. Abraham, Josephine B. Chang, Jay M. Gambetta
  • Patent number: 10383232
    Abstract: A multilayer structure for an electronic device including a flexible substrate film for accommodating electronics; at least one electronic component provided on the substrate film; and a number of conductive traces provided on the substrate film for electrically powering and/or connecting electronics including the at least one electronic component, wherein at least one preferably thermoformed cover is attached to the substrate film on top of the at least one electronic component, the at least one thermoformed cover and the substrate film accommodating the electronics being overmolded with thermoplastic material. The invention also relates to a method for manufacturing a multilayer structure for an electronic device.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: August 13, 2019
    Assignee: TACTOTEK OY
    Inventors: Mikko Heikkinen, Jarmo Sääski, Jarkko Torvinen
  • Patent number: 10367045
    Abstract: Embodiments disclosed herein relate to an electroluminescence display device including a first electrode, a second electrode facing the first electrode, an emission layer between the first electrode and the second electrode, and a bank layer defining the emission layer. The bank layer may be disposed between the first electrode and the second electrode. The bank layer may include a first bank layer and a second bank layer. The second bank layer may include a black pigment. The first bank layer may be closer to the first electrode than the second bank layer, and the first bank layer may have a lower permittivity than the second bank layer.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: July 30, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Yeongyun Yang, Bonggeum Lee, WonKeun Park, Sohee Yu, Hanyoung Cho
  • Patent number: 10361247
    Abstract: A device including a plurality of interconnected concentric coplanar diodes.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: July 23, 2019
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Hubert Bono, Jonathan Garcia
  • Patent number: 10361125
    Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, patterning the hardmask layer to form a plurality of patterned hardmask portions on the substrate, depositing a dummy hardmask layer on the substrate, patterning the dummy hardmask layer to form a plurality of patterned dummy hardmask portions on the substrate, wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions to the substrate to form a plurality of fins and a plurality of dummy fins from the substrate.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Peng Xu, Kangguo Cheng, Yann Mignot, Choonghyun Lee
  • Patent number: 10361297
    Abstract: A semiconductor epitaxial wafer includes a semiconductor wafer, and a semiconductor layer of a first conductivity type disposed on a main surface of the semiconductor wafer. The semiconductor epitaxial wafer includes a plurality of device regions. The plurality of device regions each include a body region of a second conductivity type in contact with the semiconductor layer, a source region of the first conductivity type in contact with the body region, and a channel layer that is constituted by a semiconductor, and that is disposed on the semiconductor layer so as to be in contact with at least a part of the body region. In a plane parallel to the main surface of the semiconductor wafer, a thickness distribution in the channel layer and a concentration distribution of the first conductivity type impurity in the channel layer are negatively correlated to each other.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: July 23, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Tsutomu Kiyosawa
  • Patent number: 10347486
    Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate, the patterning material film stack including a resist layer formed over one or more additional layers, and forming a metal-containing top coat over the resist layer. The method further includes exposing the multi-layer patterning material film stack to patterning radiation through the metal-containing top coat to form a desired pattern in the resist layer, removing the metal-containing top coat, developing the pattern formed in the resist layer, etching at least one underlying layer in accordance with the developed pattern, and removing remaining portions of the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ekmini Anuja De Silva, Dario Goldfarb, Nelson Felix, Daniel Corliss, Rudy J. Wojtecki
  • Patent number: 10347726
    Abstract: A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion. A plug spacer film is between the insulating layer and at least one of the first lower portion and the second lower portion and includes a material different from a material of the insulating layer.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: July 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Deok Han Bae, Hyung Jong Lee, Hyun Jin Kim
  • Patent number: 10332796
    Abstract: A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second plurality of fin structures having a second width in a second region of the substrate, the second width being less than the first width. A first gate structure is formed on the first plurality of fin structures including a first high-k gate dielectric that is in direct contact with a channel region of the first plurality of fin structures and a first gate conductor. A second gate structure is formed on the second plurality of fin structures including a high voltage gate dielectric that is in direct contact with a channel region of the second plurality of fin structures, a second high-k gate dielectric and a second gate conductor.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang