Patents Examined by Ngan V. Ngo
  • Patent number: 10636779
    Abstract: The present disclosure provides a packaging device for an integrated power supply system and a packaging method thereof. The packaging device comprises: a power consumption system die and a power supply system die below the power consumption system die; the power supply system die comprises an active module, a passive module and a rewiring layer, wherein the active module and the reactive module are molded, and the rewiring layer is located above the molded active module and passive module, to connect the active module and the passive module, and a plurality of power supply tracks are disposed in the rewiring layer to abut the power consumption system die; the power consumption system die is abutted with the plurality of power supply tracks; and an external power source supplies power to the power consumption system die through the power supply system die.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: April 28, 2020
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Jangshen Lin, Chengchung Lin, Chihhung Ho, Qifeng Cai
  • Patent number: 10636851
    Abstract: An embodiment provides a display device including an insulating layer which is continuous between opposed ends of two adjacent lower electrodes from an upper part of one of the ends to an upper part of the other end, a first organic layer which is disposed over the lower electrodes and the insulating layer, a second organic layer which is disposed over the lower electrodes and the insulating layer with the first organic layer interposed therebetween and includes a light emitting layer, and a second electrode which covers the organic layer. The upper face of the insulating layer includes a recess between the two lower electrodes. The aspect ratio of the recess is 0.5 or more.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: April 28, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventor: Nobutaka Ukigaya
  • Patent number: 10636748
    Abstract: A package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Jing-Cheng Lin, Tsei-Chung Fu
  • Patent number: 10629517
    Abstract: A semiconductor device including a connection terminal that is electrically connected to a semiconductor chip, a bus bar with an opening through which the connection terminal passes, and a fusing portion including a jointing portion, which is provided over an upper surface of the bus bar from an upper part of the connection terminal that is positioned above the upper surface of the bus bar by making the connection terminal pass through the opening of the bus bar, is provided.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: April 21, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Koji Ichikawa, Kento Shirata
  • Patent number: 10626007
    Abstract: In accordance with an embodiment, a microelectromechanical transducer includes a displaceable membrane having an undulated section comprising at least one undulation trough and at least one undulation peak and a plurality of piezoelectric unit cells. At least one piezoelectric unit cell is provided in each case in at least one undulation trough and at least one undulation peak, where each piezoelectric unit cell has a piezoelectric layer and at least one electrode in electrical contact with the piezoelectric layer. The membrane may be formed as a planar component having a substantially larger extent in a first and a second spatial direction, which are orthogonal to one another, than in a third spatial direction, which is orthogonal to the first and the second spatial direction and defines an axial direction of the membrane.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: April 21, 2020
    Assignee: Infineon Technologies AG
    Inventors: Christian Bretthauer, Alfons Dehe, Alfred Sigl
  • Patent number: 10622551
    Abstract: A method for forming a semiconductor device is provided. The method includes: providing a semiconductor substrate; forming a bottom electrode layer over the semiconductor substrate; forming a magnetic tunneling junction (MTJ) layer over the bottom electrode layer; forming a top electrode layer over the MTJ layer; and performing a single etch operation to etch the bottom electrode layer, the MTJ layer, and the top electrode layer, thereby forming a bottom electrode, a MTJ, and a top electrode respectively.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: April 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih-Wei Lu, Chung-Ju Lee
  • Patent number: 10615200
    Abstract: Disclosed are image sensors and methods of fabricating the same. The image sensor includes a semiconductor substrate including a pixel zone and a pad zone and having a first surface and a second surface opposing each other, a first pad separation pattern on the pad zone and extending from the first surface of the semiconductor substrate toward the second surface of the semiconductor substrate, a second pad separation pattern extending from the second surface toward the first surface of the semiconductor substrate on the pad zone the second pad and in contact with the first pad separation pattern, and a pixel separation pattern on the pixel zone and extending from the second surface of the semiconductor substrate toward the first surface of the semiconductor substrate.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: April 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Changkeun Lee
  • Patent number: 10607947
    Abstract: A semiconductor device includes a metallization system positioned above a substrate and a die seal positioned at least in the metallization system and delimiting a die region. The die seal includes a via line feature having an axial length and including one or more first portions having a first target dimension and one or more second portions along the axial length. The one or more second portions have a second target dimension less than the first target dimension.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: March 31, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Dirk Breuer, Maik Liebau, Matthias Lehr
  • Patent number: 10607972
    Abstract: A semiconductor device includes an active region disposed in a semiconductor substrate and an uppermost metal level including metal lines, where the uppermost metal level is disposed over the semiconductor substrate. Contact pads are disposed at a major surface of the semiconductor device, where the contact pads are coupled to the metal lines in the uppermost metal level. An isolation region separates the contact pads disposed at the major surface. Adjacent contact pads are electrically isolated from one another by a portion of the isolation region. Reflective structures are disposed between the upper metal level and the contact pads, where each of the reflective structures that is directly over the active region completely overlaps an associated portion of the isolation region separating the contact pad.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: March 31, 2020
    Assignee: Infineon Technologies AG
    Inventors: Dietrich Bonart, Bernhard Weidgans, Johann Gatterbauer, Thomas Gross, Martina Heigl
  • Patent number: 10600883
    Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by introducing a threshold voltage modifying dopant into a physically exposed portion of a metal gate layer composed of an n-type workfunction TiN. The threshold voltage modifying dopant changes the threshold voltage of the original metal gate layer.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Takashi Ando, Jingyun Zhang, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10600915
    Abstract: A flexible substrate structure including a flexible substrate, a first dielectric layer, a metal-containing layer and a second dielectric layer is provided. The first dielectric layer is located on the flexible substrate. The metal-containing layer has a reflectivity greater than 15% and a heat transfer coefficient greater than 2 W/m-K. The metal-containing layer is disposed between the first dielectric layer and the second dielectric layer, and the second dielectric layer is an inorganic material layer. A flexible transistor including the above-mentioned flexible substrate structure and a method for fabricating the same are also provided.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: March 24, 2020
    Assignee: National Applied Research Laboratories
    Inventors: Wen-Hsien Huang, Jia-Min Shieh, Chang-Hong Shen
  • Patent number: 10593480
    Abstract: A chip capacitor according to the present invention includes a substrate, a pair of external electrodes formed on the substrate, a capacitor element connected between the pair of external electrodes, and a bidirectional diode connected between the pair of external electrodes and in parallel to the capacitor element. Also, a circuit assembly according to the present invention includes the chip capacitor according to the present invention and a mounting substrate having lands, soldered to the external electrodes, on a mounting surface facing a front surface of the substrate.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: March 17, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Hiroki Yamamoto, Keishi Watanabe, Hiroshi Tamagawa
  • Patent number: 10593769
    Abstract: A method of manufacturing a semiconductor device includes forming a base layer in an upper part of a substrate and a trench in the substrate. A gate insulating film is on an inner bottom surface and an inner side surface of the trench and a gate electrode is embedded into the trench. The gate electrode is etched so that an upper surface of the gate electrode is at a first height from the bottom of the trench. A source region is in contact with an outer side surface of the trench. A base contact region is in contact with part of the outer side surface of the trench, an upper part of the base layer, and an upper part of the source region. A source electrode is embedded in a remaining part of the trench and in contact with the source region and the base contact region.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: March 17, 2020
    Assignee: ABLIC INC.
    Inventors: Yuki Osuga, Hirofumi Harada
  • Patent number: 10584924
    Abstract: A heat sink includes a first fin and a second fin. The spacing between the first fin and the second fin may be adjusted by a threaded rod. The threaded rod includes a first portion that is engaged with the first fin and a second portion that is engaged with the second fin. The thread pitch of the first portion and the second portion may differ. For example, the pitch of a first internal thread of the first fin may be smaller than the pitch of a second internal thread of the second fin. The spacing of the heat sink fins may be adjusted based upon the current operating conditions of the electronic device to maintain an optimal temperature of a heat generating device during device operation.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Paul F. Bodenweber, Kamal K. Sikka
  • Patent number: 10586811
    Abstract: In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: March 10, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshikazu Kondo, Hideyuki Kishida
  • Patent number: 10580846
    Abstract: A display apparatus includes a display region and a peripheral region adjacent to the display region. The display apparatus further includes a first flexible substrate (FFS), a driving circuit (DC), a conductive pattern (CP), a conductive line, a light-emitting device, and a support substrate. The FFS includes a first surface and a second surface opposite the first surface. The second surface includes, in the peripheral region, a cavity extending into the FFS. The DC is on the first surface and includes at least one transistor. The CP is in the cavity and is partially exposed by the cavity. The conductive line electrically connects the CP to the DC. The light-emitting device is in the display region and is electrically connected to the DC. The support substrate is on the second surface. In a view normal to the second surface, the support substrate is spaced apart from the CP.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: March 3, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kiseong Seo, Jekil Ryu, Wonkyu Choe, Jungho Choi, Mugyeom Kim, Changyong Jeong
  • Patent number: 10573739
    Abstract: A method of producing a semiconductor device including steps (A) and (B). Step (A) is preparing a semiconductor epitaxial wafer including a plurality of device regions, each including a body region contacting a semiconductor layer. Step (B) is forming a channel layer contacting at least a part of the body region by epitaxial growth of a semiconductor on a surface of the semiconductor layer. The channel layer contains an impurity at a concentration ranging from 1×1018 cm?3 to 1×1019 cm?3, inclusive, and has a thickness ranging from 10 nm to 100 nm, inclusive. In the step (B), a condition for the epitaxial growth is controlled so that, in a plane parallel to the main surface of the semiconductor wafer, a thickness distribution in the channel layer and a concentration distribution of the impurity in the channel layer are negatively correlated to each other.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: February 25, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Tsutomu Kiyosawa
  • Patent number: 10573740
    Abstract: A method of producing a semiconductor device includes the following steps (A), (B), and (C). In the step (A), a semiconductor epitaxial wafer is prepared. The semiconductor epitaxial wafer includes a body region. In the step (B), a channel layer is formed by epitaxial growth. In the step (C), a gate insulation film is formed on the channel layer. The channel layer contains impurity at a concentration ranging from 1×1018 cm?3 to 1×1019 cm?3, inclusive, and has a thickness ranging from 10 nm to 100 nm, inclusive. In the steps of (B) and (C), a condition for the epitaxial growth and a condition for forming the gate insulation film are controlled so that a thickness distribution in the channel layer and a thickness distribution in the gate insulation film are positively correlated to each other.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 25, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Tsutomu Kiyosawa
  • Patent number: 10566299
    Abstract: Method for manufacturing a multi-band antenna package structure includes providing a first temporary substrate; forming a first dielectric material layer, and first metal patterns; forming at least one metal via; forming at least one metal pillar, and disposing an integrated circuit chip; forming a molding layer; thinning down the molding layer thus forming an integrated circuit chip layer; forming a first redistribution layer; forming a first antenna unit layer; forming a first protection layer, thus a first stacked structure formed; removing the first temporary substrate, and facing down the first stacked structure to adhere it on a second temporary substrate with a second glue layer; forming a second redistribution layer; forming a second protection layer; forming bump balls, thus a second stacked structure formed; removing the second temporary substrate with the second glue layer, facing down and mounting the second stacked structure on a substrate through the bump balls.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: February 18, 2020
    Assignee: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Ching-Wen Chiang, Yen-Cheng Kuan, Chia-Jen Liang, Chien-Te Yu
  • Patent number: 10566498
    Abstract: A semiconductor light-emitting device comprises an epitaxial structure comprising an main light-extraction surface, a lower surface opposite to the main light-extraction surface, a side surface connecting the main light-extraction surface and the lower surface, a first portion and a second portion between the main light-extraction surface and the first portion, wherein a concentration of a doping material in the second portion is higher than that of the doping material in the first portion and, in a cross-sectional view, the second portion comprises a first width near the main light-extraction surface and second width near the lower surface, and the first width is smaller than the second width.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: February 18, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Hsin-Chih Chiu, Shih-I Chen, You-Hsien Chang, Hao-Min Ku, Ching-Yuan Tsai, Kuan-Chih Kuo, Chih-Hung Hsiao, Rong-Ren Lee