Abstract: According to an embodiment, a light-emitting device is disclosed. The disclosed light-emitting device comprises: a substrate having a body and first and second lead electrodes on the body; a light-emitting chip arranged on the second lead electrode and electrically connected to the first and second lead electrodes; a phosphor film arranged on the light-emitting chip; a reflective member arranged on the outer peripheries of the light-emitting chip and the phosphor film, respectively; and an optical lens, which is arranged on the phosphor film and on the reflective member, and which has a lens portion that has an aspherical shape.

Abstract: A semiconductor light emitting device comprising a light emitting layer disposed between an n-type region and a p-type region is combined with a ceramic layer which is disposed in a path of light emitted by the light emitting layer. The ceramic layer is composed of or includes a wavelength converting material such as a phosphor. Luminescent ceramic layers according to embodiments of the invention may be more robust and less sensitive to temperature than prior art phosphor layers. In addition, luminescent ceramics may exhibit less scattering and may therefore increase the conversion efficiency over prior art phosphor layers.

Abstract: Embodiments of the present disclosure relate to an integrated circuit (IC) package, including a molding compound positioned on a first die and laterally adjacent to a stack of dies positioned on the first die. The stack of dies electrically couples the first die to an uppermost die, and a thermally conductive pillar extends through the molding compound from the first die to an upper surface of the molding compound. The thermally conductive pillar is electrically isolated from the stack of dies and the uppermost die. The thermally conductive pillar laterally abuts and contacts the molding compound.

Abstract: A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.

Abstract: A semiconductor device includes: a drain region formed on a rear surface side of a substrate; a base layer formed between the drain region and a front surface of the substrate; a trench formed in the substrate; a gate insulating film covering an inner surface of the trench from a bottom of the trench to a first height; a gate electrode filling the trench to the first height; an insulating film filling the trench to a second height higher than the first height; a source electrode filling a remaining part of the trench; a base contact region formed in a surface of the substrate and has one side contacting the source electrode; and a source region having an upper surface contacting a part of a bottom surface of the base contact region, one side contacting a side of the trench and is partially contacting the source electrode.

Abstract: This disclosure relates to a display device including a lens array unit. An exemplary embodiment of the present inventive concept provides a display device including: a display unit including a plurality of pixels; and a lens array unit including a plurality of lenses, wherein a first lens of the plurality of lenses corresponds to and overlaps two or more of the plurality of pixels, the two or more pixels include a first pixel and a second pixel, the first pixel is closer to an optical axis of the first lens than the second pixel is in a plan view, and a shortest distance between the first pixel and a reference surface that is perpendicular to the optical axis of the first lens is greater than a shortest distance between the reference surface and the second pixel.

Abstract: A technique relates to a superconducting qubit. A Josephson junction includes a first superconductor and a second superconductor formed on a non-superconducting metal. A capacitor is coupled in parallel with the Josephson junction.

Abstract: A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second plurality of fin structures having a second width in a second region of the substrate, the second width being less than the first width. A first gate structure is formed on the first plurality of fin structures including a first high-k gate dielectric that is in direct contact with a channel region of the first plurality of fin structures and a first gate conductor. A second gate structure is formed on the second plurality of fin structures including a high voltage gate dielectric that is in direct contact with a channel region of the second plurality of fin structures, a second high-k gate dielectric and a second gate conductor.

Abstract: Disclosed in an embodiment is a light emitting device comprising: a light-emitting structure having a first semiconductor layer, an active layer under the first semiconductor layer, and a second semiconductor layer under the active layer; a first contact layer disposed under the light-emitting structure; a reflective layer disposed under the first contact layer; a first electrode layer including a capping layer disposed under the reflective layer; a second electrode layer electrically connected with the first semiconductor layer; a protective layer disposed at the outer peripheral portion between the capping layer and the light-emitting structure; a barrier layer at an outer side of the reflective layer and made of a metal different from that of the reflective layer; and a support member disposed under the capping layer.

Abstract: A hydrogen sensor can include a substrate, an Ohmic metal disposed on the substrate, a nitride layer disposed on the substrate and having a first window exposing the substrate, a Schottky metal placed in the first window and disposed on the substrate, a final metal disposed on the nitride layer and the Schottky metal and having a second window exposing the Schottky metal, and a polymethyl-methacrylate (PMMA) layer encapsulating the second window. The PMMA layer can fill the second window and be in contact with the Schottky metal.

Abstract: An object is to provide an imaging device with high efficiency of transferring charge corresponding to imaging data. The imaging device includes first to fifth conductors, first and second insulators, an oxide semiconductor, a photoelectric conversion element, and a transistor. The first conductor is in contact with a bottom surface and a side surface of the first insulator. The first insulator is in contact with a bottom surface of the oxide semiconductor. The oxide semiconductor is in contact with bottom surfaces of the second and third conductors and the second insulator. Each of the second and third conductors is in contact with the bottom surface and a side surface of the second insulator. The second insulator is in contact with bottom surfaces of the fourth and fifth conductors. The first conductor has regions overlapped by the fourth and fifth conductors. The second conductor has a region overlapped by the fourth conductor. The third conductor has a region overlapped by the fifth conductor.

Abstract: An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.

Abstract: A diode including a vertical stack of first and second semiconductor regions having opposite conductivity types, and a first electrode for biasing its first region arranged in a trench extending from the surface of the second region opposite to the first region, the first electrode including, in top view, the following conductive elements: a polygonal ring; for each vertex of the polygonal ring, a first rectilinear bar extending between the vertex and the center of the ring, substantially along a direction running from the vertex to the center of the ring; and for each first bar, a plurality of second rectilinear bars extending from the first bar substantially parallel to the sides of the ring, starting from the vertex forming the origin of the first bar.

Abstract: A semiconductor device with three transistors of same conductive type but different threshold voltage is provided in the present invention, wherein the first transistor includes a high-k dielectric layer, a first bottom barrier metal layer, a second bottom barrier metal layer, a work function metal layer and a low resistance metal. The second transistor includes the high-k dielectric layer, the first bottom barrier metal layer, the second bottom barrier metal layer and the low resistance metal, and a third transistor on the substrate. The third transistor includes the high-k dielectric layer, the first bottom barrier metal layer and the low resistance metal.

Abstract: A method for manufacturing a solar cell comprises forming a first conductivity-type silicon-based thin-film on a first surface of a substrate; forming a second conductivity-type silicon-based thin-film different from the first conductivity-type silicon-based thin-film, on a second surface of the substrate that is opposite to the first surface of the substrate; forming a first transparent electrode layer on the first conductivity-type silicon-based thin-film; and forming a second transparent electrode layer on the second conductivity-type silicon-based thin-film; forming a first metal seed layer on a first transparent electrode layer; forming a second metal seed layer on a second transparent electrode layer; forming a third metal seed layer on a peripheral edge and on an end-edge of the second conductivity-type silicon-based thin-film; forming a first plating layer on the first metal seed layer and a third plating layer on the third metal seed layer simultaneously by an electroplating method.

Abstract: An imaging device having a pixel array in which one plate of a storage capacitor is coupled to a storage node while another plate is formed by an electrode of a photo-conversion region.

Abstract: A field effect transistor (FET) includes a trench extending into a silicon region of a first conductive type. A shield insulated from the silicon region by a shield dielectric extends in a lower portion of the trench. A gate electrode is in the trench over but insulated from the shield electrode by an inter-poly dielectric (IPD). The IPD comprises a conformal layer of dielectric and a thermal oxide layer.

Abstract: A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method making is described. The multilayered doped conductor creates a high dopant concentration in the active area close to the channel region. The rich dopant layer created by the multilayered doped conductor is less susceptible to depletion from trapped charges in the oxide. This improves device reliability at burn-in and lowers junction leakage, thereby providing a longer period between refresh cycles.

Abstract: A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.

Abstract: A nonvolatile semiconductor memory device including a memory cell and a selection transistor, and the memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in the substrate, first and second control gates formed on the opposite sides of the floating gate to drive the floating gate, and an inter-gate insulation film formed between the first and second control gates and the floating gate. The selection transistor includes a selection gate formed on the substrate via a second gate insulation film, and a pair of second diffusion layers formed in the substrate positioned on the opposite sides of the selection gate and one of which is electrically connected to one of the pair of first diffusion layers.