Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

Abstract: A color conversion element includes a base substrate, and a first color filter layer, a second color conversion layer, and a third color conversion layer disposed on the base substrate, wherein the first color filter layer, the second color conversion layer, and the third color conversion layer are sequentially arranged on a plane, and wherein an interval between the first color filter layer and the second color conversion layer or an interval between the first color filter layer and the third color conversion layer is different from an interval between the second color conversion layer and the third color conversion layer.

Abstract: Provided is a cooler including an upper plate configured to have a semiconductor chip to be arranged thereon, a plurality of plate-like fins arranged under the upper plate, and a coupling bar coupled to the plate-like fins. The coupling bar has a main-body portion and a plurality of comb-tooth portions protruding from the main-body portion into the flow channel, the cooler includes a plurality of openings in a plane orthogonal to an extending direction of the plate-like fins, and the openings are defined at least by the comb-tooth portions and the plate-like fins, and the openings include a first opening provided in a first flow channel that does not run below the semiconductor chip, and a second opening provided in a second flow channel that runs below the semiconductor chip, where the second opening is larger than the first opening.

Abstract: A method of manufacturing a bipolar junction transistor (BJT) structure is provided. Pattern etching through a second semiconductor layer and recessing a silicon germanium layer are performed to form a plurality of vertical fins each including a silicon germanium pattern, a second semiconductor pattern and a hard mask pattern sequentially stacked on a first semiconductor layer above a substrate. First spacers are formed on sidewalls of the plurality of vertical fins. Exposed silicon germanium layer above the first semiconductor layer is directionally etched away. A germanium oxide layer is conformally coated to cover all exposed top and sidewall surfaces. Condensation annealing followed by silicon oxide strip is performed. The first spacers, remaining germanium oxide layer and the hard mask pattern are removed. A dielectric material is deposited to isolate the plurality of vertical fins.

Abstract: A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

Abstract: A display apparatus includes a first clock line providing a first clock signal and a second clock line providing a second clock signal. The first clock line includes a first main clock line and a first dummy clock line extending from the first main clock line, the second clock line includes a second main clock line and a second dummy clock line extending from the second main clock line, and the first dummy clock line and the second dummy clock line have different areas from each other.

Abstract: A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising longitudinally extending, columnar grains of crystalline material, an ion reservoir material over the buffer material, and a second electrode over the ion reservoir material. A memory cell, a memory device, an electronic system, and a method of forming a resistive memory element are also described.

Abstract: A static random-access memory (SRAM) device includes a base substrate including a PU transistor region and a PD transistor region adjacent to the PU transistor region, a gate dielectric layer formed on a portion of the base substrate in the PU transistor region and the PD transistor region, a first WF layer formed on a portion of the gate dielectric layer in the PU transistor region and a second WF layer formed on the first WF layer in the PU transistor region, and a third WF layer formed on a top surface and a sidewall surface of the second WF layer in the PU transistor region, a sidewall surface of the first WF layer in the PU transistor region, and the gate dielectric layer in the PD transistor region. Each of the first WF layer and the second WF layer is made of a P-type WF material, and the third WF layer is made of an N-type WF material. The SRAM device also includes a gate electrode layer formed on the third WF layer.

Abstract: An IGBT having a barrier region is presented. A power unit cell of the IGBT has at least two trenches that may both extend into the barrier region. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by means of the drift region. The barrier region can be electrically floating.

Abstract: The present disclosure is directed to quantum dots comprising a core-shell structure and a novel arrangement of ligands thereon. Light emitting diodes including the quantum dots, light emitting devices including the same as well as methods associated with preparation and use of such compounds and devices are also provided.

Abstract: A semiconductor device includes a first transistor in a first region and a second transistor in a second region. The first transistor includes: a first nanowire, a first gate electrode, a first gate dielectric layer, a first source/drain region, and an inner-insulating spacer. The first nanowire has a first channel region. The first gate electrode surrounds the first nanowire. The first gate dielectric layer is between the first nanowire and the first gate electrode. The first source/drain region is connected to an edge of the first nanowire. The inner-insulating spacer is between the first gate dielectric layer and the first source/drain region. The second transistor includes a second nanowire, a second gate electrode, a second gate dielectric layer, and a second source/drain region. The second nanowire has a second channel region. The second gate electrode surrounds the second nanowire. The second gate dielectric layer is between the second nanowire and the second gate electrode.

Abstract: Semiconductor packages and methods of manufacturing semiconductor packages are described herein. In certain embodiments, the semiconductor package includes a housing including a first compartment and a second compartment, the first and second compartments being divided from one another. The semiconductor package can also include an integrated device die disposed in the first compartment, and a radio frequency (RF) absorber disposed in the second compartment.

Abstract: A multi-band antenna package structure includes a first redistribution layer; an integrated circuit layer, formed on the first redistribution layer, comprising at least one metal via, at least one metal pillar, an integrated circuit chip, and a molding layer, wherein the molding layer is used to fill openings formed by the metal via, the metal pillar and the integrated circuit chip which are disposed on the first redistribution layer, the metal via is electrically connected to one of the first metal patterns of the first redistribution layer; a second redistribution layer, formed on the integrated circuit layer; and a first antenna unit layer, comprising a first dielectric layer and third metal patterns formed in openings of the first dielectric layer, wherein at least one of the third metal patterns is electrically connected to one of the second metal patterns, and the third metal patterns form a first antenna unit.

Abstract: In accordance with at least one embodiment of the invention, a transistor comprises a semiconductor, a first drift layer, a drain region, a body region, a source region, a shallow trench isolation region, a dielectric, and a gate. The first drift layer is formed in the semiconductor and has majority carriers of a first type. The drain region is formed in the first drift layer and has majority carriers of the first type. The body region is formed in the semiconductor and has majority carriers of a second type. The source region is formed in the body region and has majority carriers of the first type. The shallow trench isolation region is formed in the first drift layer and disposed between the drain region and the body region. The dielectric is formed on the semiconductor, and the gate is formed over the dielectric and has a lift-up region.

Abstract: An OLED device and a manufacturing method thereof and a display apparatus are provided. The OLED device includes an anode, a cathode, and a functional layer disposed between the anode and the cathode, the cathode includes an organometallic layer, and the organometallic layer includes an organic metal. The OLED device is capable of increasing the stability of the cathode in the OLED device and reducing the cost of the OLED device.

Abstract: A semiconductor package having an internal heat distribution layer and methods of forming the semiconductor package are provided. The semiconductor package can include a first semiconductor device, a second semiconductor device, and an external heat distribution layer. The first semiconductor device can comprise a first semiconductor die and an external surface comprising a top surface, a bottom surface, and a side surface joining the bottom surface to the tope surface. The second semiconductor device can comprise a second semiconductor die and can be stacked on the top surface of the first semiconductor device. The external heat distribution layer can cover an external surface of the second semiconductor device and the side surface of the first semiconductor device. The external heat distribution layer further contacts an internal heat distribution layer on a top surface of the first semiconductor die.

Abstract: Embedded resistors which have tunable resistive values located between interconnect levels are provided. The embedded resistors have a pillar structure, i.e., they have a height that is greater than their width, thus they occupy less real estate as compared with conventional planar resistors that are typically employed in BEOL technology.

Abstract: A method for fabricating a semiconductor structure includes forming a plurality of initial fin structures on a substrate, each including a first region used as a first fin structure, a second region on the first region, and a third region on the second region; forming a first isolation layer on the substrate; removing each third region to form a first opening in the first isolation layer; forming a second isolation layer on sidewall surfaces of each first opening; and removing each second region to form an initial second opening; performing an etching process on the first isolation layer on sidewall surfaces of each initial second opening to form a second opening; forming a second fin structure in each first opening and the second opening; and removing a portion of the first isolation layer and the second isolation layer to expose a portion of sidewall surfaces of each second fin structure.

Abstract: The present disclosure relates to a top-emissive organic light-emitting diode display. The organic light-emitting diode comprises a substrate, an auxiliary cathode, a passivation film, a planarization film, an under-cut opening, a connecting terminal, an under-area, a bank, an organic emission layer, and a cathode. The auxiliary cathode is placed on the substrate. The connecting terminal makes contact with the top surface of the one end exposed through the under-cut opening and protrudes into the under-cut opening, being longer in length than the one end of the auxiliary cathode. The under-area is formed between the end of the connecting terminal and the one end of the auxiliary cathode. The cathode is stacked on the organic emission layer, makes contact with the side of the connecting terminal not covered by the organic emission layer, and extends all the way to the under-area.