Abstract: A charger includes an output circuit unit to output a charging current to a secondary battery, a voltage detection unit to detect a voltage of the secondary battery, and a control unit to control the output circuit unit, whereby constant current charging and constant voltage charging are performed. The control unit decreases a constant current value of the charging current by stages during the constant current charging and determines that the secondary battery has deteriorated by using a first voltage drop value of the secondary battery occurring upon first conversion and a second voltage drop value of the secondary battery occurring upon second conversion.

Abstract: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation.

Abstract: When a timer charge time zone is set by a timer charge reservation means for allowing a user to designate a predetermined timer charge time zone and a target charge amount, and timer charge is carried out from a timer charge start time previously designated, it is judged whether or not the timer charge start time should be advanced, at a time earlier by a predetermined time period than the timer charge start time. Owing to the judgment, charge of a battery can be completed at a predetermined time without enhancing a required capacity of a heater.

Abstract: This disclosure describes a multi-height routing cell and utilization of the multi-height routing in an integrated circuit to reduce routing congestion in a standard cell design floorplan. The multi-height routing cell includes a bypass connection, or “tunnel,” that routes a signal through a non-routing layer and under an impeding power rail. The multi-height routing cell includes bypass connectors on both sides of the bypass connection that provide connection points for which to connect standard cells on opposite sides of the impeding power rail. As such, the multi-height routing cell provides a route underneath the impeding power rail and, in turn, reducing routing congestion in the standard cell design floorplan.

Abstract: A system and method for managing energy of an electric vehicle are provided to calculate a necessary amount of energy based on battery characteristics and a user's schedule, and control charging and discharging of the electric vehicle using power information provided by a smart grid. The system includes a cloud server configured to collect a schedule from a user and store and generate the user's schedule information, an energy management device configured to calculate necessary energy based on the received schedule information of the user, set charging information based on power network state information received from a power supplier and the calculated necessary energy, generate a charging request signal based on the set charging information, and store electric energy, and a charging unit configured to transfer the electric energy to the energy management device based on the received charging request signal.

Abstract: A charging device and associated electrical appliances are provided. More than one electronic device can be charged simultaneously, with a wireless charging option available. Thus, the user has greater flexibility in selecting the desired charging option. Each associated appliance has a receiving compartment to hold the charging device, and the receiving compartment is configured with at least one first terminal. The charging device has at least one electrical interface for cable connection, a wireless charging transmitter, and at least one second terminal for mating electrically to the first terminal.

Abstract: A charge control device is configured to delay a charge suspension time if a battery is being heated by a battery heater when carrying out a timed charge in a charge time slot specified by a user via an interface device. This enables the battery to be charged to a target charge amount without increasing a required capacity of the battery heater.

Abstract: A method for a rechargeable battery is disclosed that includes applying a charge voltage to the rechargeable battery; monitoring a battery voltage and a battery current of the rechargeable battery; and identifying a top of charge condition when for a defined time period the battery voltage is within a voltage tolerance of the charge voltage and the battery current is within a current tolerance of a threshold current. Also disclosed is a rechargeable battery system.

Abstract: For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.

Abstract: A system, method, and computer program product for using continuous parameter value updates to rapidly evaluate parameterized cells in a design tool. Embodiments display parameters and corresponding parameter values of parameterized cells in a circuit design in a GUI, adjust parameter values according to user input, evaluate the parameterized cell, and present results of the evaluating in the GUI during the displaying. Parameters influence circuit layout, circuit schematics, or simulation settings. Parameter values include current, minimum, maximum, and increment values. Parameterized cells may be individual cell instances, submaster cells, or master cells. Embodiments integrate validation tools and detect design rule check violations, assertion violations, invalid parameter values, and evaluation errors, and responsively generate user error alerts and selectively disallow further adjusting. Embodiments generate test circuits, each using a parameter value from a permutation of the adjusted parameter values.

Abstract: Methods, system and apparatus are provided for securing a rechargeable electronic device with respect to a surface of a wireless battery charging apparatus of a vehicle.

Abstract: A push-pull circuit comprising: a push-pull first switching element and second switching element; a first rectifier element; a third switching element for switching a pathway between conductance and cutoff, the pathway leading from a connection point between the first switching element and an inductive load via the first rectifier element to a connection point between a DC power source and a center tap of the inductive load; a second rectifier element; and a fourth switching element for switching a pathway between conductance and cutoff, the pathway leading from a connection point between the second switching element and the inductive load via the second rectifier element to a connection point between the DC power source and the center tap of the inductive load.

Abstract: Methods, layouts and chip design layouts that use annotations for communicating gate-length biasing amounts to post-layout tools are disclosed. One method includes receiving a chip design layout designed to includes select ones of a plurality of nominal cell layouts and an annotated cell layout. The chip design layout is defined by a plurality of layers and the plurality of nominal cell layouts define transistors, wherein each of the plurality of nominal cell layouts define nominal length transistors, and the annotated cell layout also defines transistors. The annotated cell layout is associated with an annotation layer that identifies a gate-length biasing to be applied to at least one transistor of the annotated cell layout. The gate-length biasing identifies an amount of change for a gate length and not width-sizing of a gate width of the at least one transistor of the annotated cell layout. The annotation layer is used to communicate design-specific directives that require implementation.

Abstract: One embodiment provides a charge/discharge determination apparatus for performing a charge/discharge control of a battery based on instructions given from charge/discharge instruction apparatuses, including: a battery information storage unit which stores battery information concerned with the battery; a charge/discharge information storage unit which stores charge/discharge information for charging/discharging the battery; a communication unit which receives a communication message concerned with an access request from each charge/discharge instruction apparatus; and a control unit which controls access from each charge/discharge instruction apparatus based on the battery information, the charge/discharge information and contents of the access request.

Abstract: Described herein are systems and methods for a partitioned extraction-simulation technique that efficiently combines a partitioned extraction technique and a partitioned simulation technique by removing and not performing particular steps of the techniques to provide a more efficient netlist extraction and circuit simulation process. In some embodiments, a plurality of circuit simulators directly receive and process a plurality of sub-region netlists that are based on a spatial partitioning of the IC layout. In further embodiments, an EDA hybrid cloud system is implemented using pipelining and serializing of memory data. In these embodiments, an overall EDA process is divided into a plurality of pipelined stages to accelerate the computational speed of the overall EDA process. In further embodiments, EDA data is transferred, over a network, from a memory of one computer system directly to a memory of another computer system by serializing the EDA data.

Abstract: A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks.

Abstract: A technique for determining whether an integrated circuit design is susceptible to glitches includes identifying storage elements in an original register-transfer level (RTL) file of the integrated circuit design and identifying clock signals for each of the storage elements in the original RTL file. The technique also includes generating respective assertions for each of the identified clock signals and identifying potential glitchy logic in respective clock paths for each of the identified clock signals. Finally, the technique includes inserting, at the potential glitchy logic, glitches in each of the respective clock paths of the original RTL file to provide a modified RTL file and executing an RTL simulation using the modified RTL file and the respective assertions.

Abstract: A method of patterning a plurality of layers of a work piece in a series of writing cycles in one or a plurality of write machines, the workpiece being deviced to have a number of N layers and layers of the workpiece having one or a plurality of boundary condition(s) for pattern position, the method comprising the steps of: determining the boundary conditions of layers 1 to N, calculating deviations due to the boundary conditions and calculating a compensation for the deviation of the first transformation added with the assigned part of the deviation due to the boundary conditions.

Abstract: A vehicle allows a power storage device mounted therein to be externally charged using electric power from an external power supply. The vehicle includes an engine, a motor generator and a vehicle ECU. The vehicle allows a motor generator to generate electric power by driving the engine. Then, when charging of the power storage device is not completed within a target charging time period set by the user only using the electric power from the external power supply in the case where external charging is performed, the vehicle ECU charges the power storage device with the electric power from the external power supply additionally using the electric power generated by driving the engine.

Abstract: The present system and method manage a rechargeable battery comprising two or more battery cells or series stacks of cells. The system includes a set of switches, each of which connects a cell or stack of cells between positive and negative nodes when actuated, or connects one cell in a stack of cells to another cell in the stack when actuated, such that when all the switches in a given stack are actuated, it is connected between the positive and negative nodes. An electrical load is directly connected to the positive and negative nodes. A controller determines the state of each cell or stack of cells by measuring and/or calculating one or more predetermined characteristics, and selectively actuates the switches based on the states of the cells or stacks of cells so as to enhance the life of the battery.