Abstract: A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern.

Abstract: The invention relates to an apparatus for charging a remote feedable circuit bioelectronic implanted in a patient or in a laboratory animal, said apparatus comprising a composable container configured to define a closed environment suitable to receive a patient or a laboratory animal, said container comprising a plurality of composable walls made of a nonmagnetic material and connected to each other so as to define said closed environment, said container comprising at least one first winding whose axis is arranged in a first direction (Z) and at least one second winding whose axis is arranged in a second direction (Y) perpendicular to said first direction (Z).

Abstract: A method for designing a clock tree is disclosed. In one embodiment, a preliminary clock tree design for an integrated circuit (IC) is processed. The clock tree includes a root node, a number of intermediate levels, and a leaf level that is coupled to a number of clocked circuits. Clock gating circuits are placed at the leaf level of the clock tree, and at least some of the intermediate levels. Processing the preliminary clock tree design includes ensuring that an equal number of clock gating circuits are coupled between each leaf level clock gating circuit and the root node. After processing the preliminary clock tree design, clock tree synthesis is performed by executing a clock tree synthesis tool on a computer system to generate a synthesized clock tree design.

Abstract: A vehicle having communications circuitry for connecting over a wireless network to a server for exchanging vehicle condition information is provided. The vehicle includes an on-board computer for interfacing with vehicle systems and the communications circuitry. The on-board computer is further configured to process input received from at least one vehicle interface of the vehicle and processing output via at least one vehicle output of the vehicle. The communications circuitry is configured to send to the server over the wireless network vehicle data for vehicle status information, the vehicle status information is for one or more vehicle systems of the vehicle. The server accesses at least one database that include diagnostics data for a vehicle type of the vehicle and crowd sourced data for the vehicle type, the crowd sourced data includes comments received from one or more users of vehicles of the vehicle type that relate to the vehicle status information of one or more vehicle systems of the vehicle.

Abstract: Interlaced bi-sensor super-resolution enhancement techniques and a resultant scalable pixel array suitable for a mega-pixel design are disclosed. The method includes interlacing a first array of pixels of a first size with a second array of pixels of a second size. The interlacing of the first array of pixels with the second array of pixels avoids crossing two or more photosensitive areas of the first array of pixels and the second array of pixels.

Abstract: A portable charger is capable of jump starting a 12V car battery as well as charging 5V portable electronic devices. The charger includes a charger battery; a power supply operatively connected with the charger battery; at least one USB output jack operatively connected with the power supply for providing +5V USB power; and positive and negative jumper cable jacks operatively connected with the power supply for providing +12 V DC power to jump start a vehicle battery.

Abstract: A method of designing a layout of a semiconductor device includes receiving information on a size of a target chip and a unit placement width for forming a gate line through a self-align double patterning process by a layout design system. The method also includes allocating an input and output area, a hard macro area, and a standard cell area at the target chip, and adjusting a width of the standard cell area by applying a gate generation rule for setting a width of at least one cell row located in the standard cell area to an odd number multiple of the unit placement width. The unit placement width corresponds to a width between centers of a pair of gate lines in the self-align double patterning process.

Abstract: An energy storage system is provided. The energy storage system including a battery includes a battery management system (BMS) monitoring a battery state of the battery and controlling charging and discharging operations of the battery; and a power condition system (PCS) determining a desired control value of the battery, obtaining power market adjustment rule information on a power market including the energy storage system, calculating a deadband value for the desired control value based on the obtained power market adjustment rule information, and controlling the BMS controlling the charging and discharging operations of the battery based on the calculated deadband value for the desired control value and the monitored battery state.

Abstract: An integrated circuit may include observable storage circuits and unobservable or non-observable storage circuits. Among values stored in the observable and the non-observable storage circuits, only the values stored in the observable storage circuits are accessible for read-back and/or write-back operations during hardware emulation. A computer system may receive a circuit design that includes a design-under-test and implement at least a portion of the circuit design in the integrated circuit. The computer system may insert observable storage circuits into the circuit design and couple the observable storage circuits to the non-observable storage circuits such that the data stored in the non-observable storage circuits may be accessed during read-back operations using the inserted observable storage circuits.

Abstract: Disclosed is a wireless power receiver and a power control method thereof. The wireless power receiver includes a reception unit to receive power from the wireless power transmitter by using a resonance scheme; a load management unit to control an impedance of the load according to a state of the load; and a rectifying unit disposed between the reception unit and the load management unit in order to rectify the received power, wherein the power transmitted from the wireless power transmitter is controlled by the controlled impedance.

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

Abstract: The invention relates to an attenuation circuit for an energy storage device having one or more energy storage modules which are connected in series in one or more energy supply lines and have at least one energy storage cell and a coupling device which has a multiplicity of coupling elements and is designed to selectively switch or bridge the energy storage cell in the respective energy supply line.

Abstract: A system and method perform global routing during integrated circuit fabrication. The method includes performing a design change in a portion of an integrated circuit design using a processor, determining whether the design change requires rerouting, and requesting a global routing lock based on determining that the design change requires the rerouting. The method also includes a router providing control of the global routing lock to one of two or more of the threads that request the global routing lock, and performing global routing for all of the two or more of the threads in parallel. A physical implementation of the integrated circuit design is obtained.

Abstract: Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating transition state specifications that include information regarding low power behavior of a System on Chip (SoC) and/or a Network on Chip (NoC). Such transition state specifications can enable verification of switching behavior when elements/components of a SoC/NoC or a subset thereof switch from one power profile to another, or when the elements/components switch in stable states of power based on inputs such as voltages, clocks, power domains, and traffic.

Abstract: Aspects of processing a circuit design include synthesizing the circuit design and placing elements of the synthesized circuit design. After placing and before routing, respective delay values and slacks are determined. A first path having a most negative slack is determined and a first group of candidate paths is selected. The first group of candidate paths is a subset of critical paths of the circuit design, and the first group of candidate paths have delay values within a threshold range of delay values from the delay value of the first path. The first group of candidate paths are modified to reduce the respective delay values and a second group of candidate paths is selected. The second group of candidate paths have circuit structures that match selected circuit structures and are modified to reduce the respective delay values. A critical path having a most negative slack is iteratively selected and modified to reduce the respective delay value.

Abstract: A monitoring device includes an input terminal configured to receive an input signal from a battery system management (BSM); an output terminal configured to output cell parameters used to determine an open cell voltage associated with one of a plurality of cells within the battery stack connected to the monitoring circuit based on the input signal received from the BSM; a processor; and a memory storing executable instructions for causing the processor to: measure a cell voltage associated with the one of the plurality of cells within the battery stack; measure a voltage drop associated with a measured balancing current; calculate the open cell voltage by adjusting the measured cell voltage based on the measured voltage drop; and balance the battery stack based on the calculated open cell voltage, wherein balancing and calculating the open cell voltage are performed concurrently.

Abstract: Embodiments relate to the emulation of circuits, and representation of unknown states of signals. A disclosed system (and method and computer program product) includes an emulation environment to convert a digital signal of a DUT in a form capable of representing an unknown state. In addition, the disclosed system converts digital logic circuits such as Boolean logic, flip flops, latches, and memory circuits to be operable with signals having unknown states. Thus, an unknown state of a signal is indicated and propagated through digital logic circuits represented in a disclosed semantic to enable prompt detection of improper operation of the DUT, for example, due to power shut down or inadequate initialization.

Abstract: A system and method of layout design for an integrated circuit and integrated circuit, the method includes positioning all conductive traces of a first mask pattern, in a first direction, wherein the conductive traces of the first mask pattern are in a first conductive layer. The method also includes positioning all conductive traces of a second mask pattern, in the first direction, wherein the conductive traces of the second mask pattern are in the first conductive layer, and the second mask pattern is offset from the first mask pattern in a second direction different from the first direction.

Abstract: An IC design method includes: receiving a first layout including a first pattern; receiving a second layout including a second pattern, the first pattern separated from the second pattern when overlapping the first layout and the second layout; providing a cut pattern between the first pattern and the second pattern and overlapping the first pattern when overlapping the first layout, the second layout and the cut pattern; and providing a jog extending from the cut pattern to further overlap the first pattern with a length when a spacing between the second pattern and an edge of the cut pattern overlapping the first pattern is lower than a predetermined value, in which a ratio of the length of the jog to the spacing between the second pattern and the edge of the cut pattern overlapping the first pattern is in a range of 1/5 to 1/1.

Abstract: A method performed by at least one processor comprises the steps of: generating a layout data of a chip comprising transistors; determining heat-related parameters for the transistors based on the locations thereof in the layout data; generating a netlist data comprising the heat-related parameters; performing a post-layout simulation based on the netlist data; and verifying whether the post-layout simulation meets a design specification.