Abstract: Provided is a substrate processing apparatus, including: a processing space configured to process a substrate: an exhaust buffer chamber which is provided so as to surround a lateral circumference of the processing space and into which a gas supplied into the processing space is flowed; and a conductance adjustment plate disposed to face a gas flow path between the processing space and the exhaust buffer chamber, wherein the conductance adjustment plate has R-shaped portion or a tapered inclined portion on an inner peripheral side edge facing the gas flow path from the processing space to the exhaust buffer chamber.

Abstract: A battery block is equipped with a plurality of battery blocks. Each of the battery blocks includes at least one battery cell to provide a block voltage of the battery block. A first number of the battery blocks is selected, and the first number of the battery blocks is coupled to voltage terminals of the battery to set a battery voltage which corresponds to the sum of the block voltages of the first number of battery blocks. Further, a second number of the battery blocks is selected, and the second number of battery blocks is coupled to the voltage terminals of the battery to set a battery voltage which corresponds to the sum of the block voltages of the second number of battery blocks.

Abstract: Systems and techniques are described for optimizing a circuit design by using a numerical solver. The gates sizes are optimized by modeling a set of gate optimization problems and solving the set of gate optimization problems by using a numerical solver. Modeling each gate optimization problem can include selecting a portion of the circuit design that includes a driver gate that drives one or more inputs of each gate in a set of gates, and modeling a gate optimization problem for the portion of the circuit design based on circuit information for the portion of the circuit design. A differentiable objective function for delay can be created using numerical models for the delays in the circuit. In some embodiments, gradients of the differentiable objective function can be computed to enable the use of a conjugate-gradient-based numerical solver.

Abstract: An embodiment of the invention provides a charging station for a cleaning robot. The charging station includes an IR transmitter and a controller. The IR transmitter outputs a first IR light beam, wherein the IR light beam includes a second boundary and a first boundary which is substantially perpendicular or perpendicular to the charging station and the cleaning robot moves to the charging station along the first boundary. The controller controls the IR transmitter to output the first IR light beam or a second IR light beam. When the controller determines that the cleaning robot is near to the charging station, the controller controls the IR transmitter to output the second IR light beam.

Abstract: Methods and apparatus for decompressing test data using XOR trees for application to scan chains of a design for test (DFT) integrated circuit in a physically efficient construction are disclosed. Moreover, methods and apparatus for compressing test response data from scan chains in a DFT integrated circuit in a physically efficient construction are disclosed. The XOR tree decompression method may comprise splitting signals at each node of the XOR trees according to distribution logic implemented by a set of XOR gates. The XOR tree compression method may comprise combining signals at each node of the XOR trees according to combination logic implemented by a set of XOR gates.

Abstract: A non-transitory recording medium storing a program that causes a computer to execute a circuit board design assistance process. The circuit board design assistance process includes: extracting, from design information of a multilayer circuit board in which a plurality of layers are layered, a plurality of ground patterns in the multilayer circuit board that are within a predetermined distance from a path of a signal that flows in the multilayer circuit board; resolving a region at which the plurality of ground patterns are electronically separated as being a discontinuity region; and displaying the resolved discontinuity region.

Abstract: Provided is a charging and discharging device that does not need to use a high voltage capacitor even if a shielding switch is provided in an assembled battery for the sake of convenience of maintenance, and the like. The charging and discharging device includes: capacitors for connecting control terminals of adjacent circuit blocks, the shielding switch interposed between the adjacent battery modules, and a transformer interposed between the control terminals corresponding to the adjacent battery modules.

Abstract: Disclosed is a method for improving integrated circuit (IC) chip reliability. In the method, IC chips, which are manufactured according to a given IC chip design, are sorted into multiple different groups associated with different process windows in the process distribution for the design. Different operating voltages are assigned to the different groups, respectively, in order to optimize overall reliability of IC chips across the process distribution. That is, each group is associated with a specific process window, comprises a specific portion of the IC chips and is assigned a group-specific operating voltage that minimizes the fail rate of the specific portion of the IC chips and that, thereby optimizes the reliability of the specific portion of the IC chips. The group-specific operating voltage will be within minimum and maximum voltages associated with either the process distribution or the specific process window (e.g., following power-optimized selective voltage binning).

Abstract: Systems and methods compute a mean timing value of an integrated circuit design for variables using a first timing calculation of relatively higher accuracy; and calculate a first timing value of the integrated circuit design for the variables, using a second timing calculation having a relatively lower accuracy. Such systems and methods calculate second timing values of the integrated circuit design for additional sets of variables using the second timing calculation; and calculate finite differences of each of the second timing values to the first timing value. Thus, these systems and methods calculate a statistical sensitivity of the first timing value to the additional sets of variables based on the finite differences. Further, such systems and methods calculate a statistical sensitivity of the mean timing value to the additional sets of values based on the statistical sensitivity of the first timing value to the additional sets of values.

Abstract: A rechargeable battery temperature detection method adapted to an electronic system includes detecting a status of a processor of the electronic system when an external power is input to a power conversion module of the electronic system; determining whether a thermistor of the electronic system is conducted to a fuel gauge or a charge control circuit according to the state of the processor such that the fuel gauge or the charge control circuit determine a temperature sensing result via the thermistor. The thermistor is disposed adjacent to a rechargeable battery and has a resistance which varies with a temperature of the rechargeable battery. The temperature sensing result is related to the resistance.

Abstract: This application discloses a system implementing tools and mechanisms to determine whether a portion of combinational logic in a first circuit design is equivalent to a portion of combinational logic in a second circuit design. When the portions of the combinational logic in the first circuit design and the second circuit design are not equivalent, the tools and mechanisms can sequentially expand the portions of the combinational logic in the first circuit design and the second circuit design, and determine whether the expanded portion of the combinational logic in the first circuit design is equivalent the expanded portion of the combinational logic in the second circuit design.

Abstract: An embodiment of the invention provides a cleaning robot including a light detector and a controller. The light detector detects a light beam. The controller is coupled to the light detector to control the cleaning robot. When the controller determines that the light beam is being output by a charging station, the controller controls the cleaning robot to move to the charging station along a first boundary of the light beam, which is substantially perpendicular to the charging station.

Abstract: An IC design method includes: receiving a first layout including a first pattern; receiving a second layout including a second pattern, the first pattern separated from the second pattern when overlapping the first layout and the second layout; providing a cut pattern between the first pattern and the second pattern and overlapping the first pattern when overlapping the first layout, the second layout and the cut pattern; and providing a jog extending from the cut pattern to further overlap the first pattern with a length when a spacing between the second pattern and an edge of the cut pattern overlapping the first pattern is lower than a predetermined value, in which a ratio of the length of the jog to the spacing between the second pattern and the edge of the cut pattern overlapping the first pattern is in a range of 1/5 to 1/1.

Abstract: An adapter includes a converter unit which increases at least one of voltage and current outputted from a battery pack and supply the increased the voltage and/or the current to a load, and a characteristic detection unit which detects at least one of the voltage outputted from the battery pack, the current outputted from the battery pack, a temperature of the battery pack, a voltage inputted to the load, a current inputted to the load and a temperature of the converter unit. The adapter further includes a control unit configured to control the converter unit to increase each of said at least one of the voltage and the current outputted from the battery pack to a corresponding reference value and perform a control operation of suppressing such increase to prevent an occurrence of over-current or over-discharge based on at least one detection result.

Abstract: Methods and computer-readable media for effecting physically efficient scans of integrated circuit designs may include selecting a two-dimensional grid size for exposure to the method, the two-dimensional grid having a size that includes a first side length, a second side length, and a number of flops. The method is performed to select a two-dimensional grid size that maximizes compression efficiency and limit wiring congestion on the IC. In one aspect, the method may be performed on each region of the grid that maintains one of a respective first side length and a respective second side length greater than one, including selecting a larger side, determining if the larger side is odd or even, and dividing the grid along the larger side into two regions each having a proportion of the flops. The scans of the resulting regions are efficient, and consequently facilitate integrated circuit design and subsequent manufacture.

Abstract: A system for designing a semiconductor package using a computing system, comprising: a virtual stacking module configured to receive a layout parameter for a first chip, a layout parameter for a second chip, and a layout parameter for a package substrate, and in response to the layout parameters of the first chip, the second chip, and the package substrate, generate a plurality of virtual layouts in which the first and second chips are stacked, on the package substrate; a modeling module configured to model operating parameters for the first and second chips and the package substrate in response to the virtual layouts; and a characteristic analyzing module configured to analyze operating characteristics of the virtual layouts in response to the modeled operating parameters.

Abstract: A system and method for tracing a net includes comparing an IC design against a marked portion of the IC design, and extracting a traced net that includes the marked portion from the IC design file. The method also includes displaying the traced net and storing at least one indicator along with information identifying the traced net.

Abstract: A secondary battery has a progressively deteriorating SOC in which battery performance deteriorates when the secondary battery is stored, and is charged and discharged by a control device. An information processing device stores a preset first threshold smaller than the progressively deteriorating SOC of the secondary battery and a preset second threshold greater than the progressively deteriorating SOC, and separates the range from the minimum SOC to the maximum SOC of the secondary battery into, at least, two regions by setting the section from the first threshold to the second threshold as a boundary to thereby cause the control device to charge or discharge the secondary battery within any of the above regions.

Abstract: A control circuit for indirectly limiting a load current which flows through a controllable semiconductor component. The control circuit controls the controllable semiconductor component based upon a measured and/or a calculated load-current-dependent power loss of the semiconductor component. The control circuit can also control the controllable semiconductor component based upon a measured and/or a calculated load-current-dependent component temperature of the controllable semiconductor component. A charging circuit includes a controllable semiconductor component for limiting a load current and has a control circuit in accordance with the invention. A motor vehicle includes an on-board electrical power supply system having a charging circuit in accordance with the invention.

Abstract: The present invention relates to a pair of transistors wherein each transistor of said transistor pair is made of several sub-transistors, and each sub-transistor of a transistor has a sub-transistor channel length and has a sub-transistor channel width, said sub-transistor channel length being substantially equal to the transistor channel length, and said sub-transistor channel width being smaller than the transistor channel width, so that the sum of the sub-transistor channel widths of the sub-transistors of a transistor is substantially equal to the channel width of said transistor, wherein each sub-transistor (43) of a transistor of said transistor pair is spaced apart from at least one adjoining sub-transistor (44) of the other transistor of said transistor pair by a distance D less than half the transistor channel width, said distance d between two sub-transistors (43, 44) being measured between the respective center of the channels of said sub-transistors.