Patents Examined by Nicholas J. Tobergte
  • Patent number: 12015013
    Abstract: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: June 18, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Min-Chien Hsiao, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu
  • Patent number: 12015019
    Abstract: A multichip module (MCM) power package includes a multilayer routable leadframe substrate (MRLF) substrate including a first and a second RLF layer. A multilayer extending via extends from the first into the second RLF layer. A first vertical FET has a side flipchip attached to a bottom side of the second RLF. A second vertical FET has a side flipchip attached to a bottom side of the second RLF layer, and contacts the multilayer extending via. A controller integrated circuit (IC) is flipchip attached a top side of the MRLF substrate at least partially over the first vertical FET. A top mold compound is on a top side of the MRLF substrate lateral to the controller IC that is lateral to a metal pad on the multilayer extending via. A bottom side of the first and second vertical FET are exposed by a bottom mold compound layer.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: June 18, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jonathan Almeria Noquil, Makarand Ramkrishna Kulkarni
  • Patent number: 12014977
    Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same.
    Type: Grant
    Filed: May 19, 2023
    Date of Patent: June 18, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Seok Hong, Dongwoo Kim, Hyunah Kim, Un-Byoung Kang, Chungsun Lee
  • Patent number: 12015113
    Abstract: The application discloses a bonding method, a display backplane and a system for manufacturing the display backplane. The method includes: providing a substrate, and forming a plurality of first metal bumps on the substrate; providing a transfer device to transfer the plurality of the first metal bumps to a TFT substrate to form a plurality of pairs of metal pads on the TFT substrate, wherein each pair of the metal pads include two of the first metal bumps; and providing a plurality of LED flip chips, and transferring the plurality of LED flip chips to the TFT substrate by using the transfer device to bond electrodes of each of the LED flip chips to one pair of the metal pads respectively.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: June 18, 2024
    Assignee: CHONGQING KONKA PHOTOELECTRIC TECHNOLOGY RESEARCH INSTITUTE CO., LTD.
    Inventors: Shoujun Xiao, Tzu-ping Lin, Shan-Fu Yuan, Liu-chung Lee, Chung-yu Chou
  • Patent number: 12015080
    Abstract: Some embodiments include an integrated assembly having an access device between a storage element and a conductive structure. The access device has channel material which includes semiconductor material. The channel material has a first end and an opposing second end, and has a side extending from the first end to the second end. The first end is adjacent the conductive structure, and the second end is adjacent the storage element. Conductive gate material is adjacent the side of the channel material. A first domed metal-containing cap is over the conductive structure and under the channel material and/or a second domed metal-containing cap is over the channel material and under the storage element. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Yoshitaka Nakamura, Yi Fang Lee, Jerome A. Imonigie, Scott E. Sills, Aaron Michael Lowe
  • Patent number: 12014969
    Abstract: A package structure is provided. The package structure includes a redistribution structure over a substrate, a semiconductor die over the redistribution structure and electrically coupled to the substrate, and an underfill material over the substrate and encapsulating the redistribution structure and the semiconductor die. The underfill material includes an extension portion overlapping a corner of the semiconductor die and extending into the substrate.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chen Lai, Ming-Chih Yew, Li-Ling Liao, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 12009420
    Abstract: A semiconductor device includes a semiconductor layer having a first face with a trench formed thereon and a second face opposite to the first face, a gate electrode, and a gate insulating layer. The semiconductor layer includes a first n-type semiconductor layer, a second n-type semiconductor layer, a p-type semiconductor layer, and an n-type semiconductor region. The trench is formed to penetrate through the p-type semiconductor layer and to reach the second n-type semiconductor layer. The p-type semiconductor layer includes an extended portion extending to a position closer to the second face of the semiconductor layer than the trench is. Such structure allows suppressing dielectric breakdown in the gate insulating layer.
    Type: Grant
    Filed: September 14, 2023
    Date of Patent: June 11, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Yuki Nakano
  • Patent number: 12010828
    Abstract: A memory device includes a substrate and a stack including word lines and interlayer insulating patterns alternatingly stacked on the substrate. The word lines extend in a first direction. Semiconductor patterns cross the word lines and have longitudinal axes parallel to a second direction. The semiconductor patterns are spaced apart from each other in the first direction and a third direction. Bit lines extend in the third direction and are spaced apart from each other in the first direction. Each of the bit lines contacts first side surfaces of the semiconductor patterns spaced apart from each other in the third direction. Data storage elements, which are respectively provided between vertically adjacent interlayer insulating patterns and contact second side surfaces opposite to the first side surfaces, and substrate impurity layers provided in portions of the substrate at both sides of the stack, are included.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: June 11, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungjae Jung, Kwang-Ho Park
  • Patent number: 12010835
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures vertically extending through the alternating stack in a memory array region, and an electrically conductive spacer extending vertically and electrically connecting a first drain-select-level electrically conductive layer to a second drain-select-level electrically conductive layer.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: June 11, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Satoshi Shimizu
  • Patent number: 12010829
    Abstract: A semiconductor memory device and method for making the same. The semiconductor device includes a transistor laterally extending in a direction parallel to a substrate and including an active layer over the substrate, the active layer having a first end and a second end; bit line contact nodes formed on an upper surface and a lower surface of the first end of the active layer, respectively; a bit line side-ohmic contact vertically extending and connecting to the first end of the active layer and the bit line contact nodes; a bit line extending in a vertical direction to the substrate and connected to the bit line side-ohmic contact; and a capacitor connected to the second end of the active layer.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: June 11, 2024
    Assignee: SK hynix Inc.
    Inventor: Seung Hwan Kim
  • Patent number: 12010827
    Abstract: An apparatus includes fin structures comprising individual levels of a conductive material having elongated portions extending in a first horizontal direction, first conductive lines extending in a second horizontal direction transverse to the first horizontal direction, and second conductive lines extending in a vertical direction transverse to each of the first horizontal direction and the second horizontal direction. At least portions of the first conductive lines are aligned vertically. The apparatus also includes horizontal capacitor structures comprising the conductive material of the fin structures and access devices proximate intersections of the first conductive lines and the second conductive lines. The access devices comprise the conductive material of the fin structures. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: June 11, 2024
    Assignee: Micron Technology, Inc.
    Inventors: William M. Brewer, Christopher Locke, Kyle B. Campbell
  • Patent number: 12002763
    Abstract: A package substrate includes: a core insulation layer having first and second package regions and a boundary region between the first and second package regions; a first upper conductive pattern in the first package region; a second upper conductive pattern in the second package region; a first insulation pattern on the core insulation layer to partially expose the first and second upper conductive patterns, wherein the first insulation pattern includes a first trench at the boundary region, and first reinforcing portions in the first trench; a first lower conductive pattern in the first package region; a second lower conductive pattern in the second package region; and a second insulation pattern on the core insulation layer to partially expose the first and second lower conductive patterns, wherein the second insulation pattern includes a second trench at the boundary region, and second reinforcing portions in the second trench.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: June 4, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seungmin Kim
  • Patent number: 12004338
    Abstract: Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes a pillar having an upper source/drain, a middle source/drain, a lower source/drain, an upper channel between the upper source/drain and the middle source/drain, and a lower channel between the middle source/drain and the lower source/drain. The integrated assembly includes a gate pair that includes a first gate and a second gate. The first gate is positioned on a first side of the pillar at a first height, and the second gate is positioned on a second side of the pillar, that is opposite the first side, at a second height that is different from the first height. The integrated assembly includes a capacitor that is electrically coupled with the upper source/drain. Some implementations include methods of forming the various structures, integrated assemblies, and memory devices.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: June 4, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Giorgio Servalli, Marcello Mariani, Antonino Rigano, Marcello Calabrese
  • Patent number: 11996359
    Abstract: Apparatuses may include a device substrate including a microelectronic device and bond pads proximate to an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball positioned and configured to carry a high-bandwidth data signal or a high-frequency clock signal may be located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry a high-bandwidth data signal or a high-frequency clock signal. Each ball positioned and configured to carry a high-bandwidth data signal may be located only diagonally adjacent to any other balls configured to carry a high-bandwidth data signal or a high-frequency clock signal.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: May 28, 2024
    Assignee: Micron Technology, Inc.
    Inventors: David K. Ovard, Thomas Hein, Timothy M. Hollis, Walter L. Moden
  • Patent number: 11996325
    Abstract: A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Li-Te Hsu
  • Patent number: 11990167
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Jhih Shen, Kuang-I Liu, Joung-Wei Liou, Jinn-Kwei Liang, Yi-Wei Chiu, Chin-Hsing Lin, Li-Te Hsu, Han-Ting Tsai, Cheng-Yi Wu, Shih-Ho Lin
  • Patent number: 11990350
    Abstract: Methods for manufacturing semiconductor devices having a flexible reinforcement structure, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes electrically coupling at least one semiconductor die to a redistribution structure on a first carrier. The semiconductor die can include a first surface facing the redistribution structure and a second surface spaced apart from the redistribution structure. The method also includes reducing a thickness of the semiconductor die to no more than 10 ?m. The method further includes coupling a flexible reinforcement structure to the second surface of the at least one semiconductor die.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: May 21, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Chan H. Yoo
  • Patent number: 11985816
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a drain region positioned in the substrate; a common source region positioned in the substrate and opposing to the drain region; a bit line structure including a bit line conductive layer positioned on the substrate and electrically coupled to the common source region; a cell contact positioned on the substrate, adjacent to the bit line structure, and electrically connected to the drain region; a landing pad positioned above the bit line conductive layer and electrically connected to the cell contact; and an air gap positioned between the landing pad and the bit line conductive layer.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: May 14, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Liang-Pin Chou
  • Patent number: 11985811
    Abstract: A semiconductor memory device and a manufacturing method thereof, a reading/writing method, an electronic device and a memory circuit are provided. A transistor is provided in each memory cell in the semiconductor memory device. A gate electrode and an auxiliary electrode are provided in the transistor, and the auxiliary electrode is electrically connected to a drain electrode. During a writing operation, a first voltage is applied to the gate electrode through a word line, and an electrical signal is applied to a source electrode through a bit line according to the external input data.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: May 14, 2024
    Assignee: Beijing Superstring Academy of Memory Technology
    Inventors: Zhengyong Zhu, Bokmoon Kang, Guilei Wang, Chao Zhao
  • Patent number: 11984403
    Abstract: An integrated substrate structure includes a redistribution film, a circuit substrate, and a plurality of conductive features. The redistribution film includes a fine redistribution circuitry, a circuit substrate is disposed over the redistribution film and includes a core layer and a coarse redistribution circuitry disposed in and on the core layer. The circuit substrate is thicker and more rigid than the redistribution film, and a layout density of the fine redistribution circuitry is denser than that of the coarse redistribution circuitry. The conductive features are interposed between the circuit substrate and the redistribution film to be connected to the fine redistribution circuitry and the coarse redistribution circuitry. A redistribution structure and manufacturing methods are also provided.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: May 14, 2024
    Inventor: Dyi-Chung Hu