Patents Examined by Nicholas J. Tobergte
  • Patent number: 11183466
    Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The method inluces forming a semiconductor chip, forming an electromagnetic shield that covers the semiconductor chip, and forming a molding that covers the electromagnetic shield. The electromagnetic shield is electrically connected to a conductor on a side of the semiconductor chip.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: November 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Youngwoo Park
  • Patent number: 11183470
    Abstract: A semiconductor package includes a substrate and a semiconductor chip disposed over the substrate. The substrate includes: a base layer including an upper surface facing the semiconductor chip; an upper ground electrode plate disposed over the upper surface of the base layer and configured to transmit a ground voltage to the semiconductor chip; and a dummy power pattern disposed in the upper ground electrode plate and having a side surface which is surrounded by the upper ground electrode plate and is spaced apart from the upper ground electrode plate with an insulating material between the dummy power pattern and the upper ground electrode plate. A ground voltage transmission path from the upper ground electrode plate to the semiconductor chip is spaced apart from the dummy power pattern.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: November 23, 2021
    Assignee: SK hynix Inc.
    Inventors: Jae Hoon Lee, Hyung Ho Cho
  • Patent number: 11177206
    Abstract: A layout structure of double-sided flexible circuit board includes a flexible substrate having a first surface and a second surface, a first circuit layer and a second circuit layer. An inner bonding region is defined on the first surface and an inner supporting region is defined on the second surface according to the inner bonding region. The first circuit layer is located on the first surface and includes first conductive lines which each includes an inner lead located on the inner bonding region. The second circuit layer is located on the second surface and includes second conductive lines which each includes an inner supporting segment located on the inner supporting region. A width difference between any two of the inner supporting segment of the second conductive lines is less than 8 ?m.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: November 16, 2021
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chun-Te Lee, Chih-Ming Peng, Hui-Yu Huang, Yin-Chen Lin
  • Patent number: 11177241
    Abstract: A semiconductor device is disclosed including a die stack including a number of dies aligned with each other with respect to an axis, and a top die that is offset along the axis the to prevent die cracking.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: November 16, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Junrong Yan, Jianming Zhang, Min Zhao, Kailei Zhang, Chee Keong Chin, Kim Lee Bock
  • Patent number: 11177213
    Abstract: An anti-fuse device having enhanced programming efficiency is provided. The anti-fuse device includes via contact structures that have different critical dimensions located between a first electrode and a second electrode. Notably, a first via contact structure having a first critical dimension is provided between a pair of second via contact structures having a second critical dimension that is greater than the first critical dimension. When a voltage is applied to the device, dielectric breakdown will occur first through the first via contact structure having the first critical dimension.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Baozhen Li, Tianji Zhou, Ashim Dutta, Saumya Sharma
  • Patent number: 11171069
    Abstract: A display module and a method of manufacturing the display module are provided. The display module comprises a display panel, a driving integrated circuit on the display panel, and a protective tape on the driving integrated circuit. The protective tape includes a second adhesive material on the driving integrated circuit, and an adhesive tape on the second adhesive material. The second adhesive material fills an area between the adhesive tape and the display panel.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 9, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Guoqiang Jiang
  • Patent number: 11164998
    Abstract: An electrode structure includes a first electrode and a second electrode disposed opposite to each other. The first electrode has a first side and a second side. The second side is located between the first side and the second electrode. The first electrode has a maximum vertical length and a minimum vertical length from the first side to the second side, and a ratio of the minimum vertical length to the maximum vertical length is less than 0.8. The second electrode and the first electrode are separated by a first vertical gap and a second vertical gap, and the second vertical gap is greater than the first vertical gap.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: November 2, 2021
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Yu-Chu Li, Pei-Hsin Chen, Yi-Chun Shih, Yi-Ching Chen
  • Patent number: 11164798
    Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first device region and a second device region; forming a first doped layer on the semiconductor substrate; forming a first fin layer on the first doped layer in the first device region; forming a second fin layer on the first doped layer in the second device region; forming a first isolation layer on the first doped layer in the first device region and covering sidewall surfaces of the first fin layer; forming a second isolation layer on the second doped layer in the second device region and covering portions of sidewall surfaces of the second fin layer and with a thickness smaller than a thickness of the first isolation layer; and forming a first gate structure on the first isolation layer and a second gate structure on the second isolation layer.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: November 2, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 11164839
    Abstract: A package structure includes a semiconductor die and a redistribution circuit structure. The redistribution circuit structure is disposed on and electrically connected to the semiconductor die and includes a patterned conductive layer, a dielectric layer, and an inter-layer film. The dielectric layer is disposed on the patterned conductive layer. The inter-layer film is sandwiched between the dielectric layer and the patterned conductive layer, and the patterned conductive layer is separated from the dielectric layer through the inter-layer film.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Po-Han Wang, Yung-Chi Chu, Hung-Chun Cho
  • Patent number: 11164825
    Abstract: An interposer circuit includes a substrate and a dielectric layer that is disposed on top of the substrate. The interposer circuit includes two or more connection layers including a first connection layer and a second connection layer that are disposed at different depths in the dielectric layer. The interposer circuit includes a fuse that is disposed in the first connection layer. The first connection layer is coupled to a first power node and the second connection layer is coupled to a first ground node. The interposer circuit further includes a first capacitor that is in series with the fuse and is connected between the first and the second connection layers. The interposer circuit also includes first, second, and third micro-bumps on top of the dielectric layer such that the fuse is coupled between the first and second micro-bumps and the first capacitor is coupled between the second and third micro-bumps.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: November 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Liang-Chen Lin, Shih-Cheng Chang
  • Patent number: 11158684
    Abstract: A display device includes a display panel and an anti-reflection unit directly disposed on the display panel. The display panel includes first to third light emitting elements, each of which includes first and second electrodes, and a light emitting layer, which is disposed between the first electrode and the second electrode. The pixel definition layer includes a first portion, in which a light-emitting opening exposing the first electrode is defined, and a second portion, which is disposed on and overlapped with the first portion. The anti-reflection unit includes first to third color filters overlapped with the first to third light emitting elements, respectively, and a color spacer, which is overlapped with the second portion and is thicker than each of the first to third color filters.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: October 26, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyeonbum Lee, Hyoeng-ki Kim, Kwangwoo Park
  • Patent number: 11152424
    Abstract: A display device includes at least one first and second electrodes extending in a first direction, at least one first and second light emitting elements disposed therebetween, a first contact electrode partially covering the first electrode and contacting a first end of the first light emitting element, a second contact electrode partially covering the second electrode and contacting a third end of the second light emitting element, and a third contact electrode disposed between the first and second contact electrodes and contacting a second end of the first light emitting element and a fourth end of the second light emitting element, in which a distance between the first and second electrodes is greater than a longitudinal length of at least one of the first and second light emitting elements, and the first and second light emitting elements are connected in series between the first and second electrodes.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: October 19, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Xin Xing Li, Tae Jin Kong, Hee Keun Lee, Hyun Min Cho, Chang Il Tae
  • Patent number: 11152276
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric protection layer is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Kuo-Ming Wu
  • Patent number: 11145543
    Abstract: A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive line including a first conductive material, and a second conductive line including a second conductive material. A via connects the first conductive line to the second conductive line, wherein the via includes conductive via material, wherein the via material top surface is coated with a liner material, wherein the via is a bottomless via.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: October 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Terry A. Spooner, Junli Wang
  • Patent number: 11145586
    Abstract: An interposer includes a stacked body including insulating base material layers that are stacked on one another, first and second electrodes, a conductor pattern, and an interlayer connection conductor. The stacked body includes a first mounting surface including a first electrode, and a second mounting surface facing the first mounting surface and including a second electrode. The first electrode is electrically connected to the second electrode through the conductor pattern and the interlayer connection conductor. A length of an electrical path including conductor patterns connecting the first electrode and the second electrode is larger than a total length of the interlayer connection conductor in a stacking direction.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: October 12, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kanto Iida, Hiromasa Koyama
  • Patent number: 11147156
    Abstract: A composite member includes a substrate composed of a composite material containing a metal and a non-metal. One surface of the substrate has spherical warpage of which radius of curvature R is not smaller than 5000 mm and not greater than 35000 mm. A sphericity error is not greater than 10.0 ?m, the sphericity error being defined as an average distance between a plurality of measurement points on a contour of a warped portion of the substrate and approximate arcs defined by the plurality of measurement points. The substrate has a thermal conductivity not lower than 150 W/m·K and a coefficient of linear expansion not greater than 10 ppm/K.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: October 12, 2021
    Assignees: Sumitomo Electric Industries, Ltd., AL.M.T. CORP.
    Inventors: Isao Iwayama, Shigeki Koyama, Masashi Okamoto, Yuta Inoue, Hiroyuki Kontani, Takehisa Yamamoto
  • Patent number: 11145692
    Abstract: Embodiments of the disclosed subject matter provide a wearable device that includes an organic light emitting diode (OLED) light source to output light having one peak wavelength from a single OLED emissive layer, and a first barrier layer that is disposed over or between the single OLED emissive layer and one or more down-conversion layers. One or more regions of the single OLED emissive layer are independently switchable and controllable so that the wearable device is configurable to output a plurality of wavelengths of light. One of the plurality of wavelengths of light that is output is near infrared light.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: October 12, 2021
    Assignee: Universal Display Corporation
    Inventors: Michael Hack, Mark E. Thompson, Eric A. Margulies, Nicholas J. Thompson, Michael Stuart Weaver
  • Patent number: 11139442
    Abstract: Embodiments of the disclosed subject matter provide an emissive layer, a first electrode layer, a plurality of nanoparticles and a material disposed between the first electrode layer and the plurality of nanoparticles. In some embodiments, the device may include a second electrode layer and a substrate, where the second electrode layer is disposed on the substrate, and the emissive layer is disposed on the second electrode layer. In some embodiments, a second electrode layer may be disposed on the substrate, the emissive layer may be disposed on the second electrode layer, the first electrode layer may be disposed on the emissive layer, a first dielectric layer of the material may be disposed on the first electrode layer, the plurality of nanoparticles may be disposed on the first dielectric layer, and a second dielectric layer may be disposed on the plurality of nanoparticles and the first dielectric layer.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: October 5, 2021
    Assignee: Universal Display Corporation
    Inventors: Michael Fusella, Nicholas J. Thompson
  • Patent number: 11139338
    Abstract: A light emitting device including a substrate, first and second light emitting diodes disposed thereon and including a first semiconductor layer, an active layer, and a second semiconductor layer, a first upper electrode electrically connected to the first semiconductor layer and insulated from the second semiconductor layer of the first light emitting diode, a second upper electrode electrically connected to the first semiconductor layer and insulated from the second semiconductor layer of the second light emitting diode, in which the first and second light emitting diodes are spaced apart from each other to expose the substrate, the first upper electrode has a protrusion electrically connected to the second semiconductor layer of the second light emitting diode and covering portions of the exposed substrate, the first light emitting diode, and the second light emitting diode, and the second upper electrode has a groove.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: October 5, 2021
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jong Min Jang, Jong Hyeon Chae, Joon Sup Lee, Daewoong Suh, Hyun A Kim, Won Young Roh, Min Woo Kang
  • Patent number: 11139240
    Abstract: A semiconductor module includes a semiconductor chip including wiring formed over a semiconductor element such as a MISFET, a sealing resin part MR covering the semiconductor chip such that the wiring is exposed, and an inductor formed in redistribution wiring. The inductor overlaps with the sealing resin part covering at least a side surface of the semiconductor chip in plan view.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: October 5, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba