Patents Examined by Nicholas J. Tobergte
  • Patent number: 11569158
    Abstract: A semiconductor package includes a redistribution substrate having a dielectric layer and a wiring pattern in the dielectric layer, the wiring pattern including a line part that extends horizontally, and a via part connected to the line part, the via part having a width less than a width of the line part, a passivation layer on a top surface of the redistribution substrate, the passivation layer including a material different from a material of the dielectric layer, a conductive pillar that penetrates the passivation layer, the conductive pillar being connected to the via part, and a connection terminal on a top surface of the conductive pillar, a distance between the top surface of the conductive pillar and a top surface of the passivation layer being greater than a thickness of the passivation layer.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: January 31, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myungsam Kang, Youngchan Ko, Jeongseok Kim, Kyung Don Mun, Bongju Cho
  • Patent number: 11569480
    Abstract: Provided are compounds, formulations comprising compounds, and devices that utilize compounds, where the devices include a substrate, a first electrode, an organic emissive layer comprising an organic emissive material disposed over the first electrode. The device includes an enhancement layer, comprising a plasmonic material exhibiting surface plasmon resonance that non-radiatively couples to the organic emissive material and transfers excited state energy from the organic emissive material to the non-radiative mode of surface plasmon polaritons. The enhancement layer is provided no more than a threshold distance away from the organic emissive layer, where the organic emissive material has a total non-radiative decay rate constant and a total radiative decay rate constant due to the presence of the enhancement layer. At least one of the organic emissive material and the organic emissive layer has a vertical dipole ratio (VDR) value of equal or greater than 0.33.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: January 31, 2023
    Assignee: Universal Display Corporation
    Inventors: Michael Fusella, Nicholas J. Thompson
  • Patent number: 11569202
    Abstract: A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: January 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tin-Hao Kuo, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Yu-Chia Lai, Po-Yuan Teng
  • Patent number: 11569228
    Abstract: A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The method includes forming a conductive layer on a precursor memory structure, in which the precursor memory structure includes a plurality of transistors and a plurality of contact plugs disposed on and connected to the transistors. The conductive layer in a TEG region is then patterned to form a first patterned conductive layer on the precursor memory structure. The first patterned conductive layer is then patterned to form a plurality of first landing pads extending along a first direction, in which the first landing pads are separated from each other in a second direction that is different from the first direction and are electrically connected to each other through the contact plugs and the transistors.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: January 31, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Hsueh-Han Lu, Yu-Ting Lin, Tsang-Po Yang
  • Patent number: 11563070
    Abstract: Provided is a display device including: a pixel unit in which a plurality of pixel circuits (PIX_A, PIX_B, PIX_C) each of which includes a light emitting element and a driving circuit configured to drive the light emitting element are arranged in a matrix form. In a diffusion layer in which transistors included in the driving circuits of the pixel circuits (PIX_A, PIX_B, PIX_C) are formed, an electricity supply region (223) that is an active area for supplying an electric potential to a well is provided between mutually adjacent ones of the pixel circuits (PIX_A, PIX_B, PIX_C).
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: January 24, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Naobumi Toyomura, Takuma Fujii
  • Patent number: 11563011
    Abstract: A method used in forming integrated circuitry comprises forming conductive material over a substrate. The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the conductive line. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the conductive line. Electronic components are formed directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars. Additional methods, including structure independent of method, are disclosed.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: January 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Vinay Nair, Silvia Borsari, Ryan L. Meyer, Russell A. Benson, Yi Fang Lee
  • Patent number: 11562983
    Abstract: A package includes an integrated circuit. The integrated circuit includes a first chip, a second chip, a third chip, and a fourth chip. The second chip and the third chip are disposed side by side on the first chip. The second chip and the third chip are hybrid bonded to the first chip. The fourth chip is fusion bonded to at least one of the second chip and the third chip.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: January 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 11557579
    Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: January 17, 2023
    Assignee: Intel Corporation
    Inventors: Chong Zhang, Cheng Xu, Junnan Zhao, Ying Wang, Meizi Jiao
  • Patent number: 11557591
    Abstract: A method used in forming an array of memory cells comprises forming lines of top-source/drain-region material, bottom-source/drain-region material, and channel-region material vertically there-between in rows in a first direction. The lines are spaced from one another in a second direction. The top-source/drain-region material, bottom-source/drain-region material, and channel-region material have respective opposing sides. The channel-region material on its opposing sides is laterally recessed in the second direction relative to the top-source/drain-region material and the bottom-source/drain-region material on their opposing sides to form a pair of lateral recesses in the opposing sides of the channel-region material in individual of the rows. After the pair of lateral recesses are formed, the lines of the top-source/drain-region material, the channel-region material, and the bottom-source/drain-region material are patterned in the second direction to comprise pillars of individual transistors.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: January 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Marcello Mariani, Giorgio Servalli
  • Patent number: 11552022
    Abstract: A package substrate includes: a core insulation layer having first and second package regions and a boundary region between the first and second package regions; a first upper conductive pattern in the first package region; a second upper conductive pattern in the second package region; a first insulation pattern on the core insulation layer to partially expose the first and second upper conductive patterns, wherein the first insulation pattern includes a first trench at the boundary region, and first reinforcing portions in the first trench; a first lower conductive pattern in the first package region; a second lower conductive pattern in the second package region; and a second insulation pattern on the core insulation layer to partially expose the first and second lower conductive patterns, wherein the second insulation pattern includes a second trench at the boundary region, and second reinforcing portions in the second trench.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: January 10, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seungmin Kim
  • Patent number: 11552121
    Abstract: A semiconductor apparatus includes a stack of a first chip having a plurality of pixel circuits arranged in a matrix form and a second chip having a plurality of electric circuit arranged in a matrix form. A wiring path between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit or a positional relationship between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit is differentiated among the electric circuits.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: January 10, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hiroaki Kobayashi, Atsushi Furubayashi, Katsuhito Sakurai
  • Patent number: 11545424
    Abstract: A package structure including a redistribution circuit structure, an insulator, a plurality of conductive connection pieces, a first chip, a second chip, an encapsulant, a third chip, and a plurality of conductive terminals is provided. The redistribution circuit structure has first and second connection surfaces opposite to each other. The insulator is embedded in and penetrates the redistribution circuit structure. The conductive connection pieces penetrate the insulator. The first and second chips are disposed on the first connection surface. The encapsulant is disposed on the redistribution circuit structure and at least laterally covers the first and second chips. The third chip is disposed on the second connection surface and electrically connected to the first and second chips through the conductive connection pieces. The conductive terminals are disposed on the second connection surface and electrically connected to the first chip or the second chip through the redistribution circuit structure.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: January 3, 2023
    Assignee: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Nan-Chun Lin, Hung-Hsin Hsu
  • Patent number: 11545404
    Abstract: Before a semiconductor die of a brittle III-V compound semiconductor is encapsulated with a molding compound during package fabrication, side surfaces of the semiconductor die are treated to avoid or prevent surface imperfections from propagating and fracturing the crystal structure of the substrate of the III-V compound semiconductor under the stresses applied as the molding compound solidifies. Surfaces are treated to form a passivation layer, which may be a passivated layer of the substrate or a passivation material on the substrate. In a passivated layer, imperfections of an external layer are transformed to be less susceptible to fracture. Passivation material, such as a poly-crystalline layer on the substrate surface, diffuses stresses that are applied by the molding compound. Semiconductor dies in flip-chip and wire-bond chip packages with treated side surfaces as disclosed have a reduced incidence of failure caused by die fracturing.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: January 3, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Gengming Tao, Bin Yang, Xia Li
  • Patent number: 11538726
    Abstract: A method for forming a packaged electronic die includes forming a plurality of bonding pads on a device wafer. A photoresist layer is deposited over the device wafer and is patterned so as to form a photoresist frame that completely surrounds a device formed on the device wafer. Conductive balls are deposited over the bonding pads. The wafer is cut to form the electronic die and the electronic die is placed over the substrate. The conductive balls are heated and compressed, moving the electronic die closer to the substrate such that the photoresist frame is in direct contact with the substrate or with a landing pad formed on the substrate. Encapsulant material is deposited such that the encapsulant material covers the electronic die and the substrate. The encapsulant material is cured so as to encapsulate the electronic die. The substrate is cut to separate the packaged electronic die.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: December 27, 2022
    Assignee: Microchip Technology Inc.
    Inventors: Matthias Klein, Andreas Zakrzewski, Richard Gruenwald
  • Patent number: 11538819
    Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers comprise doped silicon dioxide and the second tiers comprise undoped silicon dioxide. Horizontally-elongated trenches are formed into the stack. Through the trenches, the doped silicon dioxide that is in the first tiers is etched selectively relative to the undoped silicon dioxide that is in the second tiers. Conducting material is formed in the void space in the first tiers that is left by the etching. Structure independent of method is disclosed.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Purnima Narayanan
  • Patent number: 11527493
    Abstract: The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a first metal plug, a second metal plug, a third metal plug, and a fourth metal plug over a semiconductor substrate; forming an energy removable liner covering the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug; performing an etching process to remove a portion of the energy removable layer from the substrate, while remaining an energy removable block between the first metal plug and the second metal plug in the cell region; forming a dielectric layer covering the energy removable block and the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug; performing a thermal treating process to transform the energy removable layer into a first air gap structure including a first air gap enclosed by liner layer.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: December 13, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tzu-Ching Tsai
  • Patent number: 11519098
    Abstract: Silicon carbide (SiC) wafers, SiC boules, and related methods are disclosed that provide improved dislocation distributions. SiC boules are provided that demonstrate reduced dislocation densities and improved dislocation uniformity across longer boule lengths. Corresponding SiC wafers include reduced total dislocation density (TDD) values and improved TDD radial uniformity. Growth conditions for SiC crystalline materials include providing source materials in oversaturated quantities where amounts of the source materials present during growth are significantly higher than what would typically be required. Such SiC crystalline materials and related methods are suitable for providing large diameter SiC boules and corresponding SiC wafers with improved crystalline quality.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: December 6, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Yuri Khlebnikov, Robert T. Leonard, Elif Balkas, Steven Griffiths, Valeri Tsvetkov, Michael Paisley
  • Patent number: 11521958
    Abstract: A semiconductor device package includes a redistribution layer, a plurality of conductive pillars, a reinforcing layer and an encapsulant. The conductive pillars are in direct contact with the first redistribution layer. The reinforcing layer surrounds a lateral surface of the conductive pillars. The encapsulant encapsulates the first redistribution layer and the reinforcing layer. The conductive pillars are separated from each other by the reinforcing layer.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: December 6, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ya Fang Chan, Yuan-Feng Chiang
  • Patent number: 11521755
    Abstract: Systems and methods are disclosed for identifying and modeling unresolved vessels, and the effects thereof, in image-based patient-specific hemodynamic models. One method includes: receiving, in an electronic storage medium, one or more patient-specific anatomical models representing at least a vessel of a patient; determining, using a processor, the values and characteristics of one or more patient-specific morphometric features in the one or more patient-specific anatomical models; modifying the patient-specific anatomical model using the determined patient-specific morphometric features; and outputting, one or more of, a modified patient-specific anatomical model or a patient-specific morphometric feature to an electronic storage medium or display.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: December 6, 2022
    Assignee: HeartFlow, Inc.
    Inventors: Charles A. Taylor, Hyun Jin Kim, Leo Grady, Rhea Tombropoulos, Gilwoo Choi, Nan Xiao, David Spain
  • Patent number: 11522070
    Abstract: A manufacturing method of a low temperature poly-silicon (LTPS) array substrate is described. The LTPS array substrate includes a metal light-shielding layer, a buffer layer, a polycrystalline silicon layer, a gate insulating and interlayer insulating layer, a gate line layer, and a source and drain electrode layer. The method adopts a one-time chemical vapor deposition process to form a gate insulator and interlayer insulating layer. A gate line trench is formed in the gate insulating layer and the interlayer insulating layer, thereby reducing the thickness of the LTPS array substrate film layer and the process steps.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: December 6, 2022
    Inventor: Chen Chen