Patents Examined by Nicholas J. Tobergte
  • Patent number: 10818742
    Abstract: A display apparatus includes an insulating layer on a substrate, the substrate including a main through hole, a first groove around and outside the main through hole, and a first test concave portion outside the main through hole, and the insulating layer including a main insulating through hole connected to the main through hole, a first insulating through ring around and outside the main insulating through hole and connected to the first groove, and a first insulating through hole outside the main insulating through hole and connected to the first test concave portion. Along a same width direction: at a same position along the substrate, a width of the first insulating through ring of the insulating layer is less than a width of the first groove of the substrate, and a width of the first insulating through hole is less than a width of the first test concave portion.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: October 27, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yongjun Park, Wooyong Sung, Sunghoon Yang, Seyoon Oh
  • Patent number: 10818621
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip; a passivation layer disposed on the second interconnection member; and an under-bump metal layer including an external connection pad formed on the passivation layer and a plurality of vias connecting the external connection pad and the redistribution layer of the second interconnection member to each other, wherein the first interconnection member includes a redistribution layer electrically connected to the connection pads of the semiconductor chi
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: October 27, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Hwan Lee, Hyoung Joon Kim, Dae Jung Byun
  • Patent number: 10818618
    Abstract: An adhesive substrate includes a support base member and an adhesive layer provided on the support base member. The support base member contains electroconductive particles and an insulating resin, and has a recessed and projected pattern with two or more projected portions on one surface or both surfaces of the support base member. The adhesive layer is provided at least on upper surfaces of the projected portions in the recessed and projected pattern of the support base member. The adhesive layer on the upper surfaces of the projected portions has an upper surface with a curved surface. Thus, the present invention provides an adhesive substrate capable of selectively picking up and quickly transferring large amounts of fine chips and particles, a method for producing the adhesive substrate, and a transfer device.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: October 27, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Hiroyuki Iguchi, Toshio Shiobara, Tsutomu Kashiwagi
  • Patent number: 10818658
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second gate stack formed on the fin structure; a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric layer includes a first portion disposed on a sidewall of the first gate stack with a first thickness and a second portion disposed on a sidewall of the second gate stack with a second thickness greater than the first thickness; a first gate spacer disposed on the first portion of the dielectric material layer; and a second gate spacer disposed on the second portion of the dielectric material layer.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Ying-Keung Leung, Chi On Chui
  • Patent number: 10811600
    Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure has a plurality of sub-layers including one or more metals having non-zero concentrations that change as a distance from the first electrode increases.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin, Wen-Ting Chu
  • Patent number: 10811357
    Abstract: An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Boong Lee, Jung-Ho Do, Tae-Joong Song, Seung-Young Lee, Jong-Hoon Jung, Ji-Su Yu
  • Patent number: 10811337
    Abstract: A semiconductor device includes a first electrode plate, a second electrode plate disposed to oppose the first electrode plate, and a semiconductor chip disposed between the first electrode plate and the second electrode plate. At least one of the first electrode plate and the second electrode plate has a space where a cooling medium circulates.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: October 20, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Shigeaki Hayase
  • Patent number: 10811455
    Abstract: A semiconductor apparatus includes a stack of a first chip having a plurality of pixel circuits arranged in a matrix form and a second chip having a plurality of electric circuit arranged in a matrix form. A wiring path between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit or a positional relationship between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit is differentiated among the electric circuits.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: October 20, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hiroaki Kobayashi, Atsushi Furubayashi, Katsuhito Sakurai
  • Patent number: 10804316
    Abstract: A light emitting diode array is provide to include: a substrate; light emitting diodes positioned over the substrate, each including a first semiconductor layer, an active layer, and a second semiconductor layer, wherein each light emitting diode is disposed to form a first via hole structure exposing a portion of the corresponding first semiconductor layer; lower electrodes disposed over the second semiconductor layer; a first interlayer insulating layer disposed over the lower electrodes and configured to expose the portion of the first semiconductor layer of corresponding light emitting diodes; upper electrodes electrically connected to the first semiconductor layer through the first via hole structure, wherein the first via hole structure is disposed in parallel with one side of the corresponding second semiconductor layer and the first interlayer insulating layer is disposed to form a second via hole structure exposing a portion of the lower electrodes.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: October 13, 2020
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Jong Min Jang, Jong Hyeon Chae, Joon Sup Lee, Daewoong Suh, Hyun A. Kim, Won Young Roh, Min Woo Kang
  • Patent number: 10804435
    Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer emitting an UV light, formed between the first semiconductor layer and the second semiconductor layer; a first transparent conductive layer formed on the second semiconductor layer, the first transparent conductive layer including metal oxide; and a second transparent conductive layer formed on the first transparent conductive layer, the second transparent conductive layer including graphene, wherein the first transparent conductive layer is continuously formed over a top surface of the second semiconductor layer, the first transparent conductive layer comprises a thickness smaller than 10 nm.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: October 13, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chang-Tai Hisao, I-Lun Ma, Hao-Yu Chen, Shu-Fen Hu, Ru-Shi Liu, Chih-Ming Wang, Chun-Yuan Chen, Yih-Hua Renn, Chien-Hsin Wang, Yung-Hsiang Lin
  • Patent number: 10797134
    Abstract: Integrated circuit devices are provided. An integrated circuit device includes a substrate and a device isolation film on the substrate. An active region of the substrate is defined by the device isolation film on the substrate and has a first width in a horizontal direction. A gate electrode is on the active region and has a second width equal to or less than the first width of the active region in the horizontal direction. The integrated circuit device includes an insulating spacer over the device isolation film and the active region.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 6, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Myoung-soo Kim
  • Patent number: 10790136
    Abstract: There is provided a technique that includes (a) forming a film containing silicon, carbon and nitrogen having a carbon concentration within a range from 10 at % to 15 at % on a substrate; (b) performing an oxidation process with respect to the substrate where the film is exposed on a surface thereof; and (c) performing a process using hydrogen fluoride with respect to the substrate where the film is exposed on the surface thereof after the oxidation process is performed.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: September 29, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Tatsuru Matsuoka, Yoshitomo Hashimoto
  • Patent number: 10790340
    Abstract: A display device includes a display panel and an anti-reflection unit directly disposed on the display panel. The display panel includes first to third light emitting elements, each of which includes first and second electrodes, and a light emitting layer, which is disposed between the first electrode and the second electrode. The pixel definition layer includes a first portion, in which a light-emitting opening exposing the first electrode is defined, and a second portion, which is disposed on and overlapped with the first portion. The anti-reflection unit includes first to third color filters overlapped with the first to third light emitting elements, respectively, and a color spacer, which is overlapped with the second portion and is thicker than each of the first to third color filters.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: September 29, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyeonbum Lee, Hyoeng-ki Kim, Kwangwoo Park
  • Patent number: 10790154
    Abstract: Methods and systems for line cut by multi-color patterning techniques are presented. In an embodiment, a method may include providing a substrate. The method may also include forming a first feature on the substrate, the first feature having a cap formed of a first material. Additionally, the method may include forming a second feature on the substrate, the second feature having a cap formed of a second material. In still a further embodiment, the method may include selectively removing the second feature using an etch process that etches the first material at a first etch rate and etches the second material at a second etch rate, wherein the second etch rate is higher than the first etch rate.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: September 29, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Eric Chih-Fang Liu, Akiteru Ko
  • Patent number: 10790787
    Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: September 29, 2020
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Simon John Mahon, Allen W. Hanson, Chuanxin Lian, Frank Gao, Rajesh Baskaran, Bryan Schwitter
  • Patent number: 10784321
    Abstract: The present disclosure relates to a method for manufacturing an OLED device, an OLED device and a display panel. The method for manufacturing the OLED device comprises: forming a first electrode layer on a substrate; forming at least one layer of inorganic film at a position on the first electrode layer corresponding to a pixel defining layer; breaking a first organic layer at an etching angle of the at least one layer of inorganic film when forming the first organic layer; forming the pixel defining layer on the inorganic film; forming the first organic layer on the first electrode layer, the inorganic film and the pixel defining layer; and forming a light emitting layer, a second organic layer and a second electrode layer in this order on the first organic layer.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 22, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Xiaohu Li
  • Patent number: 10777520
    Abstract: A semiconductor memory device includes a circuit chip including a first substrate, peripheral circuit elements which are defined on the first substrate and a first dielectric layer which covers the peripheral circuit elements, and having first pads which are coupled to the peripheral circuit elements, on one surface thereof; a memory chip including a second substrate which is disposed on a base dielectric layer, a memory cell array which is defined on the second substrate and a second dielectric layer which covers the memory cell array, and having second pads which are coupled with the first pads, on one surface thereof which is bonded with the one surface of the circuit chip; a contact passing through the base dielectric layer and the second dielectric layer; and one or more dummy contacts passing through the base dielectric layer and the second dielectric layer, and disposed around the contact.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventors: Go-Hyun Lee, Jae-Taek Kim, Jun-Youp Kim, Chang-Man Son
  • Patent number: 10777636
    Abstract: High density integrated circuit (IC) capacitor structures and fabrication methods that increase the capacitive density of integrated capacitors with little or no reduction in Q-factor by using a stacked high-density integrated capacitor structure that includes substrate-contact (“S-contact”) capacitor plates. Embodiments include a plurality of S-contact plates fabricated in electrical connection with a capacitor formed in a metal interconnect layer. Some embodiments include interstitial S-contact plates to provide additional capacitive density. Embodiments may also utilize single-layer transfer (SLT) and double-layer transfer (DLT) techniques to create ICs with high density, high Q-factor capacitors. Such capacitors can be beneficially combined with other structures made possible in SLT and DLT IC structures, such as metal interconnect layer capacitors and inductors, and one or more FETs having a conductive aligned supplemental gate.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: September 15, 2020
    Assignee: pSemi Corporation
    Inventor: Abhijeet Paul
  • Patent number: 10777521
    Abstract: A printable component structure includes a chiplet having a semiconductor structure with a top side and a bottom side, one or more top electrical contacts on the top side of the semiconductor structure, and one or more bottom electrical contacts on the bottom side of the semiconductor structure. One or more electrically conductive spikes are in electrical contact with the one or more top electrical contacts. Each spike protrudes from the top side of the semiconductor structure or a layer in contact with the top side of the semiconductor structure.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: September 15, 2020
    Assignee: X Display Company Technology Limited
    Inventors: Matthew Meitl, Christopher Bower, Ronald S. Cok
  • Patent number: 10763334
    Abstract: Pursuant to some embodiments of the present invention, transistor devices are provided that include a semiconductor structure, a gate finger extending on the semiconductor structure in a first direction, and a gate interconnect extending in the first direction and configured to be coupled to a gate signal at an interior position of the gate interconnect, where the gate interconnect is connected to the gate finger at a position offset from the interior position of the gate interconnect.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: September 1, 2020
    Assignee: Cree, Inc.
    Inventors: Frank Trang, Zulhazmi Mokhti, Haedong Jang