Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) devices and replacement channel processes for fabricating 3D DRAM devices. In an example, a gate dielectric layer is formed on a sacrificial material, and a gate electrode is formed on the gate dielectric layer. After the gate electrode is formed, the sacrificial material is removed and replaced by a semiconductor material. A channel region of a device (e.g., a transistor) that includes the gate dielectric layer and gate electrode is formed in the semiconductor material. The channel region can be vertical or horizontal with respect to a main surface of a substrate on which the device is formed. A capacitor can be formed, such as before or after the semiconductor material is formed, and is electrically connected to the semiconductor material. The device and the capacitor together can form at least part of a 3D DRAM cell.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

Abstract: Embodiments of the disclosed subject matter provide an emissive layer, a first electrode layer, a plurality of nanoparticles and a material disposed between the first electrode layer and the plurality of nanoparticles. In some embodiments, the device may include a second electrode layer and a substrate, where the second electrode layer is disposed on the substrate, and the emissive layer is disposed on the second electrode layer. In some embodiments, a second electrode layer may be disposed on the substrate, the emissive layer may be disposed on the second electrode layer, the first electrode layer may be disposed on the emissive layer, a first dielectric layer of the material may be disposed on the first electrode layer, the plurality of nanoparticles may be disposed on the first dielectric layer, and a second dielectric layer may be disposed on the plurality of nanoparticles and the first dielectric layer.

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposed to each other, and including an insulation member, a plurality of redistribution layers on different levels in the insulation member, and a redistribution via having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of UBM layers, each including a UBM pad on the first surface of the redistribution substrate, and a UBM via having a shape narrowing in a second direction, opposite to the first direction; and at least one semiconductor chip on the second surface of the redistribution substrate, and having a plurality of contact pads electrically connected to the redistribution layer adjacent to the second surface among the plurality of redistribution layers.

Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface.

Abstract: Provided are compounds, formulations comprising compounds, and devices that utilize compounds, where the devices include a substrate, a first electrode, an organic emissive layer comprising an organic emissive material disposed over the first electrode. The device includes an enhancement layer, comprising a plasmonic material exhibiting surface plasmon resonance that non-radiatively couples to the organic emissive material and transfers excited state energy from the organic emissive material to the non-radiative mode of surface plasmon polaritons. The enhancement layer is provided no more than a threshold distance away from the organic emissive layer, where the organic emissive material has a total non-radiative decay rate constant and a total radiative decay rate constant due to the presence of the enhancement layer. At least one of the organic emissive material and the organic emissive layer has a vertical dipole ratio (VDR) value of equal or greater than 0.33.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

Abstract: In one example, a semiconductor device includes a first conductive feature embedded in a first dielectric layer such that a top surface of the first dielectric layer is higher than a top surface of first conductive feature, a contact etch stop layer (CESL) disposed on the first dielectric layer, and a second conductive feature embedded in a second dielectric layer. The second dielectric layer is disposed on the CESL and the second conductive feature extends through the CESL and is in direct contact with the first conductive feature.

Abstract: A semiconductor device having a redistribution structure and a method of forming the same are provided. A semiconductor device includes a semiconductor structure, a redistribution structure over and electrically coupled the semiconductor structure, and a connector over and electrically coupled to the redistribution structure. The redistribution structure includes a base via and stacked vias electrically interposed between the base via and the connector. The stacked vias are laterally spaced apart from the base via.

Abstract: There are provided a color correction filter for a white organic electroluminescent light source including a resin and 0.1 part by mass or more of a coloring agent having an absorption maximum wavelength in a range of 560 to 620 nm or 460 to 520 nm with respect to 100 parts by mass of the resin, and having a moisture content of 0.5% by mass or less, and an organic EL display device having this filter.

Abstract: The present disclosure provides a semiconductor device package including a first substrate, a second substrate disposed over the first substrate, an electronic component disposed between the first substrate and the second substrate, a spacer disposed between the first substrate and the electronic component, and a supporting element disposed on the first substrate and configured to support the second substrate. The spacer is configured to control a distance between the first substrate and the second substrate through the electronic component. A method of manufacturing a semiconductor device package is also disclosed.

Abstract: Systems and methods are disclosed for identifying and modeling unresolved vessels, and the effects thereof, in image-based patient-specific hemodynamic models. One method includes: receiving, in an electronic storage medium, one or more patient-specific anatomical models representing at least a vessel of a patient; determining, using a processor, the values and characteristics of one or more patient-specific morphometric features in the one or more patient-specific anatomical models; modifying the patient-specific anatomical model using the determined patient-specific morphometric features; and outputting, one or more of, a modified patient-specific anatomical model or a patient-specific morphometric feature to an electronic storage medium or display.

Abstract: An integrated circuit includes a first set of dies, each die comprising circuitry and a second set of interposer dies. At least two dies of the first set of dies are connected to each other via at least one of the interposer dies. The at least one of the interposer dies includes first connections connected to a first die of the first set of dies, second connections connected to a second die of the first set of dies, and buffers connected between the first connections and the second connections. The buffers are configured to condition signals between the first die and the second die.

Abstract: A display panel includes: a substrate including a first area, a second area, and a third area; a stacked structure corresponding to a plurality of display elements in the second area, the stacked structure including a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode; and a plurality of grooves in the third area, wherein the stacked structure includes at least one organic material layer that is disconnected by the plurality of grooves, at least one groove of the plurality of grooves is defined in a first multi-layer including a first lower layer and a first upper layer, and at least one of the first lower layer and the first upper layer includes a plurality of sub-layers.

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The method includes forming a semiconductor chip, forming an electromagnetic shield that covers the semiconductor chip, and forming a molding that covers the electromagnetic shield. The electromagnetic shield is electrically connected to a conductor on a side of the semiconductor chip.

Abstract: A semiconductor device including: a trench defining an active region in a substrate; a first semiconductor liner formed over the trench; a second semiconductor liner formed over the first semiconductor liner; and a device isolation layer formed over the second semiconductor liner and filling the trench. Disclosed is also a method for fabricating a semiconductor device, the method including: forming a trench defining an active region in a substrate; forming a plurality of semiconductor liners over the trench; performing pretreatment before forming each of the semiconductor liners; and performing post-treatment after forming each of the semiconductor liners.

Abstract: A semiconductor structure comprises a gate structure of a transistor. The gate structure comprises a gate conductive portion disposed on a gate dielectric layer. The semiconductor structure further comprises a capacitor structure disposed on the gate structure. The capacitor structure comprises a first conductive layer, a dielectric layer disposed on the first conductive layer and a second conductive layer disposed on the dielectric layer. The first and second conductive layers are respectively connected to a first contact portion and a second contact portion.

Abstract: A protective film forming agent for plasma dicing which can favorably form an opening (processed groove) of a desired shape by irradiation of a laser beam, at a desired position of the protective film, upon producing semiconductor chips by cutting a semiconductor substrate by plasma dicing, and a method for producing a semiconductor chip using this protective film forming agent. The protective film forming agent comprises a water-soluble resin, a light absorber, and a solvent, and a weight loss rate when the temperature is raised to 500° C. in thermogravimetry of the water-soluble resin is at least 80 weight %.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. According to embodiments of the present disclosure, a height of the work function layer, especially a height of the second portion of the work function layer, is significantly increased, and a height of the first gate material layer is significantly reduced, so that the height ratio of the second portion of the work function layer to the first gate material layer to the second gate material layer is maintained at 3 to 8:1 to 1.5:1; therefore, it can be ensured that the work function of the WL groove filling material layer of the recessed gate structure with a small WL width will be significantly increased, thereby greatly weakening the row hammer effect at the bottom of the WL groove and obviously reducing the GIDL effect at the upper part of the WL groove.

Abstract: A package substrate includes an insulating layer having a mounting surface; a wiring pattern extending in the insulating layer; and a chip bonding pad provided on the mounting surface of the insulating layer and connected to the wiring pattern, the chip bonding pad having a tapered shape in which a horizontal cross-sectional area thereof gradually decreases away from the mounting surface of the insulating layer in a vertical direction. A portion of the chip bonding pad closest to the mounting surface of the insulating layer has a horizontal length of about 20 micrometers (?m) to about 30 ?m.