Patents Examined by Nicholas J. Tobergte
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Patent number: 11916020Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.Type: GrantFiled: October 29, 2021Date of Patent: February 27, 2024Assignee: Intel CorporationInventors: Adel A. Elsherbini, Amr Elshazly, Arun Chandrasekhar, Shawna M. Liff, Johanna M. Swan
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Patent number: 11916106Abstract: Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: an array of channel regions, including a first channel region and an adjacent second channel region; a first source/drain region proximate to the first channel region; a second source/drain region proximate to the second channel region; and an insulating material region at least partially between the first source/drain region and the second source/drain region.Type: GrantFiled: July 11, 2022Date of Patent: February 27, 2024Assignee: Intel CorporationInventors: Sean T. Ma, Andy Chih-Hung Wei, Guillaume Bouche
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Patent number: 11916003Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.Type: GrantFiled: September 18, 2019Date of Patent: February 27, 2024Assignee: Intel CorporationInventors: Xiao Lu, Jiongxin Lu, Christopher Combs, Alexander Huettis, John Harper, Jieping Zhang, Nachiket R. Raravikar, Pramod Malatkar, Steven A. Klein, Carl Deppisch, Mohit Sood
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Patent number: 11908773Abstract: An element module includes an element, a plurality of conductive members, and a spacer member. The plurality of conductive members are connected to the element and arranged in a predetermined direction. The spacer member is disposed between two conductive members of the plurality of conductive members adjacent to each other in the predetermined direction and is in contact with parts of the two conductive members.Type: GrantFiled: July 30, 2019Date of Patent: February 20, 2024Assignee: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYSTEMS CORPORATIONInventor: Kento Kuwabara
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Patent number: 11901279Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, an encapsulant and a redistribution structure. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the encapsulant and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wiring layer and a second conductive via stacked along a stacking direction, the first conductive via has a first terminal surface contacting the first conductive wiring layer, the second conductive via has a second terminal surface contacting the first conductive wiring layer, an area of a first cross section of the first conductive via is greater than an area of the first terminal surface of the first conductive via, and an area of a second cross section of the second conductive via is greater than an area of the second terminal surface of the second conductive via.Type: GrantFiled: March 14, 2023Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ting Hung, Meng-Liang Lin, Shin-Puu Jeng, Yi-Wen Wu, Po-Yao Chuang
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Patent number: 11903274Abstract: A display substrate and a display device are provided. In the display substrate, each of the plurality of anode groups includes a first anode and a second anode, the first anode includes a first main body portion, a first connection portion, an extension portion and an anode compensation portion, an orthographic projection of the anode compensation portion on the base substrate covers one thin film transistor, the anode compensation portion has a first point at a side away from the second center line, and the first main body portion has a second point at the first side, the first anode and a connection line between the first point and the second point enclose a notch region, and an area of the notch region is greater than at least one of an area of the anode compensation portion and an area of the first connection portion.Type: GrantFiled: September 10, 2020Date of Patent: February 13, 2024Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Lulu Yang, Tinghua Shang, Guomeng Zhang, Yu Wang, Xiaofeng Jiang, Xin Zhang, Yupeng He, Yi Qu, Biao Liu, Mengmeng Du, Xiangdan Dong, Hongwei Ma
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Patent number: 11901277Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, an encapsulant and a redistribution structure. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the encapsulant and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wiring layer and a second conductive via stacked along a stacking direction, the first conductive via has a first terminal surface contacting the first conductive wiring layer, the second conductive via has a second terminal surface contacting the first conductive wiring layer, an area of a first cross section of the first conductive via is greater than an area of the first terminal surface of the first conductive via, and an area of a second cross section of the second conductive via is greater than an area of the second terminal surface of the second conductive via.Type: GrantFiled: July 3, 2022Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ting Hung, Meng-Liang Lin, Shin-Puu Jeng, Yi-Wen Wu, Po-Yao Chuang
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Patent number: 11903230Abstract: A quantum dot light-emitting device, a manufacturing method and a display device are provided. The quantum dot light-emitting device includes a substrate and a cathode arranged on the substrate; an electron transport layer arranged on one side of the cathode, away from the substrate, wherein the electron transport layer comprises a plurality of pixel regions; an adhesive layer arranged on one side of the electron transport layer, away from the cathode; a quantum dot film layer arranged on one side of the adhesive layer, away from the electron transport layer, wherein both the quantum dot film layer and the adhesive layer are located in the pixel regions; wherein the adhesive layer is respectively connected to the electron transport layer and the quantum dot film layer through at least one of chemical bonding and physical entanglement.Type: GrantFiled: March 30, 2020Date of Patent: February 13, 2024Assignee: BOE Technology Group Co., Ltd.Inventors: Wenhai Mei, Zhenqi Zhang, Aidi Zhang
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Patent number: 11894314Abstract: A semiconductor device has a substrate and an electrical component disposed over a surface of the substrate. An antenna interposer is disposed over the substrate. A first encapsulant is deposited around the antenna interposer. The first encapsulant has a high dielectric constant. The antenna interposer has a conductive layer operating as an antenna and an insulating layer having a low dielectric constant less than the high dielectric constant of the first encapsulant. The antenna interposer is made from an antenna substrate having a plurality of antenna interposers. Bumps are formed over the antenna substrate and the antenna substrate is singulated to make the plurality of antenna interposers. A second encapsulant is deposited over the electrical component. The second encapsulant has a low dielectric constant less than the high dielectric constant of the first encapsulant. A shielding layer is disposed over the second encapsulant.Type: GrantFiled: September 10, 2021Date of Patent: February 6, 2024Assignee: STATS ChipPAC Pte. Ltd.Inventors: HunTeak Lee, Gwang Kim, Junho Ye, YouJoung Choi, MinKyung Kim, Yongwoo Lee, Namgu Kim
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Patent number: 11894293Abstract: A circuit structure and an electronic structure are provided. The circuit structure includes a low-density conductive structure, a high-density conductive structure and an electrical connection structure. The high-density conductive structure is disposed on the low-density conductive structure. The electrical connection structure extends through the high-density conductive structure and is electrically connected to the low-density conductive structure. The electrical connection structure includes a shoulder portion.Type: GrantFiled: July 23, 2021Date of Patent: February 6, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Wen Hung Huang
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Patent number: 11894338Abstract: Provided are a wafer level package and a method of manufacturing the same, wherein an underfill sufficiently fills a space between a redistribution substrate and a semiconductor chip, thereby reducing warpage. The wafer level package includes a redistribution substrate including at least one redistribution layer (RDL), a semiconductor chip on the redistribution substrate, and an underfill filling a space between the redistribution substrate and the semiconductor chip. The underfill covers side surfaces of the semiconductor chip. The redistribution substrate includes a trench having a line shape and extending in a first direction along a first side surface of the semiconductor chip.Type: GrantFiled: February 4, 2022Date of Patent: February 6, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Jinwoo Park, Jungho Park, Dahye Kim, Minjun Bae
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Patent number: 11887936Abstract: A semiconductor device includes a first stack structure on a substrate, and a second stack structure on the first stack structure. A channel structure extends through the first stack structure and the second stack structure. A first auxiliary stack structure including a plurality of first insulating layers and a plurality of first mold layers are alternately stacked on the substrate. An alignment key extends into the first auxiliary stack structure and protrudes to a higher level than an uppermost end of the first stack structure. A second auxiliary stack structure is disposed on the first auxiliary stack structure and the alignment key, and includes a plurality of second insulating layers and a plurality of second mold layers alternately stacked. The second auxiliary stack structure includes a protrusion aligned with the alignment key.Type: GrantFiled: September 9, 2021Date of Patent: January 30, 2024Inventors: Kwanyong Kim, Sungwon Shin, Seungmin Lee, Juyoung Lim, Wonseok Cho
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Patent number: 11887964Abstract: A wafer-level heterogeneous dies integration structure and method are provided. The integration structure includes a wafer substrate, a silicon interposer, heterogeneous dies, and a configuration substrate. A standard integration module is defined by the heterogeneous dies connected to the silicon interposer. The standard integration module is connected to an upper surface of the wafer substrate, and the configuration substrate is connected to a lower surface of the wafer substrate. The wafer substrate is connected to the configuration substrate via Through Silicon Vias on lower surface of the wafer substrate. And the upper surface of the wafer substrate is provided with Re-distributed Layers and a standardized micro bump array to form standard integration zone connected to the standard integration module.Type: GrantFiled: April 11, 2023Date of Patent: January 30, 2024Assignee: ZHEJIANG LABInventors: Shunbin Li, Weihao Wang, Ruyun Zhang, Qinrang Liu, Zhiquan Wan, Jianliang Shen
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Patent number: 11882686Abstract: A method for forming a capacitor includes: providing a substrate with an electric contact portion; forming a supporting layer and a sacrificial layer which are alternately laminated on a surface of the substrate, wherein the topmost layer is a supporting layer; forming a capacitor hole penetrating through the supporting layer and the sacrificial layer and exposing the electric contact portion; forming a bottom electrode layer covering an inner surface of the capacitor hole; forming a protective layer covering a surface of the bottom electrode layer; removing the sacrificial layer, during which the bottom electrode layer being protected by the protective layer; removing the protective layer; and sequentially forming a capacitor dielectric layer and a top electrode layer.Type: GrantFiled: July 13, 2021Date of Patent: January 23, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Wenfeng Wang, Shuangshuang Wu
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Patent number: 11877435Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a first bit line on a substrate; a contact adjacent to the first bit line on the substrate, wherein a first distance between a top portion of the contact and the first bit line is less than a second distance between a lower portion of the contact and the first bit line; a dielectric layer, disposed conformally over the first bit line, the substrate, and the contact; and a first air gap, sealed by the dielectric layer and defined by the first bit line, the substrate and the contact.Type: GrantFiled: January 12, 2022Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Yao-Hsiung Kung
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Patent number: 11869835Abstract: A semiconductor package includes a semiconductor chip, a redistribution structure below the semiconductor chip, a first insulating layer below the redistribution structure, a pad below the first insulating layer, the pad being in contact with the redistribution structure, and a bump below the pad, wherein a horizontal maximum length of an upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.Type: GrantFiled: August 22, 2022Date of Patent: January 9, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Seokhyun Lee, Jongyoun Kim, Yeonho Jang, Jaegwon Jang
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Patent number: 11869845Abstract: A semiconductor wiring substrate includes a first circuit layer, a second circuit layer and a first dielectric layer. The first circuit layer includes a plurality of first signal traces and a plurality of first ground traces, wherein the first signal traces and the first ground traces are alternatively arranged on the first circuit layer, and one of the first signal traces is spaced at a first spacing from adjacent one of the first ground traces. The first dielectric layer is between the first circuit layer and the second circuit layer and has a first thickness in an arrangement direction of the first circuit layer, the first dielectric layer and the second circuit layer, wherein the first spacing substantially ranges from 0.78 to 1.96 times the first thickness.Type: GrantFiled: August 29, 2022Date of Patent: January 9, 2024Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng-Fan Yang, Wei-Chiao Wang, Yi-Tzeng Lin
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Patent number: 11864376Abstract: A method of making a semiconductor device includes forming a first transistor on a substrate, wherein forming the first transistor comprises forming a first source/drain electrode in the substrate. The method further includes forming a second transistor on the substrate, wherein forming the second transistor comprises forming a second source/drain electrode. The method further includes forming an insulating layer extending into the substrate, wherein the insulating layer directly contacts the first source/drain electrode and the second source/drain electrode, a top surface of the insulating layer is above a top surface of the substrate.Type: GrantFiled: July 8, 2021Date of Patent: January 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Shan Wang, Shun-Yi Lee
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Patent number: 11854704Abstract: Systems and methods are disclosed herein for anatomical modeling using information obtained during a medical procedure, whereby an initial anatomical model is generated or obtained, a correspondence is determined between the initial model and additional data and/or measurements from an invasive or noninvasive procedure, and, if a discrepancy is found between the initial model and the additional data, the anatomical model is updated to incorporate the additional data and reduce the discrepancy.Type: GrantFiled: July 15, 2022Date of Patent: December 26, 2023Assignee: HeartFlow, Inc.Inventors: Leo Grady, Charles A. Taylor, Campbell Rogers, Christopher K. Zarins, Gilwoo Choi
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Patent number: 11854986Abstract: A semiconductor device includes a die, an encapsulant over a front-side surface of the die, a redistribution structure on the encapsulant, a thermal module coupled to the back-side surface of the die, and a bolt extending through the redistribution structure and the thermal module. The die includes a chamfered corner. The bolt is adjacent to the chamfered corner.Type: GrantFiled: June 30, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Hua Yu, Wei-Kang Hsieh, Shih-Wei Chen, Tin-Hao Kuo, Hao-Yi Tsai