Abstract: Disclosed is a method of manufacturing a junctionless transistor based on vertically integrated gate-all-around multiple nanowire channels including forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated, forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels, forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels is exposed, and forming a gate dielectric layer on the interlayer dielectric layer to fill the hole, wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole includes depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels which is exposed though the hole.

Abstract: A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material. The trenches individually comprise longitudinally-spaced masked portions and longitudinally-spaced openings in the trenches longitudinally between the masked portions. The trench openings have walls therein extending longitudinally in and along the individual trench openings against laterally-opposing sides of the trenches. At least some of the insulative material that is under the trench openings is removed through bases of the trench openings between the walls and the masked portions to form individual capacitor openings in the insulative material that is lower than the walls. Individual capacitors are formed in the individual capacitor openings. A line of access transistors is formed in the individual trenches. The line of access transistors electrically couples to the individual capacitors that are along that line.

Abstract: A semiconductor device is provided with a semiconductor element having a plurality of electrodes, a plurality of terminals electrically connected to the plurality of electrodes, and a sealing resin covering the semiconductor element. The sealing resin covers the plurality of terminals such that a bottom surface of the semiconductor element in a thickness direction is exposed. A first terminal, which is one of the plurality of terminals, is disposed in a position that overlaps a first electrode, which is one of the plurality of electrodes, when viewed in the thickness direction. The semiconductor device is provided with a conductive connection member that contacts both the first terminal and the first electrode.

Abstract: The present disclosure relates to an RRAM device. In some embodiments, the RRAM device includes a lower electrode disposed over a conductive lower interconnect layer. An upper electrode is over the lower electrode and a multi-layer data storage structure is between the lower and upper electrodes. The multi-layer data storage structure has first and second sub-layers. The first sub-layer has a first metal from a first group of metals, a first concentration of a second metal from a second group of metals, and oxygen. The second sub-layer has a third metal from the first group of metals, a non-zero second concentration of a fourth metal from a second group of metals, and oxygen. The non-zero second concentration is smaller than the first concentration and causes conductive filaments formed within the second sub-layer to be wider than conductive filaments formed within the first sub-layer.

Abstract: Systems and methods are disclosed for identifying and modeling unresolved vessels, and the effects thereof, in image-based patient-specific hemodynamic models. One method includes: receiving, in an electronic storage medium, one or more patient-specific anatomical models representing at least a vessel of a patient; determining, using a processor, the values and characteristics of one or more patient-specific morphometric features in the one or more patient-specific anatomical models; modifying the patient-specific anatomical model using the determined patient-specific morphometric features; and outputting, one or more of, a modified patient-specific anatomical model or a patient-specific morphometric feature to an electronic storage medium or display.

Abstract: A memory device according to an embodiment includes a first conductive layer, a second conductive layer, a third conductive layer intersecting the first conductive layer and the second conductive layer, and a resistance change layer including a first region which is provided between the first conductive layer and the third conductive layer and has a superlattice structure, a second region which is provided between the second conductive layer and the third conductive layer and has the superlattice structure, and a third region which is provided between the first region and the second region. The third region includes at least one element selected from the group consisting of O, F, C, P, B, N, H, Bi, Cd, Zn, Ga, Se, Al, S, Be, In, and Pb. Concentration of the at least one element in the third region is higher than that in the first region and the second region.

Abstract: A method for determining a remaining life span of an elastomer in a motor. The method includes running a downhole tool into a wellbore. The downhole tool includes a mud motor having a rotor and a stator. At least one of the rotor or the stator includes, or is at least partially made from, an elastomer. A number of cycles before the elastomer fails may be predicted. A number of cycles during a time period may be determined. A change in a remaining life span of the elastomer over the time period may be determined, based upon the number of cycles before the elastomer fails and the number of cycles during the time period.

Abstract: A microelectronic package has a microelectronic element overlying or mounted to a first surface of a substrate and substantially rigid conductive posts projecting above the first surface or projecting above a second surface of the substrate remote therefrom. Conductive elements exposed at a surface of the substrate opposite the surface above which the conductive posts project are electrically interconnected with the microelectronic element. An encapsulant overlies at least a portion of the microelectronic element and the surface of the substrate above which the conductive posts project, the encapsulant having a recess or a plurality of openings each permitting at least one electrical connection to be made to at least one conductive post. At least some conductive posts are electrically insulated from one another and adapted to simultaneously carry different electric potentials.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.

Abstract: A numerical controller controls a machine tool that performs a turning on a workpiece on the basis of a cycle instruction indicated by an NC program. The machine tool includes first and second cutter holders that are mutually coupled by a coupling member, and first and second tools are mounted on the cutter holders in mutually opposing fashion. The machine tool performs a turning according to a complex fixed cycle, in a reciprocal fashion rather than unidirectionally, using the first and second tools, and when the turning by the first tool has been completed and the first tool that has performed a turning is withdrawn, it is possible to perform a turning in the opposite direction by the second tool on the opposite side.

Abstract: Systems and methods process a measured ultrasonic response waveform to determine a well casing thickness and an acoustic impedance of a sealing medium surrounding the well casing. An array of simulated response waveforms corresponding to a set of candidate acoustic impedances for the sealing medium surrounding the well casing and a set of candidate well casing thicknesses is generated. A simulated response waveform from the array of simulated response waveforms is identified that best matches the measured response waveform so as to determine the sealing medium acoustic impedance.

Abstract: Systems and methods for model-based optimization of spinal cord stimulation electrodes and devices are disclosed. According to an aspect a method includes providing a patient-specific electroanatomical model including the spine, spinal cord, and a map of target neural elements and non-target neural elements. The method also includes using model electrodes to stimulate the target neural elements. Further, the method includes determining differences in activation thresholds between the target neural elements and the non-target neural elements in a plurality of different configurations of the model electrodes. The method also includes generating an optimal spinal cord stimulation electrode configuration based on the determined differences in activation thresholds.

Abstract: Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal.

Abstract: A semiconductor device includes one nanowire structure disposed on semiconductor substrate and extending in first direction on semiconductor substrate. Each nanowire structure includes plurality of nanowires extending along first direction and arranged in second direction, the second direction being substantially perpendicular to first direction. Each nanowire is spaced-apart from immediately adjacent nanowire. A gate structure extends in third direction over first region of nanowire structure, the third direction being substantially perpendicular to both first direction and second direction. The gate structure includes a gate electrode. Source/drain regions are disposed over second region of nanowire structure, the second region being located on opposing sides of gate structure. The gate electrode wraps around each nanowire.

Abstract: A semiconductor device includes an insulating layer on a substrate, a first channel pattern on the insulating layer and contacting the insulating layer, second channel patterns on the first channel pattern and being horizontally spaced apart from each other, a gate pattern on the insulating layer and surrounding the second channel patterns, and a source/drain pattern between the second channel patterns.

Abstract: A semiconductor device includes: a first bidirectional switch element including a first gate electrode, a second gate electrode, a first electrode, and a second electrode; a first field-effect transistor including a third gate electrode, a third electrode, and a fourth electrode; and a second field-effect transistor including a fourth gate electrode, a fifth electrode, and a sixth electrode. The first electrode is electrically connected to the third gate electrode, the first gate electrode is electrically connected to the third electrode, the second electrode is electrically connected to the fourth gate electrode, the second gate electrode is electrically connected to the fifth electrode, and the fourth electrode is electrically connected to the sixth electrode.

Abstract: A method includes forming first structures on a first portion of a silicon substrate and second structures on a second portion of the substrate; forming spacers on the first structures; forming dummy gates on the first and second structures; depositing a first interlayer dielectric on the dummy gates; removing the dummy gates from the second structures; forming metal gates on the second structures; performing an anneal; forming recess areas in the first interlayer dielectric; removing the spacers from the first structures; epitaxially growing sidewalls on the first structures; removing portions of the first structures outside the dummy gates from the first portion; depositing a second interlayer dielectric on the first portion; removing the dummy gates from the first portion; removing portions of the first structures previously under the dummy gates from the first portion; and forming metal gates on the first structures.

Abstract: A microelectronic device incorporating an air core inductor having one or more inserts to provide efficiency of the inductor are described. One or more inserts having a selected permeability may be placed within regions defined by coils of the air core inductor. The inserts can be formed of a solid material of the selected permeability or such a material can be applied to other structures, such as circuit components. Other embodiments may be described and/or claimed.

Abstract: A method includes forming first structures on a first portion of a silicon substrate and second structures on a second portion of the substrate; forming spacers on the first structures; forming dummy gates on the first and second structures; depositing a first interlayer dielectric on the dummy gates; removing the dummy gates from the second structures; forming metal gates on the second structures; performing an anneal; forming recess areas in the first interlayer dielectric; removing the spacers from the first structures; epitaxially growing sidewalls on the first structures; removing portions of the first structures outside the dummy gates from the first portion; depositing a second interlayer dielectric on the first portion; removing the dummy gates from the first portion; removing portions of the first structures previously under the dummy gates from the first portion; and forming metal gates on the first structures.

Abstract: Disclosed is a method a seismic inversion for petrophysical properties of a subsurface volume comprising the steps of: obtaining petrophysical data relating to valid geological and/or dynamical scenarios, converting this data into valid combinations of elastic parameters; projecting the valid combinations of elastic parameters onto a spherical plot; and determining a penalty term from the distances between each cell of the spherical plot and the nearest valid combination of elastic parameters within the subsurface volume. Valid geological and/or dynamical scenarios comprise those which are petrophysically possible. The penalty term is then used to constrain an inversion minimizing a cost function associated with seismic mismatch between two or more seismic surveys.